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VLSI CIRCUIT AND SYSTEMS
EC-605
EXPERIMENT1
AIM:
To study and design BCD to SEVEN segment display by the use of verilog module.
APPARTUS REQUIERD:
CPLD kit, Computer, Power supply for VLSI platform , JTAGE CABLE.
PROGRAM:
module bcd_seven_seg(bcd_in,seven_seg,tran_in);
input [3:0] bcd_in;
output [5:0]tran_in;
output [6:0] seven_seg;
reg [6:0] seven_seg;
reg [5:0]tran_in;
always@(bcd_in)
begin
case(bcd_in)
4'b0000 : begin seven_seg <= 7'b0111111;tran_in <= 6'b100000; end
4'b0001 : begin seven_seg <= 7'b0000110 ;tran_in <= 6'b100000; end
4'b0010 : begin seven_seg <= 7'b1011011 ;tran_in <= 6'b100000; end
4'b0011 : begin seven_seg <= 7'b1001111 ;tran_in <= 6'b100000; end
4'b0100 : begin seven_seg <= 7'b1100110 ;tran_in <= 6'b100000; end
4'b0101 : begin seven_seg <= 7'b1101101 ;tran_in <= 6'b100000; end
4'b0110 : begin seven_seg <= 7'b1111101 ;tran_in <= 6'b100000; end
4'b0111 : begin seven_seg <= 7'b0000111 ;tran_in <= 6'b100000; end
4'b1000 : begin seven_seg <= 7'b1111111 ;tran_in <= 6'b100000; end
4'b1001 : begin seven_seg <= 7'b1101111 ;tran_in <= 6'b100000; end
4'b1010 : begin seven_seg <= 7'b1110111 ;tran_in <= 6'b100000; end
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VLSI CIRCUIT AND SYSTEMS
EC-6054'b1011 : begin seven_seg <= 7'b1111100 ;tran_in <= 6'b100000; end
4'b1100 : begin seven_seg <= 7'b0111001 ;tran_in <= 6'b100000; end
4'b1101 : begin seven_seg <= 7'b1011110 ;tran_in <= 6'b100000; end
4'b1110 : begin seven_seg <= 7'b1111011 ;tran_in <= 6'b100000; end
4'b1111 : begin seven_seg <= 7'b1110001 ;tran_in <= 6'b100000; end
endcase
end
endmodule
RESULT:
Practical has been performed successfully and the display is shown on the kit.
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605
VIVA VOCE
Ques1: What is seven segment display ?
Ans: Seven segment display is device that displays digits from 0 to 9 in according to programming
Ques2: What is application of seven segment display ?
Ans: It is most widely uses in calculator, digital logic devices and many more.
Ques3: What is VHDL ?
Ans: VHDL stands for VHSIC Hardware Description Language, used to model any digital system.
Ques4: What is VHSIC ?
Ans: VHSIC stands for Very High Speed Integrated Circuit.
Ques5: What is CPLD ?
Ans: CPLD is Complex Programmable Logic Device.
There are 3 types of PLD :
1. SPLD
2. CPLD
3. FPGA
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605
EXPERIMENT2
AIM:
To study and design de_mux_1_4 by the use of verilog module.
APPARTUS REQUIERD:
CPLD kit, Computer , Power supply for VLSI platform , JTAGE cable.
PROGRAM:
module de_mux_1_4(sel,de_mux_in,de_mux_out);
input [1:0] sel;
input de_mux_in;
output [3:0]de_mux_out;
reg [3:0]de_mux_out;
always@(sel or de_mux_in)
begin
case (sel)
2'b00 : de_mux_out[0] <= de_mux_in;
2'b01 : de_mux_out[1] <= de_mux_in;
2'b10 : de_mux_out[2] <= de_mux_in;
2'b11 : de_mux_out[3] <= de_mux_in;
endcase
end
endmodule
RESULT:
Practical has been performed successfully and the display is shown on the kit.
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605
VIVA VOCE
Ques1: What is De multiplexer ?
Ans: De multiplexer is circuit, which has only 1 input and many outputs.
Ques2: What is 1: 4 De multiplexer ?
Ans: It has 1 input and 4 output lines.
Ques3: What do you mean by IEEE ?
Ans: IEEE is Institution for electronic and electrical engineering.
Ques4: What is use of case statement in programming ?
Ans: Case statement selects one of branches for execution, based on the value of the expression.
Ques5: Explain syntax of case statement ?
Ans: Syntax:
case()
when choice 1 = statement;
when choice 2 = statement;
when others = statement;
end case;
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605
EXPERIMENT–3
AIM :
To study and design LED_Flasher by the use of verilog module.
APPARTUS REQUIERD:
CPLD kit, Computer , Power supply for VLSI platform , JTAGE cable.
PROGRAM:
module LED_Flasher(clock,sel,leds,rst);
output [15:0]leds;
reg [15:0]leds;
reg [3:0]counter;
input clock; // 8 MHz system clock
input rst; // External reset
input [2:0]sel; // Output rate select
reg div256;
reg [3:0]cnt1; // Div by 13
reg [7:0]cnt2; // Div by 2 to 256
reg [5:0]cnt3; // Div by 8
wire clk_out;
assign clk_out = cnt3[5];
always@(posedge clock or negedge rst)
begin
if (!rst)
begin
cnt1 <= 8'b0;
end
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605 else if (cnt1 == 4'b1100) // Div by 13
begin
cnt1 <= 4'b0000;
end
else
begin
cnt1 <= cnt1 + 1;
end
end
always@(negedge cnt1[3] or negedge rst)
begin
if (!rst)
cnt2 <= 8'b0; // Div by 2 to 256 based on sel input
else
cnt2 <= cnt2 + 1;
end
always@(negedge cnt1[3] or negedge rst)
begin
if(!rst)
div256 <= 1'b0;
else
begin
case (sel)
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605 3'b000 : div256 <= cnt2[0]; //38.4 KHz {cnt2[0] div bt 2}*8*13 = 208
3'b001 : div256 <= cnt2[1]; //19.2 KHz {cnt2[0] div bt 4}*8*13 = 416
3'b010 : div256 <= cnt2[2]; //9.6 KHz {cnt2[0] div bt 8}*8*13 = 832
3'b011 : div256 <= cnt2[3]; //4.8 KHz {cnt2[0] div bt 16}*8*13 = 1664
3'b100 : div256 <= cnt2[4]; //2.4 KHz {cnt2[0] div bt 32}*8*13 = 3328
3'b101 : div256 <= cnt2[5]; //1.2 KHz {cnt2[0] div bt 64}*8*13 = 6658
3'b110 : div256 <= cnt2[6]; //600 Hz {cnt2[0] div bt 128}*8*13 = 13312
default: div256 <= cnt2[7]; //300 Hz {cnt2[0] div bt 256}*8*13 = 26624
endcase
end
end
always@(posedge div256 or negedge rst)
begin
if (!rst)
cnt3 <= 3'b0; // div by 8
else
cnt3 <= cnt3 + 1;
end
always@(posedge clk_out or negedge rst)
begin
if(!rst)
begin
counter <= 4'b0;
end
else
begin
BI LAB MANUAL AND WORKBOOK 6
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VLSI CIRCUIT AND SYSTEMS
EC-605counter <= counter +1;
end
end
always@(counter)
begin
case (counter)
4'b0000 : leds <= 16'b0000000000000001;
4'b0001 : leds <= 16'b0000000000000010;
4'b0010 : leds <= 16'b0000000000000100;
4'b0011 : leds <= 16'b0000000000001000;
4'b0100 : leds <= 16'b0000000000010000;
4'b0101 : leds <= 16'b0000000000100000;
4'b0110 : leds <= 16'b0000000001000000;
4'b0111 : leds <= 16'b0000000010000000;
4'b1000 : leds <= 16'b1000000000000000;
4'b1001 : leds <= 16'b0100000000000000;
4'b1010 : leds <= 16'b0010000000000000;
4'b1011 : leds <= 16'b0001100000000000;
4'b1100 : leds <= 16'b0000100000000000;
4'b1101 : leds <= 16'b0000010000000000;
4'b1110 : leds <= 16'b0000001000000000;
4'b1111 : leds <= 16'b0000000100000000;
default : leds <= 16'b0000000000000000;
endcase
end
endmodule
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605
VIVA VOCE
Ques1: What do you mean by LED ?
Ans: LED is Light Emitting Diode, which emits light.
Ques2: What is application of LED ?
Ans: LED device is used in many application in digital circuit for display. It works as light source.
Ques3: What is “if” statement ?
Ans: “if” statement executes some statements, when condition is true.
Ques4: Explain syntax of “if” statement ?
Ans: Begin
if (statement)
begin
sequential statements;
end
else
begin
sequential statements;
end
end
Ques5: What is syntax of ieee library ?
Ans: Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_airth.all;
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605
EXPERIMENT – 4
AIM:
To study and design Binay_to_seven_segment by the use of VHDL Module.
APPARTUS REQUIER:
CPLD kit, Computer , Power supply for VLSI platform , JTAGE CABLE.
PROGRAM:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sevenseg_dis is
port(Reset: in std_logic;
Clk : in std_logic;
Segment : out std_logic_vector(6 downto 0);
Base1 : out std_logic_vector(5 downto 0)
);
end sevenseg_dis;
architecture sevenseg_dis_arch of sevenseg_dis is
signal Counter:std_logic_vector(24 downto 0);
signal Bts:std_logic_vector(3 downto 0);
begin
Bts <= Counter(24 downto 21) ;
process(Clk,Reset)
begin
if (Reset='1')then
Counter <= (others =>'0') ;
elsif Clk'event and clk = '1' then
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605 Counter <=Counter +'1';
end if;
end process;
base1<=(others=>'1');
process (Bts)
begin
case Bts is
bcdefg Binary to 7segment decoder
when "0000" => Segment <= "0111111" ; 0
when "0001" => Segment <= "0000110" ; 1
when "0010" => Segment <= "1011011" ; 2
when "0011" => Segment <= "1001111" ; 3
when "0100" => Segment <= "1100110" ; 4
when "0101" => Segment <= "1101101" ; 5
when "0110" => Segment <= "1111101" ; 6
when "0111" => Segment <= "0000111" ; 7
when "1000" => Segment <= "1111111" ; 8
when "1001" => Segment <= "1101111" ; 9
when "1010" => Segment <= "1110111" ; A
when "1011" => Segment <= "1111100" ; B
when "1100" => Segment <= "0111001" ; C
when "1101" => Segment <= "1011110" ; D
when "1110" => Segment <= "1111011" ; E
when "1111" => Segment <= "1110001" ; F
when others => Segment <= "1000000" ; Blank
end case;
BI LAB MANUAL AND WORKBOOK 6
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EC-605 end process;
end sevenseg_dis_arch;
RESULT:
Practical has been performed successfully and the display is shown on the kit.
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605
VIVA VOCE
Ques1: What do you mean by entity declaration ?
Ans: Entity declaration describes external view of an entity. It specifies name of entity and list of interfacing ports
Ques2: Syntax of entity declaration ?
Ans: Entity entity_name is
port (port1, port2 : in bit;
port 3 : out bit); end entity_name;
Ques3: What is function of architecture body ?
Ans: Architecture body contain the internal description of entity.
Ques4: Explain types of data types, used in programming.
Ans: 1.scaler types
2. composite types
3. access type
4. file type
Ques5: Explain types of scaler data type ?
Ans: 1. enumeration
2. composite
3. physical
4. floating point
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605
EXPERIMENT – 5
AIM:
To study and design sevenseg_dis by the use of VHDL Module.
APPARTUS REQUIERD:
CPLD kit, Computer , Power supply for VLSI platform , JTAGE CABLE.
PROGRAM:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sevenseg_dis is
port(Reset: in std_logic;
Clk : in std_logic;
Segment : out std_logic_vector(6 downto 0);
Base1 : out std_logic_vector(5 downto 0)
);
end sevenseg_dis;
architecture sevenseg_dis_arch of sevenseg_dis is
signal Counter:std_logic_vector(24 downto 0);
signal Bts:std_logic_vector(3 downto 0);
begin
Bts <= Counter(24 downto 21) ;
process(Clk,Reset)
begin
if (Reset='1')then
Counter <= (others =>'0') ;
elsif Clk'event and clk = '1' then
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605 Counter <=Counter +'1';
end if;
end process;
base1<=(others=>'1');
process (Bts)
begin
case Bts is
bcdefg Binary to 7segment decoder
when "0000" => Segment <= "0111111" ; 0
when "0001" => Segment <= "0000110" ; 1
when "0010" => Segment <= "1011011" ; 2
when "0011" => Segment <= "1001111" ; 3
when "0100" => Segment <= "1100110" ; 4
when "0101" => Segment <= "1101101" ; 5
when "0110" => Segment <= "1111101" ; 6
when "0111" => Segment <= "0000111" ; 7
when "1000" => Segment <= "1111111" ; 8
when "1001" => Segment <= "1101111" ; 9
when "1010" => Segment <= "1110111" ; A
when "1011" => Segment <= "1111100" ; B
when "1100" => Segment <= "0111001" ; C
when "1101" => Segment <= "1011110" ; D
when "1110" => Segment <= "1111011" ; E
when "1111" => Segment <= "1110001" ; F
when others => Segment <= "1000000" ; Blank
end case;
BI LAB MANUAL AND WORKBOOK 6
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EC-605 end process;
end sevenseg_dis_arch;
RESULT:
Practical has been performed successfully and the display is shown on the kit.
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605
VIVA VOCE
Ques1: What do you mean by IEEE library ?
Ans: A compiled design unit is stored in a design library.
IEEE library contains the package std_logic_1164
Ques2: What do you mean by behavioral modeling ?
Ans: In this modeling, the behavior of entity is defined as a set of sequential statements.
Ques3: What is use of case statement in programming ?
Ans: Case statement selects one of branches for execution, based on the value of the expression.
Ques4: Explain syntax of case statement ?
Ans: Syntax:
case()
when choice 1 = statement;
when choice 2 = statement;
when others = statement;
end case;
Ques5: What is function of architecture body ?
Ans: Architecture body contain the internal description of entity.
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605
EXPERIMENT – 6
AIM:
To study and design bank_token by the use of Verilog Module.
APPARTUS REQUIERD:
CPLD kit, Computer , Power supply for VLSI platform , JTAGE CABLE.
PROGRAM:
module bank_token(number_in,token_out,tran_in);
input [9:0] number_in;
output [6:0]token_out;
output [5:0]tran_in;
reg [6:0]token_out;
reg [5:0]tran_in;
always@(number_in)
begin
case(number_in)
10'b0000000001 : begin token_out <= 7'b0111111; tran_in <= 6'b111111; end
10'b0000000010 : begin token_out <= 7'b0000110; tran_in <= 6'b111111; end
10'b0000000100 : begin token_out <= 7'b1011011; tran_in <= 6'b111111; end
10'b0000001000 : begin token_out <= 7'b1001111; tran_in <= 6'b111111; end
10'b0000010000 : begin token_out <= 7'b1100110; tran_in <= 6'b111111; end
10'b0000100000 : begin token_out <= 7'b1101101; tran_in <= 6'b111111; end
BI LAB MANUAL AND WORKBOOK 6
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VLSI CIRCUIT AND SYSTEMS
EC-60510'b0001000000 : begin token_out <= 7'b1111101; tran_in <=
6'b111111; end
10'b0010000000 : begin token_out <= 7'b0000111; tran_in <= 6'b111111; end
10'b0100000000 : begin token_out <= 7'b1111111; tran_in <= 6'b111111; end
10'b1000000000 : begin token_out <= 7'b1101111; tran_in <= 6'b111111; end
default : begin token_out <= 7'b1000000; tran_in <= 6'b111111; end
endcase
end
endmodule
RESULT: Practical has been performed successfully and the display is shown on the kit.
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605
VIVA VOCE
Ques1: What is use of case statement in programming ?
Ans: Case statement selects one of branches for execution, based on the value of the expression.
Ques2: Explain syntax of case statement ?
Ans: Syntax:
case()
when choice 1 = statement;
when choice 2 = statement;
when others = statement;
end case;
Ques3: What do you mean by data flow modeling ?
Ans: In this modeling, the flow of data through entity is described primarily using concurrent
signal assignment statements.
Ques4: What do you mean by IEEE library ?
Ans: A compiled design unit is stored in a design library.
IEEE library contains the package std_logic_1164
Ques5: What do you mean by entity declaration ?
Ans: Entity declaration describes external view of an entity. It specifies name of entity and list of interfacing ports
EXPERIMENT7
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605
AIM:
To study and design BCD to SEVEN segment display by the use of verilog Module.
APPARTUS REQUIERD:
FPGA kit, Computer , Power supply for VLSI platform , JTAGE CABLE.
PROGRAM:
module bcd_seven_seg(bcd_in,seven_seg,tran_in);
input [3:0] bcd_in;
output [5:0]tran_in;
output [6:0] seven_seg;
reg [6:0] seven_seg;
reg [5:0]tran_in;
always@(bcd_in)
begin
case(bcd_in)
4'b0000 : begin seven_seg <= 7'b0111111;tran_in <= 6'b100000; end
4'b0001 : begin seven_seg <= 7'b0000110 ;tran_in <= 6'b100000; end
4'b0010 : begin seven_seg <= 7'b1011011 ;tran_in <= 6'b100000; end
4'b0011 : begin seven_seg <= 7'b1001111 ;tran_in <= 6'b100000; end
4'b0100 : begin seven_seg <= 7'b1100110 ;tran_in <= 6'b100000; end
4'b0101 : begin seven_seg <= 7'b1101101 ;tran_in <= 6'b100000; end
4'b0110 : begin seven_seg <= 7'b1111101 ;tran_in <= 6'b100000; end
4'b0111 : begin seven_seg <= 7'b0000111 ;tran_in <= 6'b100000; end
4'b1000 : begin seven_seg <= 7'b1111111 ;tran_in <= 6'b100000; end
4'b1001 : begin seven_seg <= 7'b1101111 ;tran_in <= 6'b100000; end
4'b1010 : begin seven_seg <= 7'b1110111 ;tran_in <= 6'b100000; end
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VLSI CIRCUIT AND SYSTEMS
EC-6054'b1011 : begin seven_seg <= 7'b1111100 ;tran_in <= 6'b100000; end
4'b1100 : begin seven_seg <= 7'b0111001 ;tran_in <= 6'b100000; end
4'b1101 : begin seven_seg <= 7'b1011110 ;tran_in <= 6'b100000; end
4'b1110 : begin seven_seg <= 7'b1111011 ;tran_in <= 6'b100000; end
4'b1111 : begin seven_seg <= 7'b1110001 ;tran_in <= 6'b100000; end
endcase
end
endmodule
RESULT:
Practical has been performed successfully and the display is shown on the kit.
Viva Voice
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605
Ques1: Explain syntax of “if” statement ?
Ans: Begin
if (statement)
begin
sequential statements;
end
else
begin
sequential statements;
end
end
Ques2: What is syntax of ieee library ?
Ans: Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_airth.all;
Ques3: What do you mean by entity declaration ?
Ans: Entity declaration describes external view of an entity. It specifies name of entity and list of interfacing ports
Ques4: What is FPGA ?
Ans: FPGA is Field Programmable Gate Array, it is more versatile PLD device as compared
to SPLD & CPLD.
Ques5: What do you mean by data flow modeling ?
Ans: In this modeling, the flow of data through entity is described primarily using concurrent
signal assignment statements.
EXPERIMANT8
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605
AIM:
To study and design de_mux_1_4 by the use of verilog Module.
APPARTUS REQUIERD:
FPGA kit, Computer , Power supply for VLSI platform , JTAGE CABLE.
PROGRAM:
module de_mux_1_4(sel,de_mux_in,de_mux_out);
input [1:0] sel;
input de_mux_in;
output [3:0]de_mux_out;
reg [3:0]de_mux_out;
always@(sel or de_mux_in)
begin
case (sel)
2'b00 : de_mux_out[0] <= de_mux_in;
2'b01 : de_mux_out[1] <= de_mux_in;
2'b10 : de_mux_out[2] <= de_mux_in;
2'b11 : de_mux_out[3] <= de_mux_in;
endcase
end
endmodule
RESULT:
Practical has been performed successfully and the display is shown on the kit
VIVA VOCE
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605
Ques1: What do you mean by entity declaration ?
Ans: Entity declaration describes external view of an entity. It specifies name of entity and list of interfacing ports
Ques2: What is FPGA ?
Ans: FPGA is Field Programmable Gate Array, it is more versatile PLD device as compared
to SPLD & CPLD.
Ques3: Explain syntax of “if” statement ?
Ans: Begin
if (statement)
begin
sequential statements;
end
else
begin
sequential statements;
end
end
Ques4: What is syntax of ieee library ?
Ans: Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_airth.all;
Ques5: What do you mean by data flow modeling ?
Ans: In this modeling, the flow of data through entity is described primarily using concurrent
signal assignment statements.
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605
EXPERIMENT9
AIM:
To study and design LED_Flasher by the use of verilog Module.
APPARTUS REQUIERD:
FPGA kit, Computer , Power supply for VLSI platform , JTAGE CABLE.
PROGRAM:
module LED_Flasher(clock,sel,leds,rst);
output [15:0]leds;
reg [15:0]leds;
reg [3:0]counter;
input clock; // 8 MHz system clock
input rst; // External reset
input [2:0]sel; // Output rate select
reg div256;
reg [3:0]cnt1; // Div by 13
reg [7:0]cnt2; // Div by 2 to 256
reg [5:0]cnt3; // Div by 8
wire clk_out;
assign clk_out = cnt3[5];
always@(posedge clock or negedge rst)
begin
if (!rst)
begin
cnt1 <= 8'b0;
end
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VLSI CIRCUIT AND SYSTEMS
EC-605 else if (cnt1 == 4'b1100) // Div by 13
begin
cnt1 <= 4'b0000;
end
else
begin
cnt1 <= cnt1 + 1;
end
end
always@(negedge cnt1[3] or negedge rst)
begin
if (!rst)
cnt2 <= 8'b0; // Div by 2 to 256 based on sel input
else
cnt2 <= cnt2 + 1;
end
always@(negedge cnt1[3] or negedge rst)
begin
if(!rst)
div256 <= 1'b0;
else
begin
case (sel)
3'b000 : div256 <= cnt2[0]; //38.4 KHz {cnt2[0] div bt 2}*8*13 = 208
3'b001 : div256 <= cnt2[1]; //19.2 KHz {cnt2[0] div bt 4}*8*13 = 416
3'b010 : div256 <= cnt2[2]; //9.6 KHz {cnt2[0] div bt 8}*8*13 = 832
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LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-6053'b011 : div256 <= cnt2[3]; //4.8 KHz {cnt2[0] div bt 16}*8*13 = 1664
3'b100 : div256 <= cnt2[4]; //2.4 KHz {cnt2[0] div bt 32}*8*13 = 3328
3'b101 : div256 <= cnt2[5]; //1.2 KHz {cnt2[0] div bt 64}*8*13 = 6658
3'b110 : div256 <= cnt2[6]; //600 Hz {cnt2[0] div bt 128}*8*13 = 13312
default: div256 <= cnt2[7]; //300 Hz {cnt2[0] div bt 256}*8*13 = 26624
endcase
end
end
always@(posedge div256 or negedge rst)
begin
if (!rst)
cnt3 <= 3'b0; // div by 8
else
cnt3 <= cnt3 + 1;
end
always@(posedge clk_out or negedge rst)
begin
if(!rst)
begin
counter <= 4'b0;
end
else
begin
counter <= counter +1;
end
end
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LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605always@(counter)
begin
case (counter)
4'b0000 : leds <= 16'b0000000000000001;
4'b0001 : leds <= 16'b0000000000000010;
4'b0010 : leds <= 16'b0000000000000100;
4'b0011 : leds <= 16'b0000000000001000;
4'b0100 : leds <= 16'b0000000000010000;
4'b0101 : leds <= 16'b0000000000100000;
4'b0110 : leds <= 16'b0000000001000000;
4'b0111 : leds <= 16'b0000000010000000;
4'b1000 : leds <= 16'b1000000000000000;
4'b1001 : leds <= 16'b0100000000000000;
4'b1010 : leds <= 16'b0010000000000000;
4'b1011 : leds <= 16'b0001100000000000;
4'b1100 : leds <= 16'b0000100000000000;
4'b1101 : leds <= 16'b0000010000000000;
4'b1110 : leds <= 16'b0000001000000000;
4'b1111 : leds <= 16'b0000000100000000;
default : leds <= 16'b0000000000000000;
endcase
end
endmodule
RESULT :
Practical has been performed successfully and the display is shown on the kit.
BI LAB MANUAL AND WORKBOOK 6
LAB MANUAL AND WORK BOOK
VLSI CIRCUIT AND SYSTEMS
EC-605
VIVA VOCE
Ques1: What is FPGA ?
Ans: FPGA is Field Programmable Gate Array, it is more versatile PLD device as compared
to SPLD & CPLD.
Ques2: What do you mean by IEEE ?
Ans: IEEE is Institution for electronic and electrical engineering.
Ques3: What is use of case statement in programming ?
Ans: Case statement selects one of branches for execution, based on the value of the expression.
Ques4: Explain syntax of “if” statement ?
Ans: Begin
if (statement)
begin
sequential statements;
end
else
begin
sequential statements;
end
end
Ques5: What is syntax of ieee library ?
Ans: Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_airth.all;
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LAB MANUAL AND WORK BOOK
