Lecture 7 Mosfet

8/10/2019 Lecture 7 Mosfet

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Electronic DevicesKEEE 2224

Lecture 7

Metal-Oxide-Semiconductor

Field Effect Transistor

Dr. Ghafour Amouzad Mahdiraji

November 2012


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Basic MOSFET Operation

The current in a MOSFET is due to the flow of charge in the inversion layer or

channel region adjacent to the oxide-semiconductor interface.


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Ev

EcEFiEF

EF

Ev

Ec

Metal Oxide p-type

m

s

+--

++

--

m

s

Ev

EcEFi

EFs

EFm

Ev

Ec

Metal Oxide p-type

m< s

Ev

Ec

EFiEF

EF

Ev

Ec

Metal

Oxide

p-type

m

s

---

+++

+++

---


4/21

What VG need to be applied to make

depletion region ON?

What VG need to be applied to make

depletion region OFF?Positive Negative


p-type

+VG

m>

s

p-type

-VG

m<

s

How we can let the current flow in this device?


5/21


p-type

m> s VG= 0

p-type

VG= 0m< s

----

++++-----

++++

----

++++

++++

----


6/21

MOSFET Structures

There are four basic MOSFET device types:

n-channel enhancement mode MOSFET

n-channel depletion mode MOSFET

p-channel enhancement mode MOSFET

p-channel depletion mode MOSFET


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n-Channel MOSFETs

Depletion-type MOSFET:

The device is ON at zero gate voltage.

Enhancement-type MOSFET:

The device is OFF at zero gate voltage.

A +tive gate voltage induces the electron

inversion layer, which then connects the

n-type source to drain regions.

Electron inversion layer exist at 0 V and

can be off with -tive voltage.

The source terminal is the source of carriers that flow through the channel to drain.

In n-channel device, electrons flow from the source to the drain through the channel,

thus, the current directed from drain to source.


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p-Channel MOSFET

p-channel depletion mode MOSFET.p-channel enhancement mode MOSFET

A -tive gate voltage must be applied to

create an inversion layer of holes that

will connect the p-type source to drain

regions.

Electron inversion layer exist at 0 V and

can be off with +tive voltage.

In p-channel device, holes flow from the source to the drain through the channel,

thus, the current directed from source to drain.


9/21

Current-Voltage Relationship

Considering a n-channel enhancement mode MOSFET with a gate-to-

source (or gate-to-semiconductor) voltage that is less than the threshold

voltage and with only a very small drain-to-source voltage.

The source and substrate terminals are held at ground potential.

With this bias configuration, there is no electron inversion layer, the

drain-to-substrate pn junction is reverse biased, and the drain current is

zero (regardless of pn junction leakage current).


10/21

Current-Voltage Relationship

n-channel enhancement mode MOSFET with an applied gate voltage VGS>

VT.

An electron inversion layer has been created so that when a small drain

voltage is applied, the electrons in the inversion layer will flow from the

source to the positive drain terminal. Thus the current is from drain to source.


11/21

Field Effect on Transistor Current

For small VDSvalues, the channel region has

the characteristics of a resistor, so

The inversion layer charge is a function of the gate voltage; thus, the basic MOS

transistor action is the modulation of the channel conductance by the gate voltage.

If VGS< VTno inversion layer ID = 0

If VGS> VTchannel inversion charge density increases channel conductance

increaselarger ID.

DSdD VgI

where gd is the channel conductance in the limit

as VDS0.

The channel conductance is given by

nnd QL

Wg '

where n is the mobility of the electrons in the

inversion layer and |Q'n| is the magnitude of the

inversion layer charge per unit area.


12/21

Voltage (VDS

) Effect on Current

(a): VGS> VTand VDS is small

The thickness of the inversion channel

layer in the Fig qualitatively indicates

the relative charge density, which isconstant along the entire channel .

(b):VGS> VTand VDS is larger than case (a)

As the drain voltage increases, the

voltage drop across the oxide near the

drain terminal, which means the induced

inversion charge density near the drain

also decreases.

Channel conductance at the drain

decreases, which means the slop of the

ID versus VDScurve will decrease.


13/21

Voltage (VDS

) Effect on Current

where VDS(sat) is the drain-to-source voltage producing zero inversion charge density

at the drain terminal.

(c): VGS> VTand VDS= VDS(sat) When VDS increases to the point

where the potential drop across the

oxide (at the drain terminal voltage is

equal to VT

), the induced inversion

charge density get zero at the drain

terminal.

At this point, the incremental

conductance at the drain is zero, which

means that the slope of the ID versusVDScurve is zero.

TDSGS VVV )sat(

TGSDS VVV )sat(


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Voltage (VDS

) Effect on Current

(d):VGS> VTand VDS> VDS(sat)is larger

than case (a)

When VDSbecomes larger than

VDS(sat), the point in the channel atwhich the inversion charge is just zero

moves toward the source terminal.

In this case, electrons enter the channel at the source, travel through the channeltoward the drain, and then, at the point where the charge goes to zero, the electrons

are injected into the space charge region where they are swept by the E-field to the

drain contact.

If assuming the change in channel lengthL is small, then the drain current will be a

constant for VDS> VDS(sat). This region is referred as the saturation region.


15/21

Family of ID

versus VDS

Now, if VGSchanges, the ID versus VDScurve will change.

Considering following equation, where

VDS(sat) is a function of VGS.

A family of curves can be generated for thisn-channel enhancement mode MOSFET.

TGSDS VVV )sat(


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ID

Vrs VDS

in n-Channel Depletion Mode MOSFET

In n-channel depletion mode MOSFET, an induced electron inversion layer exist at zero

gate voltage.

The current-voltage characteristics in depletion-type is exactly the same as theenhancement-type MOSFET, except that VT is a negative quantity.

In depletion-type, a -tive gate voltage required to reduce the thickness of the n-channel

region and also the drain current.

One basic requirement for this device is that the channel thickness tc

must be less than

the maximum induced space charge width in order to be able to turn the device off.


17/21

MOSFET Transistor Current The operation of a p-channel device is the same as that of the n-channel, except the charge

carrier is the hole and the conventional current direction & voltage polarities are reversed.

2)(2

2 DSDSTGS

oxnD VVVV

LCWI

When the transistor is biased in the

saturation region, the ideal current-

voltage relation is given by:

2)(2

)sat(TGS

oxn

D VVL

CWI

2)(2DSDSTGSnD

VVVVKI

where Kn

= (WnCox

)/2L is called the

conduction parameter for the n-channel

MOSFET with units of A/V2.

2)()sat(TGSnD

VVKI

or

or

n-channel MOSFET

In the nonsaturation region

2)(2

2 DSDSTGS

oxpD VVVV

L

CWI

2)(2DSDSTGSpD

VVVVKI or

2)(2

)sat(TGS

oxp

D VVL

CWI

2)()sat(TGSpD

VVKI or

p-channel MOSFET


18/21

Example Design the width of a MOSFET such that a specified current is induced for a given

applied bias.

Consider an ideal n-channel MOSFET with parametersL = 1.25 m, n = 650 cm2/V-

s, Cox = 6.9 10-8 F/cm2, and VT= 0.65 V. Design the channel width Wsuch that

ID(sat) = 4 mA for VGS= 5 V.


19/21

Complementary MOS (or CMOS) Devices

We have discussed both n-channel and p-channel enhancement MOSFETs.

When both devices are used in a circuit, they form a Complementary MOS

(or CMOS).

CMOS inverter is one of the basis of CMOS digital logic circuits.

The dc power dissipation in a digital circuit can be reduced to very low

levels by using a complementary p-channel and n-channel pair.

Usually, such devices fabricated in one cheep using integrated circuit. It is

necessary to form electrically isolated p- and n-substrate regions in anintegrated circuit to accommodate the n- and p-channel transistors.


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Example of CMOS Structures


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CMOS Inverter

For small values of the input voltage, VIN, the nMOS transistor is switched off,

whereas the pMOS transistor is switched on and connects the output mode to VDD.

For large values of the input voltage, VIN, the pMOS transistor is switched off,

whereas the nMOS transistor is switched on and connects the output mode to GND= 0V.

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Lecture 7 Mosfet