Lecture5 Ee689 Termination Txdriver

8/10/2019 Lecture5 Ee689 Termination Txdriver

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Sam Palermo

Analog & Mixed-Signal Center

Texas A&M University

ECEN689: Special Topics in High-Speed

Links Circuits and SystemsSpring 2012

Lecture 5: Termination, TX Driver, & Multiplexer Circuits


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Announcements & Agenda

Lab 1 Report and Pre-lab 2 due Thursday Reading

Papers posted on voltage-mode drivers and

high-order TX multiplexer circuits Termination Circuits

TX Driver Circuits

TX circuit speed limitations Clock distribution

Multiplexing techniques

2


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High-Speed Electrical Link System

3


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Termination

Off-chip vs on-chip

Series vs parallel

DC vs AC Coupling Termination circuits

4


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Off-Chip vs On-Chip Termination

5

Package parasitics act as an unterminated stubwhich sends reflections back onto the line

On-chip termination makes package inductancepart of transmission line

[Dally]


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Series vs Parallel Termination

6

Series Termination Parallel Termination

Double Termination

Low impedance voltage-mode driver typically employs

series termination

High impedance current-mode driver typically employsparallel termination

Double termination yields best signal quality

Done in majority of high performance serial links


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AC vs DC Coupled Termination

7

DC coupling allows foruncoded data

RX common-mode setby transmitter signal

level

AC coupling allows forindependent RX

common-mode level Now channel has low

frequency cut-off

Data must be coded

RX Common-Mode = IR/2

RX Common-Mode = VTT


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Passive Termination

Choice of integrated resistors involves trade-offs in manufacturingsteps, sheet resistance, parasitic capacitance, linearity, and ESDtolerance

Integrated passive termination resistors are typically realized withunsalicided poly, diffusion, or n-well resistors

Poly resistors are typically used due to linearity and tightertolerances, but they typically vary +/-30% over process andtemperature

8

Resistor Poly N-diffusion N-well

Sheet R (/sq) 9010 30050 450200

VC1(V-1) 0 10-3 8x10-3

Parasitic Cap2-3fF/um2

(min L poly)

0.9fF/um2(area),

0.04fF/um (perimeter)

0.2fF/um2(area),

0.7fF/um (perimeter)

Resistor Options (90nm CMOS)


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Active Termination

Transistors must be used fortermination in CMOS processeswhich dont provide resistors

Triode-biased FET works well

for low-swing (


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Adjustable Termination

FET resistance is afunction of gateoverdrive

10

( )( )tGSoxFET

VVLWC

R

=

1

Large variance in FET threshold voltage requiresadjustable termination structures

Calibration can be done with an analog controlvoltage or through digital trimming

Analog control reduces VGSand linear range

Digital control is generally preferred

[Dally]


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Termination Digital Control Loop

Off-chip precision resistor is used as reference

On-chip termination is varied until voltages are within

an LSB Dither filter typically used to avoid voltage noise

Control loop may be shared among several links, butwith increased nanometer CMOS variation per-channel

calibration may be necessary 11

[Dally]


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High-Speed Electrical Link System

12


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TX Driver Circuits

Single-ended vs differential signaling

Current-mode drivers

Voltage-mode drivers

Slew-rate control

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Single-Ended Signaling

Finite supply impedancecauses significantSimultaneous SwitchingOutput (SSO) noise

(xtalk)

Necessitates largeamounts of decoupling

capacitance for suppliesand reference voltage

Decap limits I/O area morethat circuitry

14


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Differential Signaling

A difference between voltage or current is sent betweentwo lines

Requires 2x signal lines relative to single-ended signaling,but less return pins

Advantages Signal is self-referenced

Can achieve twice the signal swing

Rejects common-mode noise

Return current is ideally only DC

15

[Sidiropoulos]


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Current vs Voltage-Mode Driver

Signal integrity considerations (min. reflections) requires50driver output impedance

To produce an output drive voltage Current-mode drivers use Norton-equivalent parallel termination

Easier to control output impedance

Voltage-mode drivers use Thevenin-equivalent seriestermination Potentially to the current for a given output swing

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D+

D-

2VSWVZcont

D+

D-

Current-Mode Voltage-Mode


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Push-Pull Current-Mode Driver

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Used in Low-Voltage Differential Signals (LVDS) standard

Driver current is ideally constant, resulting in low dI/dt noise

Dual current sources allow for good PSRR, but headroom can be aproblem in low-voltage technologies

Differential peak-to-peak RX swing is IR with double termination


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Current-Mode Logic (CML) Driver

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Used in most high performance serial links

Low voltage operation relative to push-pull driver High output common-mode keeps current source saturated

Can use DC or AC coupling

AC coupling requires data coding

Differential pp RX swing is IR/2 with double termination


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Current-Mode Current Levels

19

( )

( )

R

VI

ppd,=

=

=

=

IRV

RIV

RIV

ppd

d

d

,

0,

1,

2

2Single-Ended Termination

Differential Termination( )( )

( )( )

R

VI

ppd,=

=

=

=

IRV

RIV

RIV

ppd

d

d

,

0,

1,

24

24


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Voltage-Mode Current Levels

20

( )( )

( )

2R

VI ppd,=

=

=

=

=

RVI

VV

VV

VV

s

sppd

sd

sd

2

2

2

,

1,

1,Single-Ended Termination

Differential Termination( )

( )

( )

4R

VI

ppd,=

=

=

=

=

RVI

VVVV

VV

s

sppd

sd

sd

4

2

2

,

1,

1,


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Current-Mode vs Voltage-Mode Summary

An ideal voltage-mode driver with differential RXtermination enables a potential4x reduction indriver power

Actualdriver power levels also depend on Output impedance control

Pre-driver power

Equalization implementation21

Driver/Termination Current Level Normalized Current Level

Current-Mode/SE Vd,pp/Z0 1x

Current-Mode/Diff Vd,pp/Z0 1x

Voltage-Mode/SE Vd,pp/2Z0 0.5x

Voltage-Mode/Diff Vd,pp/4Z0 0.25x


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Voltage-mode driver implementation depends on outputswing requirements

For low-swing (

Low-Swing Voltage-Mode Driver High-Swing Voltage-Mode Driver


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Low-Swing VM Driver Impedance Control

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A linear regulator sets the output stage supply, Vs Termination is implemented by output NMOS transistors

To compensate for PVT and varying output swing levels, the pre-drivesupply is adjusted with a feedback loop

The top and bottom output stage transistors need to be sized

differently, as they see a different VOD

[Poulton JSSC 2007]


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High-Swing VM Driver Impedance Control

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High-swing voltage-mode driver termination is

implemented with a combination of output drivertransistors and series resistors

To meet termination resistance levels (50), large outputtransistors are required

Degrades potential power savings vs current-mode driver

[Kossel JSSC 2008] [Fukada ISSCC 2008]

(Segmented for 4-tap

TX equalization)


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TX Driver Slew Rate Control

Output transition times should be controlled Too slow

Limits max data rate

Too fast

Can excite resonant circuits, resulting in ISI due to ringing

Cause excessive crosstalk

Slew rate control reduces reflections and

crosstalk

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Slew Rate Control w/ Segmented Driver

Slew rate control can be implemented with a segmentedoutput driver

Segments turn-on time are spaced by 1/n of desiredtransition time

Predriver transition time should also be controlled 26

Voltage-Mode Driver

[Wilson JSSC 2001][Dally]

Current-Mode Driver


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Current-Mode Driver Example

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Voltage-Mode Driver Example

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TX Circuit Speed Limitations

High-speed links can be limited by both the channeland the circuits

Clock generation and distribution is key circuitbandwidth bottleneck

Multiplexing circuitry also limits maximum data rate

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TX Multiplexer Full Rate

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Tree-muxarchitecture withcascaded 2:1 stagesoften used

Full-rate architecturerelaxes clock duty-cycle, but limits maxdata rate

Need to generate anddistribute high-speedclock

Need to design high-speed flip-flop


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TX Multiplexer Half Rate

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Half-rate architectureeliminates high-speedclock and flip-flop

Output eye is sensitive toclock duty cycle

Critical path no longer hasflip-flop setup time

Final mux control isswapped to prevent

output glitches Can also do this in

preceding stages forbetter timing margin


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Clock Distribution Speed Limitations

Max clock frequency thatcan be efficiently distributedis limited by clock buffersability to propagate narrowpulses

CMOS buffers are limited toa min clock period near8FO4 inverter delays About 4GHz in typical 90nm

CMOS Full-rate architecture limited

to this data rate in Gb/s

Need a faster clock usefaster clock buffers CML CML w/ inductive peaking

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Clock Amplitude Reduction*

*C.-K. Yang, Design of High-Speed Serial Links inCMOS," 1998.

tFO4in 90nm ~ 30ps

faster slower


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Multiplexing Techniques Rate

Full-rate architecture islimited by maximum clockfrequency to 8FO4 Tb

To increase data rateseliminate final retiming anduse multiple phases of aslower clock to mux data

Half-rate architecture uses 2clock phases separated by

180to mux data Allows for 4FO4Tb

180phase spacing (duty cycle)critical for uniform output eye

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2:1 CMOS Mux

2:1 CMOS mux able to propagate a minimum pulse near2FO4 Tb

However, with a -rate architecture still limited byclock distribution to 4FO4 Tb 8Gb/s in typical 90nm 35

*C.-K. Yang, Design of High-Speed Serial Links in CMOS," 1998.

faster slower


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Increasing Multiplexing Factor Rate

Increase multiplexingfactor to allow for lowerfrequency clockdistribution

-rate architecture

4-phase clock distributionspaced at 90allows for2FO4 Tb

90phase spacing and dutycycle critical for uniformoutput eye

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Increasing Multiplexing Factor Mux Speed

Higher fan-in muxes run slowerdue to increased cap at mux node

-rate architecture

4:1 CMOS mux can potentially

achieve 2FO4 Tbwith low fanout An aggressive CMOS-style design has

potential for 16Gb/s in typical 90nmCMOS

1/8-rate architecture

8-phase clock distribution spaced at45allows for 1FO4 Tb

No way a CMOS mux can achievethis!!

38*C.-K. Yang, Design of High-Speed Serial Links in CMOS," 1998.


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High-Order Current-Mode Output-Multiplexed

8:1 current-mode mux directly at output pad

Makes sense if output time constant smallerthan on-chip time constant

Very sensitive to clock phase spacing

Yang achieved 6Gb/s in 0.35m CMOS Equivalent to 33Gb/s in 90nm CMOS (now channel

(not circuit) limited)

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outout C= 25

Bit Time (FO4)

Reduction

*C.-K. Yang, Design of High-Speed Serial Links in CMOS," 1998.


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Current-Mode Input-Multiplexed

Reduces output capacitance relative to output-multiplexeddriver

Easier to implement TX equalization

Not sensitive to output stage current mismatches

Reduces power due to each mux stage not having to besized to deliver full output current

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[Lee JSSC 2000] faster slower


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Next Time

Receiver Circuits RX parameters

RX static amplifiers

Clocked comparators Circuits

Characterization techniques

Integrating receivers

RX sensitivity

Offset correction

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Lecture5 Ee689 Termination Txdriver