Low Power Low Noise RRI/O 1.8V CMOS Op-Amp

OPA2314-EP

www.ti.com.cn ZHCSAA2 –SEPTEMBER 2012

3MHz，，低低功功耗耗，，低低噪噪声声，，轨轨到到轨轨输输入入输输出出 (RRI/O)，，1.8V CMOS 运运算算放放大大器器

查查询询样样品品: OPA2314-EP

1特特性性• 低低 IQ：：150µA/ch（（最最大大值值））支支持持国国防防、、航航空空航航天天、、和和医医疗疗应应用用• 宽宽电电源源电电压压：：1.8V 至至 5.5V • 受受控控基基线线

• 低低噪噪声声：： 1kHz 下下为为 14nV/√Hz • 一一个个组组装装或或测测试试场场所所

• 增增益益带带宽宽：：3MHz • 一一个个制制造造场场所所

• 低低输输入入偏偏置置电电流流：：0.2pA • 支支持持扩扩展展（（-40°C 至至 150°C））温温度度范范围围 (1)

• 低低偏偏移移电电压压：：0.5mV • 延延长长的的产产品品生生命命周周期期

• 单单位位增增益益稳稳定定 • 延延长长的的产产品品变变更更通通知知

• 内内部部射射频频 (RF) / 电电磁磁干干扰扰 (EMI) 滤滤波波器器 • 产产品品可可追追溯溯性性

应应用用范范围围

• 电电池池供供电电仪仪器器：：

– 消消费费类类应应用用、、工工业业应应用用、、医医疗疗应应用用

– 笔笔记记本本电电脑脑、、便便携携式式媒媒体体播播放放器器

• 光光电电二二极极管管放放大大器器

• 有有源源滤滤波波器器

• 远远程程感感测测

• 无无线线仪仪表表

• 手手持持测测试试设设备备 (1) 可提供额外温度范围-请与厂家联系

说说明明

OPA2314 是一款双通道运算放大器并且代表了新一代低功耗、通用 CMOS 放大器。轨到轨输入和输出摆幅，低

静态电流（在

VS时为 5.0V 时的典型值为 150μA）与 3MHz 的宽带宽和极低噪声（1kHz 时为 14nV/√Hz）组合在一起使得这个

系列对于要求在成本和性能间达到很好平衡的多种电池供电类应用具有很大的吸引力。低输入偏置电流支持带有兆

欧级源阻抗的应用。

OPA2314 器件的稳健耐用设计方便了电路设计人员的使用：负载电容高达 300pF 时单位增益稳定、一个集成的

RF/EMI 抑制滤波器、在过驱情况下无相位反转、以及高静电放电 (ESD) 保护（4kV 人体模型 (HBM)）。

这个器件针对低至 +1.8V (±0.9V) 和最高 +5.5V (±2.75V) 的低压运行进行了优化，并且其额定运行温度范围为 -40°C 至 +150°C 的完全扩展温度范围。

OPA2314（双通道）采用四方扁平无引线（DFN)-8 封装。

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright © 2012, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does not English Data Sheet: SBOS597necessarily include testing of all parameters.

http://www.ti.com.cn/product/cn/opa2314-ep?qgpn=opa2314-ep

http://www.ti.com.cn

http://www.ti.com.cn/product/cn/opa2314-ep#samples

http://www-s.ti.com/sc/techlit/SBOS597.pdf

OPA2314-EP

ZHCSAA2 –SEPTEMBER 2012 www.ti.com.cn

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION (1)

TA PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING VID NUMBER

-40°C to 150°C DFN-8 – DRB OPA2314ASDRBTEP OUVS V62/12626-01XE

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com.

ABSOLUTE MAXIMUM RATINGS (1)

Over operating free-air temperature range, unless otherwise noted.

UNIT

Supply voltage 7 V

Voltage (2) (V–) – 0.5 to (V+) + 0.5 VSignal input terminals

Current (2) ±10 mA

Output short-circuit (3) Continuous mA

Operating temperature, TA –40 to +150 °C

Storage temperature, Tstg –65 to +150 °C

Junction temperature, TJ +170 °C

Human body model (HBM) 4000 V

ESD rating Charged device model (CDM) 1000 V

Machine model (MM) 200 V

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyondthose specified is not supported.

(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails shouldbe current limited to 10 mA or less.

(3) Short-circuit to ground, one amplifier per package.

2 Copyright © 2012, Texas Instruments Incorporated



http://www.ti.com

OPA2314-EP


ELECTRICAL CHARACTERISTICS: VS = +1.8 V to +5.5 V (1)

Boldface limits apply over the specified temperature range: TA = –40°C to +150°C.At TA = +25 °C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.

PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT

OFFSET VOLTAGE

VOS Input offset voltage VCM = (VS+) – 1.3 V 0.5 2.5 mV

Over temperature TA = –40°C to +150°C 3.5 mV

dVOS/dT vs Temperature 1 μV/°C

PSRR vs Power supply VCM = (VS+) – 1.3 V 78 92 dB

VS = 5.5 V, (VS–) – 0.2 V < TA = –40°C to +150°C 72 dBVCM < (VS+) – 1.3 V

Channel separation, dc At dc 10 µV/V

INPUT VOLTAGE RANGE

VCM Common-mode voltage range (V–) – 0.2 (V+) + 0.2 V

VS = 1.8 V, (VS–) – 0.2 V < VCM < (VS+) – 1.3 V, 68 86 dBTA = –40°C to +150°C

VS = 5.5 V, (VS–) – 0.2 V < VCM < (VS+) – 1.3 V,CMRR Common-mode rejection ratio 71 90 dBTA = –40°C to +150°C

VS = 5.5 V, VCM = –0.2 V to 5.7 V (2), 60TA = –40°C to +150°C

INPUT BIAS CURRENT

IB Input bias current ±0.2 ±10 pA

Over temperature TA = –40°C to +150°C ±2 nA

IOS Input offset current ±0.2 ±10 pA

Over temperature TA = –40°C to +150°C ±2 nA

NOISE

Input voltage noise (peak-to- f = 0.1 Hz to 10 Hz 5 μVPPpeak)

f = 10 kHz 13 nV/√Hzen Input voltage noise density

f = 1 kHz 14 nV/√Hz

in Input current noise density f = 1 kHz 5 fA/√Hz

INPUT CAPACITANCE

Differential VS = 5.0 V 1 pFCIN

Common-mode VS = 5.0 V 5 pF

OPEN-LOOP GAIN

VS = 1.8 V, 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ 90 115 dB

VS = 5.5 V, 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ 100 128 dBAOL Open-Loop Voltage Gain

VS = 1.8 V, 0.5 V < VO < (V+) – 0.5 V, RL = 2 kΩ 90 100 dB

VS = 5.5 V, 0.5 V < VO < (V+) – 0.5 V, RL = 2 kΩ 94 110 dB

VS = 5.5 V, 0.2 V < VO < (V+) – 0.2 V, RL = 10 kΩ 90 110 dBOver temperature

VS = 5.5 V, 0.5 V < VO < (V+) – 0.2 V, RL = 2 kΩ 100 dB

Phase margin VS = 5.0 V, G = +1, RL = 10 kΩ 65 deg

(1) Parameters with MIN and/or MAX specification limits are 100% production tested, unless otherwise noted.(2) Limits are based on characterization and statistical analysis; not production tested.

Copyright © 2012, Texas Instruments Incorporated 3



OPA2314-EP


ELECTRICAL CHARACTERISTICS: VS = +1.8 V to +5.5 V(1) (continued)Boldface limits apply over the specified temperature range: TA = –40°C to +150°C.At TA = +25 °C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.

PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT

FREQUENCY RESPONSE

VS = 1.8 V, RL = 10 kΩ, CL = 10 pF 2.7 MHzGBW Gain-bandwidth product

VS = 5.0 V, RL = 10 kΩ, CL = 10 pF 3 MHz

SR Slew rate (3) VS = 5.0 V, G = +1 1.5 V/μs

To 0.1%, VS = 5.0 V, 2-V step , G = +1 2.3 μstS Settling time

To 0.01%, VS = 5.0V, 2-V step , G = +1 3.1 μs

Overload recovery time VS = 5.0 V, VIN × Gain > VS 5.2 μs

Total harmonic distortion +THD+N VS = 5.0 V, VO = 1 VRMS, G = +1, f = 1 kHz, RL = 10 kΩ 0.001 %noise (4)

OUTPUT

VS = 1.8 V, RL = 10 kΩ 5 15 mV

VS = 5.5 V, RL = 10 kΩ 5 20 mVVoltage output swing from supplyVO rails VS = 1.8 V, RL = 2 kΩ 15 30 mV

VS = 5.5 V, RL = 2 kΩ 22 40 mV

VS = 5.5 V, RL = 10 kΩ 30 mVOver temperature

VS = 5.5 V, RL = 2 kΩ 60 mV

ISC Short-circuit current VS = 5.0 V ±20 mA

RO Open-loop output impedance VS = 5.5 V, f = 100 Hz 570 Ω

POWER SUPPLY

VS Specified voltage range 1.8 5.5 V

VS = 1.8 V, IO = 0 mA 130 180 µAIQ Quiescent current per amplifier

VS = 5.0 V, IO = 0 mA 150 190 µA

Over temperature VS = 5.0 V, IO = 0 mA 220 µA

Power-on time VS = 0 V to 5 V, to 90% IQ level 44 µs

TEMPERATURE

Specified range –40 +150 °C

Operating range –40 +150 °C

Storage range –65 +150 °C

(3) Signifies the slower value of the positive or negative slew rate.(4) Third-order filter; bandwidth = 80 kHz at –3 dB.

THERMAL INFORMATIONOPA2314ASDRBTEP

THERMAL METRIC (1) DRB (DFN) UNITS

8 PINS

θJA Junction-to-ambient thermal resistance 53.8

θJC(top) Junction-to-case(top) thermal resistance 69.2

θJB Junction-to-board thermal resistance 20.1°C/W

ψJT Junction-to-top characterization parameter 3.8

ψJB Junction-to-board characterization parameter 20.0

θJC(bottom) Junction-to-case(bottom) thermal resistance 11.6

(1) 有关传统和新的热度量的更多信息，请参阅IC 封装热度量应用报告， SPRA953。




http://www.ti.com/cn/lit/pdf/spra953

0.10

1.00

10.00

100.00

1000.00

10000.00

80 100 120 140 160 180 200

Es

tim

ate

d L

ife

(Y

ea

rs)

Continuous TJ (°C)

Wirebond VoidingFail Mode

Electromigration Fail Mode

OUT A

-IN A

+IN A

V-

1

2

3

4

V+

OUT B

-IN B

+IN B

8

7

6

5

ExposedThermalDie Pad

onUnderside(2)

OPA2314-EP


PIN CONFIGURATIONS

DRB PACKAGE(1)

DFN-8(TOP VIEW)

(1) Pitch: 0,65mm.

(2) Connect thermal pad to V–. Pad size: 1,8mm × 1,5mm.

xxxxxxxx

(1) See datasheet for absolute maximum and minimum recommended operating conditions.

(2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnectlife).

(3) Enhanced plastic product disclaimer applies.

Figure 1. OPA2314-EP Operating Life Derating Chart




12

10

8

6

4

2

0

Perc

ent of A

mplif

iers

(%

)

Offset Voltage (mV)

-1.4

-1.3

-1.2

-1.1

-1.0

-0.9

-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1 0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0 1.1

1.2

1.3

1.4

30

25

20

15

10

5

0

Pe

rce

nt

of

Am

plif

iers

(%

)

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Offset Voltage Drift ( V/ C)m °

180

170

160

150

140

130

120

110

100

90

80

Quie

scent C

urr

ent (

A/C

h)

m

1.5 2 2.5 3 3.5 4 4.5 5 5.5 6

Supply Voltage (V)

115

120

125

130

135

140

145

150

155

160

±50 ±25 0 25 50 75 100 125 150

Qui

esce

nt C

urre

nt (

A/C

h)

Temperature (C) C002

VS = 5.5 V

VS = 1.8 V

140

120

100

80

60

40

20

0

20-

0

20-

-

-

-

-

-

-

-

40

60

80

100

120

140

160

Gain

(dB

) Phase (

)°

101 100 1k 10k 100k 1M 10M

Frequency (Hz)

R = 10 k /10 pF

V = 2.5 V

WL

S ±

100

110

120

130

±50 ±25 0 25 50 75 100 125 150

Ope

n-Lo

op G

ain

(dB

)


N 9

N 9

N 9

OPA2314-EP


TYPICAL CHARACTERISTICSAt TA = +25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.

OPEN-LOOP GAIN AND PHASE OPEN-LOOP GAINvs FREQUENCY vs TEMPERATURE

Figure 2. Figure 3.

QUIESCENT CURRENT QUIESCENT CURRENTvs SUPPLY vs TEMPERATURE

Figure 4. Figure 5.

OFFSET VOLTAGE PRODUCTION DISTRIBUTION OFFSET VOLTAGE DRIFT DISTRIBUTION

Figure 6. Figure 7.




100

10

Vo

lta

ge

No

ise

(n

v/

)ÖH

z

10 100 1k 10k 100k

Frequency (Hz)

V = ±2.75 VS

V = ±0.9 VS

Vo

lta

ge

(0

.5V

/div

)m

Time (1 s/div)

120

100

80

60

40

20

0

Co

mm

on

-Mo

de

Re

jectio

n R

atio (

dB

),

Po

we

r-S

up

ply

Re

jectio

n R

atio

(d

B)

10 100 1k 10k 100k 1M

Frequency (Hz)

V = ±2.75 VS

+PSRR

PSRR-

CMRR

84

89

94

99

104

109

114

119

±50 ±25 0 25 50 75 100 125 150

Com

mon

-Mod

e R

ejec

tion

Rat

io (

dB)

Pow

er S

uppl

y R

ejec

tion

Rat

io (

dB)


CMRR

PSRR

1000

800

600

400

200

0

200

400

600

800

1000

-

-

-

-

-

Offse

t V

oltag

e (

V)

m

-2.75 0-2 -1.25 -0.5 0.5 1.25 2 2.75

Common-Mode Voltage (V)

Typical Units

V = ±2.75 VS

±800

±600

±400

±200

0

200

400

600

800

±50 ±25 0 25 50 75 100 125 150

Offs

et V

olta

ge (

V)


Typical Units VS = 2.75 V

OPA2314-EP


TYPICAL CHARACTERISTICS (continued)At TA = +25°C, RL = 10 kΩ connected to VS/2, VCM = VS/2, and VOUT = VS/2, unless otherwise noted.

OFFSET VOLTAGE vs COMMON-MODE VOLTAGE OFFSET VOLTAGE vs TEMPERATURE

Figure 8. Figure 9.

CMRR AND PSRR CMRR AND PSRRvs FREQUENCY (Referred-to-Input) vs TEMPERATURE

Figure 10. Figure 11.

INPUT VOLTAGE NOISE SPECTRAL DENSITY0.1-Hz to 10-Hz INPUT VOLTAGE NOISE vs FREQUENCY





40

20

0

20-

Ga

in (

dB

)

10k 100k 1M 10M

Frequency (Hz)

G = 1 V/V-

G = +1 V/V

G = +10 V/V

V = 1.8 VS

Ou

tpu

t V

olt

ag

e S

win

g (

V)

Output Current (mA)-3

-2

-1

0

1

2

3

5 10 15 20 25 37.6 30 35

-40°C+25°C+125°C

+150°C

6

5

4

3

2

1

0

Vo

lta

ge

(V

)P

P

10k 100k 1M 10M

Frequency (Hz)

V = 5.5 VIN

IN

IN

V = 3.3 V

V = 1.8 V

R = 10 k

C = 10 pF

WL

L

100k

10k

1k

1

Ou

tpu

t Im

pe

da

nce

()

W

1 10 100 1k 10k 100k 1M 10M

Frequency (Hz)

V = ±2.75 VS

V = ±0.9 VS

1000

900

800

700

600

500

400

300

200

100

0

Inp

ut

Bia

s C

urr

en

t (p

A)

-50 -25 0 25 50 75 100 125 150

Temperature (°C)

IOS

IB

0 1 2 3 4 5

Common-Mode Input Voltage (V)

0.5 1.5 2.5 3.5 4.5 5.5

20

18

16

14

12

10

Voltage N

ois

e (

nV

/)

ÖH

z

V = ±2.75 V

f = 1 kHzS

OPA2314-EP



VOLTAGE NOISE INPUT BIAS AND OFFSET CURRENTvs COMMON-MODE VOLTAGE vs TEMPERATURE


OPEN-LOOP OUTPUT IMPEDANCE MAXIMUM OUTPUT VOLTAGEvs FREQUENCY vs FREQUENCY AND SUPPLY VOLTAGE


OUTPUT VOLTAGE SWINGvs OUTPUT CURRENT (OVER TEMPERATURE) CLOSED-LOOP GAIN vs FREQUENCY





Time (1 s/div)m

1

0.75

0.5

0.25

0

0.25

0.5

0.75

1

-

-

-

-

Voltage (

V)

Gain = +1

V = ±0.9 V

R = 10 kW

S

L

VIN

VOUT

Time (1 s/div)m

2

1.5

1

0.5

0

0.5

1

1.5

2

-

-

-

-

Voltage (

V)

Gain = +1

V = ±2.75 V

R = 10 kW

S

LVIN

VOUT

Vo

lta

ge

(2

5 m

V/d

iv)

Time (1 s/div)m

Z

ZL

L

= 10 pF + 10 kW

= 100 pF + 10 kW

Gain = +1

V = ±0.9 V

R = 10 kW

S

FVIN

Vo

lta

ge

(2

5 m

V/d

iv)

Time (1 s/div)m

Z

ZL

L

= 10 pF + 10 kW

= 100 pF + 10 kW

Gain = +1

V = ±2.75 V

R = 10 kW

S

FVIN

40

20

0

20-

Ga

in (

dB

)

10k 100k 1M 10M

Frequency (Hz)

G = 1 V/V-

G = +1 V/V

G = +10 V/V

V = 5.5 VS

0 200 400 600 800 1000 1200

Capacitive Load (pF)

70

60

50

40

30

20

10

0

Ove

rsh

oo

t (%

)

V = ±2.75 V

Gain = +1 V/V

R = 10 kW

S

L

OPA2314-EP



CLOSED-LOOP GAIN vs FREQUENCY SMALL-SIGNAL OVERSHOOT vs LOAD CAPACITANCE


SMALL-SIGNAL PULSE RESPONSE (NONINVERTING) SMALL-SIGNAL PULSE RESPONSE (INVERTING)


LARGE-SIGNAL PULSE RESPONSE (NONINVERTING) LARGE-SIGNAL PULSE RESPONSE (INVERTING)





0.1

0.01

0.001

0.0001

Tota

l H

arm

onic

Dis

tort

ion +

Nois

e (

%)

0.01 0.1 1 10

Output Amplitude ( )VRMS

V = ±2.5 V

f = 1 kHz

BW = 80 kHz

G = +1 V/V

S

Load = 2 kW

Load = 10 kW

0.1

0.01

0.001

0.0001

Tota

l H

arm

onic

Dis

tort

ion +

Nois

e (

%)

0.01 0.1 1 10

Output Amplitude ( )VRMS

V = ±2.5 V

f = 1 kHz

BW = 80 kHz

G = 1 V/V

S

-

Load = 2 kW

Load = 10 kW

4

3

2

1

0

1

2

3

4

-

-

-

-

0 250 500 750 1000

Time (125 s/div)m

Vo

lta

ge

(1

V/d

iv)

V

VIN

OUT

-

-

-

-

60

80

100

120

140-

Ch

an

ne

l S

ep

ara

tio

n (

dB

)

100 1k 10k 100k 1M 10M

Frequency (Hz)

V = 2.75 VS ±

0 2 4 6 8 10 12 14

Time (2 s/div)m

3

2.5

2

1.5

1

0.5

0

0.5

1

-

-

Voltage (

0.5

V/d

iv)

Input

Output

0 2 4 6 8 10 12 14

Time (2 s/div)m

1

0.5

0

0.5

1

-

-

-

-

-

-

1.5

2

2.5

3

Voltage (

0.5

V/d

iv)

Input

Output

OPA2314-EP



POSITIVE OVERLOAD RECOVERY NEGATIVE OVERLOAD RECOVERY


CHANNEL SEPARATION vs FREQUENCYNO PHASE REVERSAL OPA2314


THD+N vs OUTPUT AMPLITUDE THD+N vs OUTPUT AMPLITUDE(G = +1 V/V) (G = –1 V/V)





0.1

0.01

0.001

0.0001

Tota

l H

arm

on

ic D

isto

rtio

n +

No

ise

(%

)

10 100 1k 10k 100k

Frequency (Hz)

V = ±2.5 V

V = 0.5 V

BW = 80 kHz

G = +1 V/V

S

OUT RMS

Load = 2 kW

Load = 10 kW

0

10

20

30

40

50

60

70

80

90

100

110

120

10M 100M 1G 10GFrequency (Hz)

EM

IRR

IN+

(dB

)

PRF = −10 dBmVS = ±2.5 VVCM = 0 V

G001

OPA2314-EP



ELECTROMAGNETIC INTERFERENCE REJECTION RATIOTHD+N vs FREQUENCY Referred to Noninverting Input (EMIRR IN+) vs FREQUENCY





Reference

Current

V+

VIN-

VIN+

V

(Ground)

-

VBIAS2

VBIAS1 Class AB

Control

Circuitry

VO

OPA2314-EP


APPLICATION INFORMATION

The OPA2314 is a low-power, rail-to-rail input/output operational amplifier specifically designed for portableapplications. This device operates from 1.8 V to 5.5 V, is unity-gain stable, and suitable for a wide range ofgeneral-purpose applications. The class AB output stage is capable of driving ≤ 10-kΩ loads connected to anypoint between V+ and ground. The input common-mode voltage range includes both rails, and allows theOPA2314 to be used in virtually any single-supply application. Rail-to-rail input and output swing significantlyincreases dynamic range, especially in low-supply applications, and makes them ideal for driving samplinganalog-to-digital converters (ADCs).

The OPA2314 features 3-MHz bandwidth and 1.5-V/μs slew rate with only 150-μA supply current per channel,providing good ac performance at very low power consumption. DC applications are also well served with a verylow input noise voltage of 14 nV/√Hz at 1 kHz, low input bias current (0.2 pA), and an input offset voltage of0.5 mV (typical).

Operating Voltage

The OPA2314 is fully specified and ensured for operation from +1.8 V to +5.5 V. In addition, many specificationsapply from –40°C to +150°C. Parameters that vary significantly with operating voltages or temperature are shownin the Typical Characteristics graphs. Power-supply pins should be bypassed with 0.01-μF ceramic capacitors.

Rail-to-Rail Input

The input common-mode voltage range of the OPA2314 extends 200 mV beyond the supply rails. Thisperformance is achieved with a complementary input stage: an N-channel input differential pair in parallel with aP-channel differential pair, as shown in Figure 34. The N-channel pair is active for input voltages close to thepositive rail, typically (V+) – 1.3 V to 200 mV above the positive supply, while the P-channel pair is on for inputsfrom 200 mV below the negative supply to approximately (V+) – 1.3 V. There is a small transition region, typically(V+) – 1.4 V to (V+) – 1.2 V, in which both pairs are on. This 200-mV transition region can vary up to 300 mVwith process variation. Thus, the transition region (both stages on) can range from (V+) – 1.7 V to (V+) – 1.5 Von the low end, up to (V+) – 1.1 V to (V+) – 0.9 V on the high end. Within this transition region, PSRR, CMRR,offset voltage, offset drift, and THD may be degraded compared to device operation outside this region.

Figure 34. Simplified Schematic




5kW

10mA max

V+

VIN

VOUT

IOVERLOAD

OPA2314

OPA2314-EP


Input and ESD Protection

The OPA2314 incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the case ofinput and output pins, this protection primarily consists of current steering diodes connected between the inputand power-supply pins. These ESD protection diodes also provide in-circuit, input overdrive protection, as longas the current is limited to 10 mA as stated in the Absolute Maximum Ratings. Figure 35 shows how a seriesinput resistor may be added to the driven input to limit the input current. The added resistor contributes thermalnoise at the amplifier input and its value should be kept to a minimum in noise-sensitive applications.

Figure 35. Input Current Protection

Common-Mode Rejection Ratio (CMRR)

CMRR for the OPA2314 is specified in several ways so the best match for a given application may be used; seethe Electrical Characteristics. First, the CMRR of the device in the common-mode range below the transitionregion [VCM < (V+) – 1.3 V] is given. This specification is the best indicator of the capability of the device whenthe application requires use of one of the differential input pairs. Second, the CMRR over the entire common-mode range is specified at (VCM = –0.2 V to 5.7 V). This last value includes the variations seen through thetransition region (see Figure 8).

EMI Susceptibility and Input Filtering

Operational amplifiers vary with regard to the susceptibility of the device to electromagnetic interference (EMI). Ifconducted EMI enters the op amp, the dc offset observed at the amplifier output may shift from its nominal valuewhile EMI is present. This shift is a result of signal rectification associated with the internal semiconductorjunctions. While all op amp pin functions can be affected by EMI, the signal input pins are likely to be the mostsusceptible. The OPA2314 operational amplifier incorporates an internal input low-pass filter that reduces theamplifiers response to EMI. Both common-mode and differential mode filtering are provided by this filter. Thefilter is designed for a cutoff frequency of approximately 80 MHz (–3 dB), with a roll-off of 20 dB per decade.

Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operationalamplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. The EMI rejection ratio (EMIRR)metric allows op amps to be directly compared by the EMI immunity. Figure 33 shows the results of this testingon the OPAx314. Detailed information can also be found in the application report, EMI Rejection Ratio ofOperational Amplifiers (SBOA128), available for download from the TI website.

Rail-to-Rail Output

Designed as a micro-power, low-noise operational amplifier, the OPA2314 delivers a robust output drivecapability. A class AB output stage with common-source transistors is used to achieve full rail-to-rail output swingcapability. For resistive loads up to 10 kΩ, the output swings typically to within 5 mV of either supply railregardless of the power-supply voltage applied. Different load conditions change the ability of the amplifier toswing close to the rails, as can be seen in the typical characteristic graph, Output Voltage Swing vs OutputCurrent.




http://www.ti.com/cn/lit/pdf/SBOA128

VIN

VOUT

V+

RS

10 to

20

W

WR

LC

L

OPA2314

OPA2314-EP


Capacitive Load and Stability

The OPA2314 is designed to be used in applications where driving a capacitive load is required. As with all opamps, there may be specific instances where the OPA2314 can become unstable. The particular op amp circuitconfiguration, layout, gain, and output loading are some of the factors to consider when establishing whether ornot an amplifier is stable in operation. An op amp in the unity-gain (+1-V/V) buffer configuration that drives acapacitive load exhibits a greater tendency to be unstable than an amplifier operated at a higher noise gain. Thecapacitive load, in conjunction with the op amp output resistance, creates a pole within the feedback loop thatdegrades the phase margin. The degradation of the phase margin increases as the capacitive loading increases.When operating in the unity-gain configuration, the OPA2314 remains stable with a pure capacitive load up toapproximately 1 nF. The equivalent series resistance (ESR) of some very large capacitors (CL greater than 1 μF)is sufficient to alter the phase characteristics in the feedback loop such that the amplifier remains stable.Increasing the amplifier closed-loop gain allows the amplifier to drive increasingly larger capacitance. Thisincreased capability is evident when observing the overshoot response of the amplifier at higher voltage gains.See the typical characteristic graph, Small-Signal Overshoot vs. Capacitive Load.

One technique for increasing the capacitive load drive capability of the amplifier operating in a unity-gainconfiguration is to insert a small resistor, typically 10 Ω to 20 Ω, in series with the output, as shown in Figure 36.This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. One possibleproblem with this technique, however, is that a voltage divider is created with the added series resistor and anyresistor connected in parallel with the capacitive load. The voltage divider introduces a gain error at the outputthat reduces the output swing.

Figure 36. Improving Capacitive Load Drive

DFN Package

The OPA2314 (dual version) uses the DFN style package (also known as SON); this package is a QFN withcontacts on only two sides of the package bottom. This leadless package maximizes printed circuit board (PCB)space and offers enhanced thermal and electrical characteristics through an exposed pad. One of the primaryadvantages of the DFN package is its low, 0.9-mm height. DFN packages are physically small, have a smallerrouting area, improved thermal performance, reduced electrical parasitics, and use a pinout scheme that isconsistent with other commonly-used packages, such as SO and MSOP. Additionally, the absence of externalleads eliminates bent-lead issues.

The DFN package can easily be mounted using standard PCB assembly techniques. See Application Note,QFN/SON PCB Attachment (SLUA271) and Application Report, Quad Flatpack No-Lead Logic Packages(SCBA017), both available for download from the TI website at www.ti.com.

NOTE: The exposed leadframe die pad on the bottom of the DFN package should be connected to themost negative potential (V-).




http://www.ti.com/cn/lit/pdf/SLUA271

http://www.ti.com/cn/lit/pdf/SLUA271

http://www.ti.com/cn/lit/pdf/SCBA017

http://www.ti.com/cn/lit/pdf/SCBA017

http://www.ti.com

RG

RF

R2R1

C2

VIN

VOUT1

2pRCf =-3 dB

C1

R R = R

C C = C

Q = Peaking factor

(Butterworth Q = 0.707)

1

1 2

2=

=

RG = ( (RF

2 -

1

Q

RG RF

R1

C1

VIN

VOUT

= 1 +V

VOUT

IN

R

RF

G

1

1 + sR C1 1( (( (

1

2pR C1 1

f =-3 dB

OPA2314-EP


APPLICATION EXAMPLES

General Configurations

When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.The simplest way to establish this limited bandwidth is to place an RC filter at the noninverting terminal of theamplifier, as Figure 37 illustrates.

Figure 37. Single-Pole Low-Pass Filter

If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for thistask, as Figure 38 shows. For best results, the amplifier should have a bandwidth that is eight to 10 times thefilter frequency bandwidth. Failure to follow this guideline can result in phase shift of the amplifier.

Figure 38. Two-Pole Low-Pass Sallen-Key Filter




PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish MSL Peak Temp(3)

Op Temp (°C) Top-Side Markings(4)

Samples

OPA2314ASDRBREP PREVIEW SON DRB 8 3000 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 150 OUVS

OPA2314ASDRBTEP ACTIVE SON DRB 8 250 Green (RoHS& no Sb/Br)


V62/12626-01XE ACTIVE SON DRB 8 250 Green (RoHS& no Sb/Br)


(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is acontinuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

http://www.ti.com/product/OPA2314-EP?CMP=conv-poasamples#samplebuy

http://www.ti.com/product/OPA2314-EP?CMP=conv-poasamples#samplebuy

http://www.ti.com/productcontent

PACKAGE OPTION ADDENDUM

www.ti.com 11-Apr-2013

Addendum-Page 2

OTHER QUALIFIED VERSIONS OF OPA2314-EP :

• Catalog: OPA2314

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

http://focus.ti.com/docs/prod/folders/print/opa2314.html

www.ti.com

PACKAGE OUTLINE

C

8X 0.350.25

2.4 0.052X

1.95

1.65 0.05

6X 0.65

1 MAX

8X 0.50.3

0.050.00

A 3.12.9

B

3.12.9

(0.2) TYP

VSON - 1 mm max heightDRB0008BPLASTIC SMALL OUTLINE - NO LEAD

4218876/A 12/2017

PIN 1 INDEX AREA

SEATING PLANE

0.08 C

1

4 5

8

(OPTIONAL)PIN 1 ID 0.1 C A B

0.05 C

THERMAL PADEXPOSED

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

SCALE 4.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MINALL AROUND

0.07 MAXALL AROUND

8X (0.3)

(2.4)

(2.8)

6X (0.65)

(1.65)

( 0.2) VIATYP

(0.575)

(0.95)

8X (0.6)

(R0.05) TYP


4218876/A 12/2017

SYMM

1

45

8

LAND PATTERN EXAMPLESCALE:20X

NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.

SOLDER MASKOPENINGSOLDER MASK

METAL UNDER

SOLDER MASKDEFINED

METALSOLDER MASKOPENING

SOLDER MASK DETAILS

NON SOLDER MASKDEFINED

(PREFERRED)

www.ti.com

EXAMPLE STENCIL DESIGN

(R0.05) TYP

8X (0.3)

8X (0.6)

(1.47)

(1.06)

(2.8)

(0.63)

6X (0.65)


4218876/A 12/2017

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

81% PRINTED SOLDER COVERAGE BY AREASCALE:25X

SYMM

1

4 5

8

METALTYP

SYMM

重重要要声声明明

德州仪器 (TI) 公司有权按照最新发布的 JESD46 对其半导体产品和服务进行纠正、增强、改进和其他修改，并不再按最新发布的 JESD48 提供任何产品和服务。买方在下订单前应获取最新的相关信息，并验证这些信息是否完整且是最新的。

TI 公布的半导体产品销售条款 (http://www.ti.com/sc/docs/stdterms.htm) 适用于 TI 已认证和批准上市的已封装集成电路产品的销售。另有其他条款可能适用于其他类型 TI 产品及服务的使用或销售。

复制 TI 数据表上 TI 信息的重要部分时，不得变更该等信息，且必须随附所有相关保证、条件、限制和通知，否则不得复制。TI 对该等复制文件不承担任何责任。第三方信息可能受到其它限制条件的制约。在转售 TI 产品或服务时，如果存在对产品或服务参数的虚假陈述，则会失去相关 TI 产品或服务的明示或暗示保证，且构成不公平的、欺诈性商业行为。TI 对此类虚假陈述不承担任何责任。

买方和在系统中整合 TI 产品的其他开发人员（总称“设计人员”）理解并同意，设计人员在设计应用时应自行实施独立的分析、评价和判断，且应全权负责并确保应用的安全性，及设计人员的应用（包括应用中使用的所有 TI 产品）应符合所有适用的法律法规及其他相关要求。设计人员就自己设计的应用声明，其具备制订和实施下列保障措施所需的一切必要专业知识，能够 (1) 预见故障的危险后果，(2) 监视故障及其后果，以及 (3) 降低可能导致危险的故障几率并采取适当措施。设计人员同意，在使用或分发包含 TI 产品的任何应用前，将彻底测试该等应用和和该等应用所用 TI 产品的功能而设计。

TI 提供技术、应用或其他设计建议、质量特点、可靠性数据或其他服务或信息，包括但不限于与评估模块有关的参考设计和材料（总称“TI 资源”），旨在帮助设计人员开发整合了 TI 产品的应用，如果设计人员（个人，或如果是代表公司，则为设计人员的公司）以任何方式下载、访问或使用任何特定的 TI 资源，即表示其同意仅为该等目标，按照本通知的条款使用任何特定 TI 资源。

TI 所提供的 TI 资源，并未扩大或以其他方式修改 TI 对 TI 产品的公开适用的质保及质保免责声明；也未导致 TI 承担任何额外的义务或责任。TI 有权对其 TI 资源进行纠正、增强、改进和其他修改。除特定 TI 资源的公开文档中明确列出的测试外，TI 未进行任何其他测试。

设计人员只有在开发包含该等 TI 资源所列 TI 产品的应用时，才被授权使用、复制和修改任何相关单项 TI 资源。但并未依据禁止反言原则或其他法理授予您任何TI知识产权的任何其他明示或默示的许可，也未授予您 TI 或第三方的任何技术或知识产权的许可，该等产权包括但不限于任何专利权、版权、屏蔽作品权或与使用TI产品或服务的任何整合、机器制作、流程相关的其他知识产权。涉及或参考了第三方产品或服务的信息不构成使用此类产品或服务的许可或与其相关的保证或认可。使用 TI 资源可能需要您向第三方获得对该等第三方专利或其他知识产权的许可。

TI 资源系“按原样”提供。TI 兹免除对资源及其使用作出所有其他明确或默认的保证或陈述，包括但不限于对准确性或完整性、产权保证、无屡发故障保证，以及适销性、适合特定用途和不侵犯任何第三方知识产权的任何默认保证。TI 不负责任何申索，包括但不限于因组合产品所致或与之有关的申索，也不为或对设计人员进行辩护或赔偿，即使该等产品组合已列于 TI 资源或其他地方。对因 TI 资源或其使用引起或与之有关的任何实际的、直接的、特殊的、附带的、间接的、惩罚性的、偶发的、从属或惩戒性损害赔偿，不管 TI 是否获悉可能会产生上述损害赔偿，TI 概不负责。

除 TI 已明确指出特定产品已达到特定行业标准（例如 ISO/TS 16949 和 ISO 26262）的要求外，TI 不对未达到任何该等行业标准要求而承担任何责任。

如果 TI 明确宣称产品有助于功能安全或符合行业功能安全标准，则该等产品旨在帮助客户设计和创作自己的符合相关功能安全标准和要求的应用。在应用内使用产品的行为本身不会配有任何安全特性。设计人员必须确保遵守适用于其应用的相关安全要求和标准而设计。设计人员不可将任何 TI 产品用于关乎性命的医疗设备，除非已由各方获得授权的管理人员签署专门的合同对此类应用专门作出规定。关乎性命的医疗设备是指出现故障会导致严重身体伤害或死亡的医疗设备（例如生命保障设备、心脏起搏器、心脏除颤器、人工心脏泵、神经刺激器以及植入设备）。此类设备包括但不限于，美国食品药品监督管理局认定为 III 类设备的设备，以及在美国以外的其他国家或地区认定为同等类别设备的所有医疗设备。

TI 可能明确指定某些产品具备某些特定资格（例如 Q100、军用级或增强型产品）。设计人员同意，其具备一切必要专业知识，可以为自己的应用选择适合的产品，并且正确选择产品的风险由设计人员承担。设计人员单方面负责遵守与该等选择有关的所有法律或监管要求。

设计人员同意向 TI 及其代表全额赔偿因其不遵守本通知条款和条件而引起的任何损害、费用、损失和/或责任。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122Copyright © 2018 德州仪器半导体技术（上海）有限公司

http://www.ti.com/sc/docs/stdterms.htm

Documents

Low Power Low Noise RRI/O 1.8V CMOS Op-Amp