M. Bruschi-CSN1 Napoli 21 Settembre 2005 1 A. Bertin, M. Bruschi, S. De Castro, L. Fabbri, P. Faccioli, B. Giacobbe, F. Grimaldi, I. Massa, M. Piccinini,

M. Bruschi-CSN1 Napoli 21 Settembre 2005

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A. Bertin, M. Bruschi, S. De Castro, L. Fabbri, P. Faccioli, B. Giacobbe, F. Grimaldi, I. Massa, M. Piccinini, M. Poli, C.

Sbarra,N. Semprini-Cesari, R. Spighi, M. Villa, A. Vitale, A. Zoccoli

La partecipazione del gruppo di Bologna (luminometro) alle attivita’ di ATLAS


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ContenutoLe attività del gruppo di Bologna in ATLAS:

Test delle schede di elettronica del LVL1 per le camere a MuoniLuminometro (LUCID): elettronica di lettura e di trigger + simulazioni

Presentazione del progettoL’elettronica di LUCID e stime (preliminari) dei costi

Altri interessi del gruppo:Partecipazione alla fisica & trigger di alto livello: fisica di alto Pt e diffrattiva Partecipazione al computing


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Attività sul LVL1 a Bologna

Il test delle schede di elettronica del LVL1 (prodotte da Roma1) per le camere a Muoni, verrà effettuato a Bologna.

Inizio: Settembre 2005.Test di: ~800 Pad-OR

~800 mother boardscon test JTAG e ELMBRate di test richiesto: 7 board/dayTempo previsto per il test del sistema: >6 mesi


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Attività sul LVL1 a Bologna - II

Prima riunione e trasporto del materiale il 7 Settembre. La scorsa settimana testate le prime 20 schede ORLe rimanenti schede OR (~800) in viaggio verso Bologna.Inizio lavoro sistematico sull’intero sistema (OR+mother) ad inizio Ottobre.

3 persone dedicate full-time al lavoro (2 su fondi universitari) + altre a rotazione.

Schedula dettagliata del test a Ottobre.


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ATLAS -LUMINOSITYImportance of Luminosity measurements: Cross sections for “Standard “ processes

t-tbar production W/Z production ……Theoretically known to better than 10% ……will improve in the future

New physics manifesting in deviation of x BR relative the Standard Model predictions

Important precision measurements Higgs production x BR tan measurement for MSSM Higgs ……


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Relative precision on the measurement of HBR for various channels, as function of mH, at Ldt = 300 fb–1. The dominant uncertainty is from Luminosity: 10% (open symbols), 5% (solid symbols).

(ATLAS-TDR-15, May 1999)

Higgs couplingtan measurement

Some examplesSome examples

Systematic error dominated by luminosity (ATLAS Physics TDR )

ATLAS –Luminosity (cont.)


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ATLAS Luminosity Measurement Program

• Relative luminosity a DEDICATED luminosity monitor is needed LUCIDLUCID will provide the luminosity per BX as well

• Absolute luminosity – Goal:

• measure L with ≲ 2-3% accuracy– How:

• LHC Machine parameters

• Use ZDC in heavy ion runs to understand machine parameters

• rates of well-calculable processes:e.g. QED, QCD

• optical theorem: forward elastic rate + total inelastic rate:

– needs ~full |η| coverage-ATLAS coverage limited

– Use tot measured by others (TOTEM)

– Combine machine luminosity with optical theorem

• luminosity from Coulomb Scattering Roman Pots

ATLAS pursuing all options

Roman Pots


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Motivations for LUCIDRequirements: A very radiation hard detector to be used as luminosity monitor Good time resolution to resolve individual beam crossings Insensitive to soft background particles Pointing capability A large dynamic range and no saturation at the highest luminosity A simple, robust and cheap construction

Solution:LUCID: LUminosity measurement using a Cherenkov Integrating

Detector

- The design is based on the Cherenkov Luminosity Counter (CLC) that is

operating successfully at CDF.- Gas filled tubes around the beampipe act as a Cherenkov detector anddetects particles from the I.P. that are above the Cherenkov threshold(2.7 GeV for pions and 9 MeV for electrons)


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Basics of the detector2 detectors x 200 Al tubes filled with C4F10 or Isobutane at atmospheric pressure

Winston cones at the end of the tubes focus the Cherenkov light onto quartz fibres

Beampipe


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The fibre read-out


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General Considerations-I

The purpose of this talk is to describe a possible baseline for the design of the ATLAS luminometer (LUCID) readout electronics and trigger scheme.

Our aim (since last June) is to achieve, as soon as possible, the following points:

• Define the general scheme of the electronics• Tune, by MC simulation and test beam, the final design

parameters• Provide a cost estimate per readout channel and

time schedule for the realization of the electronics• Start as soon as possible with the design in order to be

ready in 2007


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General Considerations-IIMain Goals of the LUCID electronics:

1. For each triggered event (ROD level): Number of tracks Tracks time of arrival

2. Monitor level Number of tracks per bunch Tracks time of arrival per bunch

3. Trigger Level Provide a fast trigger on “properly” filled bunch or on-

time events Provide a RAP-GAP vetoing for forward physics

Strategy: exploit available FED solutions where possible


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Signal from IP Background from sec. vtx

Background from particles crossing fibers

• High Occupancy ~30% (at max. luminosity)• Max. 3 tracks/tube (at max. luminosity)•The amount of information to be handled @L1 can be encoded in 18 bit

•MAPMT and FE are in a low level radiation area for electronics (5 Gray/year)

Known Facts

1) Amplitude meas. (2+1 bit @ L1) 2) Signal time-of-arrival measurement (1 bit @L1)

•Reject off - BX background sources (part of beam gas interactions, satellites BX, interactions originating off-IP)•Provide a detailed BX structure monitor•Guarantee the selection of events in time with the readout electronics of all the ATLAS detector IMPORTANT TOOL FOR THE WHOLE ATLAS DATA TAKING

3) Hit fibers pattern(7x2 bit @L1)


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System Architecture

FRONT END (FEPCB)

Similar to Roman Pot FE:OPERA/MAROC chip Input: MAPMTOutput: DIGITIZEDINFORMATION onLVDS Links (~0.5 Gb/s)

22x2

MAPMT

LVDS

LINKS

VME BUS: TTCvi, CTRL sign.,etc

ROS

ROD

ROD

ROD

ROD

TRIGG.

CARD

HV FE CONTROL

PC


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Photomultiplicator

Photons

Preamp.

BipolarFast Shaper

UnipolarFast Shaper

Trigger

Gain correction

4 discriminator thresholds

MUX_OUT1 Multiplexedcurrent output

(for channel monitor)

TRIG_OUT63 Trigger

outputsx

2 bit/output/BXon 9 LVDS TX6 Bits

(2n-4, n=0..5)

4 x 10 bits DACs

SUM_OUT9 Signal current

outputs(sum over 7 out)

THE OPERA/MAROC CHIPBLOCK FUNCTIONALITY DIAGRAM

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1

63

Modifications for Lucid in blue text


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OPERA/MAROC chip : LAYOUT– Technology: SiGe 0.35 m

– Submitted mid-June, expected mid September– Chip area : 12 mm2 (3.5mm *3.9mm)– 64 channels, 3.5V power supply

– Power consumption : 350 mW

– 228 pins–A lot of flexibility:

• Gain adjustment per channel (6 bits)• 4 thresholds • Multiplexed currentmeasurement

1 tube 7 readout channel1 mapmt 9 tubesOutput for LUCID:9 current (sum over 7 channels)1 current (multiplexed for channel control)63 x 2 bit (80 MHz clock, for trigger)


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Single Tube Readout Unit(7 channels)

15 nsint

10 nsreset

25 ns

time

time

LHC Clock

LHC Int. Time

ADC GATE

TDC START

to thetrigger

unit

FanOut

TDCWindow

ProgrammableComparator

GI+

ADC

Multiplicity per Tube

LUT

8

8

2

1

3

TUBE

LUT

(260 kB)

2

2

2

2

2

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#1

#7

LVDS

S/P

1/9 datafrom the MAROCCHIP

MAROC CHIPSUM_OUT

STRU

Discr. (Prog.

Thr+NR)

TDC START

STOP

ADC GATE

RAW DATA TO READOUT per STRU ~ 5-6 Bytes/BX

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18


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stru 1stru 2

stru 20

SUM_OUT 1_1

SUM_OUT 1_2

SUM_OUT 2_10

LVDS 1_1

LVDS 1_2

LVDS 2_9

LVDSS/P

LVDSS/P

3

3

3

LVDS 1_1 (to trig. unit)




stru 2

TTCRQ i.f.opt. lnkfrom TTCIX

VME P1VME I.F

DPRAMDPRAM

DPRAM

CTRLLOGIC

6 Bytes

6 Bytes

6 Bytes

EVENTBUFFER

s-LINKto ROS

from CTRL LOGICfrom CTRL LOGIC

160 MB/s

s-LINK Busy

LUCID ROD BOARD (22 units + spares) – VME 9U

Analog_In 1

Analog_In 2

Analog_In 20

LVDS_In 1

LVDS_In 2

LVDS_In 18

~200 Bytes/ev


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SignalBuffer

TTCRQ i.f.opt. lnkfrom TTCIX

VME P1VME I.F

CTRLLOGIC

s-LINKto ROS 160 MB/s

s-LINK Busy

LUCID TRIGGER BOARD (1 unit + spares) – VME 9U

Detector

1

Detector

2

LVDS 1_1

LVDS 1_2

LVDS 22_1

LVDS 22_2

1

2

43

44

LVDS 23_1

LVDS 23_2

LVDS 44_1

LVDS 44_2

1

2

43

44

SignalBuffer

FPGA basedTRIGGER

PROCESSINGUNIT

44 ser. Inp594 bit/BX

44 ser. Inp594 bit/BX

to the L0 trigger

~200 Bytes/ev

Algorithm:MC simulations are needed


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Description of the main building blocks of the readout electronics

OPERA MAROC CHIP • Adapted to LUCID needs from the RP design (ATLAS Orsay group)

Gated Integrator + ADC • 8 bit for the total sum

should be enough • Contacts have been taken with the LHCb preshower group (Clermont) for

adapting their GI+ADC solution

TDC• 25 ns full range; • 300 ps MAPMT resolution 7-8 bit• CERN HPTDC will be used (32 channel at 2MHz 2 channels at 32 MHz,

but still convenient)

LOGIC• Mainly Based on LUT (but still to be optimized)• IMPLEMENTED on FPGAs • Flexible and robust

ENGINEERING• Integration has to be studied but standard VME 9U will be probably

preferred


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First Costs Estimate

ITEM UNITS PROD MIN MAXFACTOR (EURO) (EURO)

MAPMT 50 80000 85000MAROC 50 10000 20000

FE 3 2 6360 6360ROD 25 2 165750 208250TB 2 2 7700 7700

VME+PC 1 40500 40500

TOTAL 310310 367810

COSTS SUMMARY

Q.ty Units MIN MAX MIN MAX

MAPMT 2 unit/ROD 1600 1700 3200 3400

MAROC 2 unit/ROD 200 400 400 800 a multiproject of 20 keuro (shared?) is assumed for 50 chip

FRONT END (FE)

coax cables (incl. connectors) 20 25m/ROD 20 20 400 400 suhner gx 02272 + SMB connectorsflat cables (incl.connectors) 1 25m/ROD 100 100 100 100 2x20 twisted pair cableLVDS TX 18 unit/ROD 20 20 360 360CTRL FPGA 1 unit/ROD 200 200 200 200TOTAL FRONT END (MATERIAL)/ROD 1060 1060

READ-OUT BOARD (ROD)

LHCb PS Gated Integrators 5 unit/ROD 100 150 500 750 purchased directly by LHCb outlet (2500 chip)8 bit ADC 40 MSPS 20 unit/ROD 5 10 100 200 investigate LHCb PS FE solutionTDC 10 unit/ROD 35 35 350 350 CERN HPTDCTTCRQ 1 unit/ROD 100 100 100 100S-LINK (incl. cable) 1 unit/ROD 200 200 200 200VME IF FPGA 1 unit/ROD 50 50 50 50CTRL LOGIC FPGA 1 unit/ROD 75 75 75 75STRU LUT,DPRAM,EVENT BUFF. FPGA 20 unit/ROD 75 100 1500 2000LVDS RX 18 unit/ROD 20 20 360 360LVDS TX 4 unit/ROD 20 20 80 80TOTAL ROD (MATERIAL) 3315 4165

TRIGGER BOARD (TB)

TTCRQ 1 unit/TB 100 100 100 100S-LINK (incl. cable) 1 unit/TB 200 200 200 200VME IF FPGA 1 unit/TB 50 50 50 50CTRL LOGIC FPGA 1 unit/TB 75 75 75 75TRIGGER PROCESSING UNIT FPGA 1 unit/TB 1500 1500 1500 1500TOTAL TB 1925 1925

VME+PC

VME 9U CRATES 3 unit 7500 7500 22500 22500 2+1 spareVME CPU 3 unit 4000 4000 12000 12000 2+1 sparePC 2 unit 3000 3000 6000 6000TOTAL SYSTEM 40500 40500

Item CommentsUNIT COST

(EURO)

TOTAL COST

(EURO)

TOTAL


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10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12

FE CARDS

Tests on the available version of the MAROC chipDesign (incl. mechanics) frozen Layout submitted (company will provide fully mounted prot+prod.)Prototype board receivedPrototypes testedElectronics readyElectronics installedInstallation testedElectronics commissioned

ROD CARDS

Design (incl. mechanics) frozen Layout submitted (company will provide fully mounted prot+prod.)Prototype board receivedPrototypes testedElectronics readyElectronics installedInstallation testedElectronics commissioned

TB (Trigger Board)

Design (incl. mechanics) frozen Layout submitted (company will provide fully mounted prot+prod.)Prototype board receivedPrototypes testedElectronics readyElectronics installedInstallation testedElectronics commissioned

2006 20072005

Tentative Time Schedule

(full production)

(full production)

(full production)

(3 units)

(25 units)

(2 units)


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Time Profile

ITEM % kEuro % kEuro

MAPMT 100 85.0 0 0.0MAROC 100 20.0 0 0.0

FE 100 6.4 0 0.0ROD 20 41.7 80 166.6TB 0 0.0 100 7.7

VME+PC 0 0.0 100 40.5

TOTAL 153.0 214.8

2006 2007

Goals of the project Detector ready beginning 2007 FED and ROD ready in 2007 in useful time before

the start of LHC operation Trigger Board before the end of 2007

Funding Profile according to these goals:


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Next Steps: System Optimization (Test Beam & MC)

1. Study the best solution for the tube readout (gas pressure, number and type of fibers per tube, MAPMT type) Test Beam at DESY October

Main goals of the Test beam (1/10-14/11): Photon generation, transfer and losses Generation, processing and transmission of electrical

signals Baseline Readout Device: MAPMT H 7546 (64 ch-UV glass

win.)

2. MC Study to refine design parameter (TDC & ADC resolution), occupancy (# of channels), trigger algorithm


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TEST BEAM: the MAPMT-FIBERS connection


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Richieste finanziarie 2006(variazioni rispetto ai moduli in colore violetto)

Richieste finanziarie 2006:M.I. : 21 k€ metabolismo M.E. : 142.5 k€ metabolismo + test beam + C&IConsumo: 21 k€ metabolismo (+5 k€ per l`attivita` sul LVL1)Inventario: 17.5 k€ farm di computing per analisi (Tier 3 like) in comune con il gruppo BO-RPC (responsabile per I 2 gruppi: F. Semeria)Costruzione apparati: 270k€ (<350k€ ) per elettronica LUCID

Comprendenti PM, Cavi, crates etc.Trasporti: 3 k€ (per l`attivita` sul LVL1)


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Conclusions

• The Bologna Group activities in ATLAS are started I many different areas.

• The group will test the LVL1 boards (~830 Pad-OR and mother boards) in Bologna. The setting-up is started. The systematic work will begin in October.

• The group is involved in the LUCID detector (lumi monitor). Main activities are concerning:– MC simulations– Electronic design


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BACKUP


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Conclusions - II

• We are developing, based on the present knowledge of the detector, a baseline design of the LUCID electronics

• We consider this baseline being in a quite advanced stage and capable to fulfill the detector requirements (more: with the TDC options LUCID become an IMPORTANT DETECTOR for the ATLAS DATA TAKING)

• Forthcoming test beam and MC simulation will be valuable inputs to improve (in case, simplifying) the design

• We have already solutions at hand for critical devices (front-end chip, G.I.,ADC, TDC) that make us confident for a start of data taking together with LHC


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More infos

- Groups involved in LUCID:University of Alberta, University & INFN Bologna, CERN, University of Lund, University of Montreal, Max Planck Institute, University of Manchester (?), SACLAY Italy would represent ~50% of the group

- Total cost of the project for INFN :~ 400 k€

Would represent ~50% of the total cost


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General Considerations-III• For the description of the readout electronics I will refer essentially to the

baseline of the detector described in the LOI

• Detector:formed by two parts each one consisting of 200 Cherenkov counters (tubes) 5 layers/section x 40 tubes/layer x 7 fibers/tube x 2 sections = 2800 fibers

• Signal:Prompt particles coming from the IP (primaries) will traverse the full length of the counter and generate a large amplitude signal in the photo-detector

• Background I: Particles originating from secondary interaction of prompt particles in the

detector material and beam-pipe (secondaries) are softer and will traverse the counters at larger angles (multiple reflections), with shorter path lengths

Background I significantly smaller than signal• Background II:

Particles crossing the readout fibers will produce light only on the crossed fibers

Background II will have different pattern of hit fibers wrt signal


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Signal amplitude measurement• CLC have the important feature to guarantee a

proportionality between the number of primary particles traversing a single tube and the resulting signal amplitude.

• These detectors response is not subjected to Landau fluctuations (present in scintillators) and the counter’s amplitude distribution will show distinct peaks for the different particle multiplicities hitting the counters.

LUCID, with an appropriate readout and trigger system can provide the Total Tracks multiplicity per BX


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Signal time-of-arrival measurement

A “precise” measurement of the arrival time of a track in the LUCID detector will help to:

• Reject off - BX background sources (part of beam gas interactions, satellites BX, interactions originating off-IP)

• Provide a detailed BX structure monitor• Guarantee the selection of events in time with the readout

electronics of all the ATLAS detector IMPORTANT TOOL FOR THE WHOLE ATLAS DATA TAKING

Hit fibers pattern

Important to reject Background (essentially of type II)


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Location of the detectorSituation when the forward shielding is removed:


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Documents

M. Bruschi-CSN1 Napoli 21 Settembre 2005 1 A. Bertin, M. Bruschi, S. De Castro, L. Fabbri, P. Faccioli, B. Giacobbe, F. Grimaldi, I. Massa, M. Piccinini,