Max 9247

8/10/2019 Max 9247

1/17

General Description

The MAX9247 digital video parallel-to-serial converterserializes 27 bits of parallel data into a serial-data stream.Eighteen bits of video data and 9 bits of control data areencoded and multiplexed onto the serial interface, reduc-ing the serial-data rate. The data-enable input determineswhen the video or control data is serialized.

The MAX9247 pairs with the MAX9248/MAX9250 dese-rializers to form a complete digital video serial link.Interconnect can be controlled-impedance PCB traces ortwisted-pair cable. Proprietary data encoding reducesEMI and provides DC balance. DC balance allows AC-coupling, providing isolation between the transmittingand receiving ends of the interface. The LVDS output isinternally terminated with 100. For operating frequen-

cies less than 35MHz, the MAX9247 can also pair withthe MAX9218 deserializer.

ESD tolerance is specified for ISO 10605 with 10kVContact Discharge and 30kV Air-Gap Discharge.

The MAX9247 operates from a +3.3V core supply andfeatures a separate input supply for interfacing to 1.8Vto 3.3V logic levels. This device is available in a 48-leadLQFP package and is specified from -40C to +85C or-40C to +105C.

ApplicationsNavigation System Displays

In-Vehicle Entertainment Systems

Video Cameras

LCDs

Features

Preemphasis Improves Eye Diagram and SignalIntegrity at the Output

Proprietary Data Encoding for DC Balance andReduced EMI

Control Data Sent During Video Blanking

Five Control Data Inputs are Single-Bit-ErrorTolerant

Programmable Phase-Shifted LVDS SignalingReduces EMI

Output Common-Mode Filter Reduces EMI

Greater Than 10m STP Cable Drive

Wide 2% Reference Clock Tolerance

ISO 10605 and IEC 61000-4-2 Level 4ESD Protection

Separate Input Supply Allows Interface to 1.8Vto 3.3V Logic

+3.3V Core Supply

Space-Saving LQFP Package

-40C to +85C and -40C to +105C OperatingTemperature Ranges

________________________________________________________________ Maxim Integrated Products 1

RNG0

RNG1

VCCLVDS

OUT+

OUT-

LVDSGND

LVDSGNDCMF

PWRDWN

VCCPLL

PLLGND

PRE

GND

VCCIN

RGB_IN10

RGB_IN11

RGB_IN12

RGB_IN13

RGB_IN14RGB_IN15

RGB_IN16

RGB_IN17

CNTL_IN0

CNTL_IN1

1

2

3

4

5

6

78

9

10

11

12

36

35

34

33

32

31

3029

28

27

26

25

GND

VCC

CNTL_

IN2

CNTL_

IN3

CNTL_

IN4

CNTL_

IN5

CNTL_

IN6

CNTL_

IN7

CNTL_

IN8

DE_

IN

PCLK_

INI.C.

LQFP

+

MAX9247

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

RGB_

IN9

RGB_

IN8

RGB_

IN7

RGB_

IN6

RGB_

IN5

RGB_

IN4

RGB_

IN3

RGB_

IN2

RGB_

IN1

RGB_

IN0

VCC

GNDTOP VIEW

PART TEMP RANGE PIN-PACKAGE

MAX9247ECM+ -40C to +85C 48 LQFP

MAX9247ECM/V+ -40C to +85C 48 LQFP

MAX9247GCM+ -40C to +105C 48 LQFP

MAX9247GCM/V+ -40C to +105C 48 LQFP

Pin Configuration

Ordering Information

19-3955; Rev 4; 4/12

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,or visit Maxims website at www.maxim-ic.com.

EVALUATIO

NKIT

AVAILABLE

+Denotes a lead(Pb)-free/RoHS-compliant package./V denotes an automotive qualified part.

27-Bit, 2.5MHz-to-42MHzDC-Balanced LVDS Serializer

8/10/2019 Max 9247

2/17

8/10/2019 Max 9247

3/17


_______________________________________________________________________________________ 3

AC ELECTRICAL CHARACTERISTICS(VCC_ = +3.0V to +3.6V, RL = 100 1%, CL = 5pF, PWRDWN= high, PRE = low, TA = -40C to +105C, unless otherwise noted.Typical values are at VCC_ = +3.3V, TA = +25C.) (Note 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

PCLK_IN TIMING REQUIREMENTS

MAX9247ECM 23.8 400.0Clock Period tT Figure 2

MAX9247GCM 28.6 400.0ns

MAX9247ECM 2.5 42.0Clock Frequency fCLK

MAX9247GCM 2.5 35.0MHz

Clock Frequency Difference from

Deserializer Reference Clock fCLK -2 +2 %

Clock Duty Cycle DC tHIGH/tTor tLOW/tT,Figure 2 35 50 65 %

Clock Transition Time tR, tF Figure 2 2.5 ns

SWITCHING CHARACTERISTICS

PRE = low 280 370Output Rise Time tRISE

20% to 80%,

VOD250mV, Figure 3 PRE = high 240 320ps

PRE = low 280 370Output Fall Time tFALL

80% to 20%,

VOD250mV, Figure 3 PRE = high 240 320ps

Input Setup Time tSET Figure 4 3 ns

Input Hold Time tHOLD Figure 4 3 ns

DC ELECTRICAL CHARACTERISTICS (continued)

(VCC_ = +3.0V to +3.6V, RL = 100 1%, PWRDWN = high, PRE = low, TA = -40C to +105C, unless otherwise noted. Typicalvalues are at VCC_ = +3.3V, TA = +25C.) (Notes 1, 2)


Differential Output Resistance RO 78 110 147

PRE = 0 15 252.5MHz

PRE = 1 27

PRE = 0 18 255MHz

PRE = 1 27

PRE = 0 23 2810MHz

PRE = 1 30

PRE = 0 33 3920MHz

PRE = 1 42

PRE = 0 50 6535MHz

PRE = 1 69

PRE = 0 60 70

Worst-Case Supply CurrentICCW

RL= 1001%,

CL= 5pF,

continuous 10

transition words

42MHzPRE = 1 75

mA

Power-Down Supply Current ICCZ (Note 4) 50 A

8/10/2019 Max 9247

4/17

MAX924

7


4 _______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS (continued)

(VCC_ = +3.0V to +3.6V, RL = 100

1%, CL = 5pF,PWRDWN

= high, PRE = low, TA = -40C to +105C, unless otherwise noted.Typical values are at VCC_ = +3.3V, TA = +25C.) (Note 3)


Serializer Delay tSD Figure 53.10 x

tT+ 2.0

3.10 x

tT+ 8.0ns

PLL Lock Time tLOCK Figure 617,100 x

tTns

Power-Down Delay tPD Figure 7 1 s

Peak-to-Peak Output Jitter tJITTMeasured with PRBS input pattern at

840Mbps data rate150 ps

840Mbps data rate,

CMF open, Figure 822 70

Peak-to-Peak Output Offset

VoltageV

OS(P-P) 840Mbps data rate,

CMF 0.1F to ground, Figure 812 50

mV

Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground,

except VOD, VOD, and VOS.

Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production

tested at TA = +25C.

Note 3: Parameters are guaranteed by design and characterization and are not production tested. Limits are set at 6 sigma.

Note 4: All LVTTL/LVCMOS inputs, except PWRDWNat 0.3V or VCCIN - 0.3V. PWRDWN is 0.3V.

8/10/2019 Max 9247

5/17


_______________________________________________________________________________________ 5

WORST-CASE PATTERN

SUPPLY CURRENT vs. FREQUENCY

MAX9247toc01

FREQUENCY (MHz)

SUPPLYCURRENT(mA)

40302010

10

20

30

40

50

60

70

00

WITH PREEMPHASIS

WITHOUT PREEMPHASIS

EYE DIAGRAM WITH PREEMPHASIS

MAX9247toc03

100mV/div

200ps/div

fREFCLK= 42MHz

2 METER CAT5 CABLE

GND

100TERMINATION

PRE = HIGH

EYE DIAGRAM WITHOUT PREEMPHASIS

MAX9247toc02

100mV/div

200ps/div

fREFCLK= 42MHz

2 METER CAT5 CABLE

GND

100TERMINATION

PRE = LOW

BIT-ERROR RATE vs. CABLE LENGTH

MAX9247toc04

CAT5 CABLE LENGTH (m)

BIT-ERRORRATE

8 10 12642

1.00E-11

1.00E-12

1.00E-13

1.00E-14

1.00E-100

CAT5 CABLE

fREFCLK= 42MHz840Mbps DATA RATEFOR CABLE LENGTH < 10mBER < 10-12

CABLE LENGTH

vs. FREQUENCY BIT-ERROR RATE < 10-9

MAX9247toc05

CABLE LENGTH (m)

FRE

QUENCY(MHz)

15

25

35

45

5

20

30

40

10

181614121086420 20

Typical Operating Characteristics

(VCC_ = +3.3V, RL = 100, TA = +25C, unless otherwise noted.)

8/10/2019 Max 9247

6/17

MAX924

7


6 _______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

1, 13, 37 GND Input Buffer Supply and Digital Supply Ground

2 VCCINInput Buffer Supply Voltage. Bypass to GND with 0.1F and 0.001F capacitors in parallel as

close to the device as possible, with the smallest value capacitor closest to the supply pin.

310,

3948

RGB_IN10

RGB_IN17,

RGB_IN0

RGB_IN9

LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Inputs. Eighteen data bits are loaded

into the input latch on the rising edge of PCLK_IN when DE_IN is high. Internally pulled down to

GND.

11, 12, 1521

CNTL_IN0,

CNTL_IN1,

CNTL_IN2

CNTL_IN8

LVTTL/LVCMOS Control Data Inputs. Control data are latched on the rising edge of PCLK_IN

when DE_IN is low. Internally pulled down to GND.

14, 38 VCC Digital Supply Voltage. Bypass to GND with 0.1F and 0.001F capacitors in parallel as close tothe device as possible, with the smallest value capacitor closest to the supply pin.

22 DE_IN

LVTTL/LVCMOS Data-Enable Input. Logic-high selects RGB_IN[17:0] to be latched. Logic-low

selects CNTL_IN[8:0] to be latched. DE_IN must be switching for proper operation. Internally

pulled down to GND.

23 PCLK_INLVTTL/LVCMOS Parallel Clock Input. Latches data and control inputs and provides the PLL

reference clock. Internally pulled down to GND.

24 I.C. Internally Connected. Leave unconnected for normal operation.

25 PRE Preemphasis Enable Input. Drive PRE high to enable preemphasis.

26 PLLGND PLL Supply Ground

27 VCCPLLPLL Supply Voltage. Bypass to PLLGND with 0.1F and 0.001F capacitors in parallel as close to

the device as possible, with the smallest value capacitor closest to the supply pin.

28 PWRDWN LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.

29 CMFCommon-Mode Filter. Optionally connect a capacitor between CMF and LVDSGND to filter

common-mode switching noise.

30, 31 LVDSGND LVDS Supply Ground

32 OUT- Inverting LVDS Serial-Data Output

33 OUT+ Noninverting LVDS Serial-Data Output

34 VCCLVDSLVDS Supply Voltage. Bypass to LVDSGND with 0.1F and 0.001F capacitors in parallel as

close to the device as possible, with the smallest value capacitor closest to the supply pin.

35 RNG1LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the

PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.

36 RNG0LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the

PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.

8/10/2019 Max 9247

7/17


_______________________________________________________________________________________ 7

Functional Diagram

MAX9247

TIMING AND CONTROL

DC BALANCE/ENCODE

INPUT LATCH

RGB_IN

CNTL_IN

DE_IN

PCLK_IN

RNG0

RNG1

PWRDWN

1

0

OUT+

OUT-

PLL

PAR-TO-SER

CMF

PRE

OUT-

VOD

VOS

GND

RL/2

RL/2

OUT+

OUT-

OUT+

(OUT+) - (OUT-)

VOS(-) VOS(+)

((OUT+) + (OUT-))/2

VOS(-)

VOD(-)VOD(-)

VOD = 0V

VOS= |VOS(+) - VOS(-)|

VOD= |VOD(+) - VOD(-)|

VOD(+)

Figure 1. LVDS DC Output Load and Parameters

8/10/2019 Max 9247

8/17

MAX924

7


8 _______________________________________________________________________________________

VILmax

tHIGH

tLOW

tT

tRtF

VIHmin

PCLK_IN

Figure 2. Parallel Clock Requirements

OUT-

CL CL

RL

OUT+

tFALL

20%20%

(OUT+) - (OUT-)

80%80%

tRISE

Figure 3. Output Rise and Fall Times

VIHmin

VIHminVIHmin

VILmax VILmax

VILmax

PCLK_IN

RGB_IN[17:0]

CNTL_IN[8:0]

DE_IN

tHOLDtSET

Figure 4. Synchronous Input Timing

8/10/2019 Max 9247

9/17


_______________________________________________________________________________________ 9

tSD BIT 0 BIT 19

N

N + 3

EXPANDED TIME SCALE

N + 4N N + 1 N + 2

N - 1

RGB_INCNTL_IN

PCLK_IN

OUT_

Figure 5. Serializer Delay

VOD = 0VHIGH IMPEDANCE

VILmax

tLOCKPWRDWN

(OUT+) - (OUT-)

PCLK_IN

Figure 6. PLL Lock Time

HIGH IMPEDANCE

VILmax

tPD

PWRDWN

(OUT+) - (OUT-)

PCLK_IN

Figure 7. Power-Down Delay

8/10/2019 Max 9247

10/17

MAX924

7


10 ______________________________________________________________________________________

Detailed DescriptionThe MAX9247 DC-balanced serializer operates at a2.5MHz-to-42MHz parallel clock frequency, serializing18 bits of parallel video data RGB_IN[17:0] when thedata-enable input DE_IN is high, or 9 bits of parallelcontrol data CNTL_IN[8:0] when DE_IN is low. TheRGB video input data are encoded using 2 overheadbits, EN0 and EN1, resulting in a serial word length of20 bits (see Table 1). Control inputs are mapped to 19bits and encoded with 1 overhead bit, EN0, also result-ing in a 20-bit serial word. Encoding reduces EMI and

maintains DC balance across the serial cable. Twotransition words, which contain a unique bit sequence,are inserted at the transition boundaries of video-to-control and control-to-video phases.

Control data inputs C0 to C4 are mapped to 3 bits eachin the serial control word (see Table 2). At the deserial-izer, 2 or 3 bits at the same state determine the state ofthe recovered bit, providing single-bit-error tolerancefor C0 to C4. Control data that may be visible if an erroroccurs, such as VSYNC and HSYNC, can be connect-ed to these inputs. Control data inputs C5 to C8 aremapped to 1 bit each.

OUT-

OUT+

((OUT+) + (OUT-))/2VOS(P-P)VOS(P-P)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

EN0 EN1 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17

Figure 8. Peak-to-Peak Output Offset Voltage

Bit 0 is the LSB and is serialized first. EN[1:0] are encoding bits. S[17:0] are encoded symbols.

Table 1. Serial Video Phase Word Format

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

EN0 C0 C0 C0 C1 C1 C1 C2 C2 C2 C3 C3 C3 C4 C4 C4 C5 C6 C7 C8

Bit 0 is the LSB and is serialized first. C[8:0] are the control inputs.

Table 2. Serial Control Phase Word Format

8/10/2019 Max 9247

11/17


______________________________________________________________________________________ 11

Transition TimingThe transition words require interconnect bandwidthand displace control data. Therefore, control data is notsampled (see Figure 9):

Two clock cycles before DE_IN goes high

During the video phase

Two clock cycles after DE_IN goes low

The last sampled control data are latched at the deserial-izer control data outputs during the transition and videophases. Video data are latched at the deserializer RGBdata outputs during the transition and control phases.

Applications Information

AC-Coupling BenefitsAC-coupling increases the common-mode voltage tothe voltage rating of the capacitor. Two capacitors are

sufficient for isolation, but four capacitorstwo at theserializer output and two at the deserializer inputpro-vide protection if either end of the cable is shorted to ahigh voltage. AC-coupling blocks low-frequencyground shifts and common-mode noise. The MAX9247serializer can also be DC-coupled to the MAX9248/MAX9250 deserializers.

Figures 10 and 12 show an AC-coupled serializer anddeserializer with two capacitors per link. Figures 11 and

13 show the AC-coupled serializer and deserializer withfour capacitors per link.

Selection of AC-Coupling Capacitors

See Figure 14 for calculating the capacitor values forAC-coupling depending on the parallel clock frequen-cy. The plot shows capacitor values for two- and four-capacitor-per-link systems. For applications using lessthan 18MHz clock frequency, use 0.1F capacitors.

Frequency-Range Setting RNG[1:0]The RNG[1:0] inputs select the operating frequencyrange of the MAX9247 serializer. An external clock with-in this range is required for operation. Table 3 showsthe selectable frequency ranges and correspondingdata rates for the MAX9247.

RNG1 RNG0PARALLEL

CLOCK (MHz)

SERIAL-DATA RATE

(Mbps)

0 0 2.5 to 5 50 to 100

0 1 5 to10 100 to 200

1 0 10 to 20 200 to 400

1 1 20 to 42 400 to 840

Table 3. Parallel Clock Frequency Range

Select

Figure 9. Transition Timing

PCLK_IN

CNTL_IN

DE_IN

RGB_IN

= NOT SAMPLED BY PCLK_IN

CONTROL

PHASE

CONTROL

PHASE

TRANSITION

PHASE

TRANSITION

PHASEVIDEO PHASE

8/10/2019 Max 9247

12/17

MAX924

7


12 ______________________________________________________________________________________

MAX9247

PAR-TO-SER

TIMING ANDCONTROL

DCB

ALANCE/

ENCODE

INPUT

LATCH

RGB_IN

CNTL_IN

DE_IN

PCLK_IN

RNG0

RNG1

PWRDWN

1

0

130

VCC

130

INOUT

82 82CMF

PRE

RNG1

RNG0

MAX9250

SER-TO-PAR

TIMING ANDCONTROL

PLL

DCB

ALANCE/

DECODE 1

0

OUTEN

RGB_OUT

LOCK

PWRDWN

REF_IN

PCLK_OUT

DE_OUT

CNTL_OUT

R/F

CERAMIC RF SURFACE-MOUNT CAPACITOR 100DIFFERENTIAL STP CABLE

PLL

*

*

*CAPACITORS CAN BE AT EITHER END.

Figure 10. AC-Coupled MAX9247 Serializer and MAX9250 Deserializer with Two Capacitors per Link

MAX9247

PAR-TO-SER

TIMING ANDCONTROL

DCB

ALANCE/

ENCODE

INPUT

LATCH

RGB_IN

CNTL_IN

DE_IN

PCLK_IN

RNG0

RNG1

PWRDWN

1

0

130

VCC

130

INOUT

82 82

RNG1

RNG0

MAX9250

SER-TO-PAR

TIMING ANDCONTROL

PLL

DCB

ALANCE/

DECODE 1

0

OUTENRGB_OUT

LOCK

PWRDWN

REF_IN

PCLK_OUT

DE_OUT

CNTL_OUT


PLL

CMF

PRE R/F

Figure 11. AC-Coupled MAX9247 Serializer and MAX9250 Deserializer with Four Capacitors per Link

8/10/2019 Max 9247

13/17


______________________________________________________________________________________ 13

MAX9247

PAR-TO-SER

TIMING ANDCONTROL

DCB

ALANCE/

ENCODE

INPUT

LATCH

RGB_IN

CNTL_IN

DE_IN

PCLK_IN

RNG0

RNG1

PWRDWN

1

0

130

VCC

130

IN+

IN-OUT

82 82CMF

PRE

REFCLK

MAX9248

SER-TO-PAR

TIMING ANDCONTROL

PLL

DCB

ALANCE/

DECODE 1

0

RGB_OUT

LOCK

PWRDWN

SS

PCLK_OUT

DE_OUT

CNTL_OUT


PLL

*

*

*CAPACITORS CAN BE AT EITHER END.

SSPLL

FIFO

RNG[0:1]

R/F

Figure 12. AC-Coupled MAX9247 Serializer and MAX9248 Deserializer with Two Capacitors per Link

MAX9247

PAR-TO-SER

TIMING ANDCONTROL

DCB

ALANCE/

ENCODE

INPUT

LATC

H

RGB_IN

CNTL_IN

DE_IN

PCLK_IN

RNG0

RNG1

PWRDWN

1

0

130

VCC

130

IN+

IN-OUT

82 82CMF

PRE

REFCLK

MAX9248

SER-TO-PAR

TIMING ANDCONTROL

PLL

DCB

ALANC

E/

DECODE 1

0

RGB_OUT

LOCK

PWRDWN

SS

PCLK_OUT

DE_OUT

CNTL_OUT


PLL SSPLL

FIFO

RNG[0:1]

R/F

Figure 13. AC-Coupled MAX9247 Serializer and MAX9248 Deserializer with Four Capacitors per Link

8/10/2019 Max 9247

14/17

MAX924

7


14 ______________________________________________________________________________________

TerminationThe MAX9247 has an integrated 100 output-termina-tion resistor. This resistor damps reflections frominduced noise and mismatches between the transmis-sion line impedance and termination resistors at thedeserializer input. With PWRDWN= low or with the sup-ply off, the output termination is switched out and theLVDS output is high impedance.

Common-Mode FilterThe integrated 100 output termination is made up oftwo 50 resistors in series. The junction of the resistorsis connected to the CMF pin for connecting an optionalcommon-mode filter capacitor. Connect the filtercapacitor to ground close to the MAX9247 as shown inFigure 15. The capacitor shunts common-mode switch-ing current to ground to reduce EMI.

LVDS Output Preemphasis (PRE)The MAX9247 features a preemphasis mode where extracurrent is added to the output and causes the ampli-tude to increase by 40% to 50% at the transition point.Preemphasis helps to get a faster transition, better eyediagram, and improve signal integrity. See the TypicalOperating Characteristics. The additional current isturned on for a short time (360ps, typ) during data transi-tion, and then turned off. Enable preemphasis by drivingPRE high.

Power-Down and Power-Off

Driving PWRDWN low stops the PLL, switches out theintegrated 100 output termination, and puts the outputin high impedance to ground and differential. WithPWRD-WN 0.3V and all LVTTL/LVCMOS inputs 0.3V or

VCCIN - 0.3V, supply current is reduced to 50A or less.Driving PWRDWNhigh starts PLL lock to PCLK_IN andswitches in the 100 output termination resistor. TheLVDS output is not driven until the PLL locks. The LVDSoutput is high impedance to ground and 100 differen-tial. The 100 integrated termination pulls OUT+ andOUT- together while the PLL is locking so that VOD = 0V.

If VCC = 0, the output resistor is switched out and the LVDSoutputs are high impedance to ground and differential.

PLL Lock Time

The PLL lock time is set by an internal counter. The locktime is 17,100 PCLK_IN cycles. Power and clock shouldbe stable to meet the lock-time specification.

Input Buffer Supply

The single-ended inputs (RGB_IN[17:0], CNTL_IN[8:0],DE_IN, RNG0, RNG1, PRE, PCLK_IN, and PWRDWN)are powered from VCCIN. VCCIN can be connected to a1.71V to 3.6V supply, allowing logic inputs with a nomi-nal swing of VCCIN. If no power is applied to VCCINwhen power is applied to VCC, the inputs are disabledand PWRDWN is internally driven low, putting thedevice in the power-down state.

Power-Supply Sequencing of MAX9247and MAX9248/MAX9250 Video Link

The MAX9247 and MAX9248/MAX9250 video link canbe powered up in several ways. The best approach isto keep both MAX9247 and MAX9248 powered downwhile supplies are ramping up and PCLK_IN of theMAX9247 and REFCLK of the MAX9248/MAX9250 arestabilizing. After all of the power supplies of theMAX9247 and MAX9248/MAX9250 are stable, includingPCLK_IN and REFCLK, do the following:

1) Power up the MAX9247 first

AC-COUPLING CAPACITOR VALUE

vs. PARALLEL CLOCK FREQUENCY

PARALLEL CLOCK FREQUENCY (MHz)

CAPACITORV

ALUE

(nF)

21 24 27 33 36 3930

120

80

60

40

20

100

140

018 42

FOUR CAPACITORS PER LINK

TWO CAPACITORS PER LINK

Figure 14. AC-Coupling Capacitor Values vs. Clock Frequencyof 18MHz to 42MHz

OUT+

RO/2

RO/2

CMF

OUT-

CCMF

Figure 15. Common-Mode Filter Capacitor Connection

8/10/2019 Max 9247

15/17


______________________________________________________________________________________ 15

2) Wait for at least tLOCK of MAX9247 (or 17100 x tT)to get activity on the link

3) Power up the MAX9248

Power-Supply Circuits and BypassingThe MAX9247 has isolated on-chip power domains. Thedigital core supply (VCC) and single-ended input supply(VCCIN) are isolated but have a common ground (GND).The PLL has separate power and ground (VCCPLL andPLLGND) and the LVDS input also has separate powerand ground (VCCLVDS and LVDSGND). The grounds areisolated by diode connections. Bypass each VCC, VCCIN,VCCPLL, and VCCLVDS pin with high-frequency, surface-mount ceramic 0.1F and 0.001F capacitors in parallelas close to the device as possible, with the smallest valuecapacitor closest to the supply pin.

LVDS OutputThe LVDS output is a current source. The voltage swingis proportional to the termination resistance. The outputis rated for a differential load of 100 1%.

Cables and ConnectorsInterconnect for LVDS typically has a differential imped-ance of 100. Use cables and connectors that havematched differential impedance to minimize impedancediscontinuities.

Twisted-pair and shielded twisted-pair cables offersuperior signal quality compared to ribbon cable andtend to generate less EMI due to magnetic field cancel-ing effects. Balanced cables pick up noise as commonmode, which is rejected by the LVDS receiver.

Board LayoutSeparate the LVTTL/LVCMOS inputs and LVDS outputto prevent crosstalk. A four-layer PCB with separate lay-ers for power, ground, and signals is recommended.

ESD ProtectionThe MAX9247 ESD tolerance is rated for IEC 61000-4-2, Human Body Model, Machine Model, and ISO 10605standards. IEC 61000-4-2 and ISO 10605 specify ESDtolerance for electronic systems. The IEC 61000-4-2discharge components are CS = 150pF and RD =330 (Figure 16). For IEC 61000-4-2, the LVDS outputsare rated for 8kV Contact Discharge and 15kV Air-Gap Discharge. The Human Body Model dischargecomponents are CS = 100pF and RD = 1.5k (Figure17). For the Human Body Model, all pins are rated for3kV Contact Discharge. The ISO 10605 dischargecomponents are CS = 330pF and RD = 2k (Figure18). For ISO 10605, the LVDS outputs are rated for10kV contact and 30kV air discharge. The MachineModel discharge components are CS = 200pF andRD = 0 (Figure 19).

CS150pF

STORAGECAPACITOR

HIGH-VOLTAGE

DCSOURCE

DEVICEUNDERTEST

CHARGE-CURRENT-LIMIT RESISTOR

DISCHARGERESISTANCE

RD

330

Figure 16. IEC 61000-4-2 Contact Discharge ESD Test Circuit

STORAGECAPACITOR

HIGH-VOLTAGE

DCSOURCE

DEVICEUNDERTEST


DISCHARGERESISTANCE

1MRD

1.5k

CS100pF

Figure 17. Human Body ESD Test Circuit

STORAGECAPACITOR

HIGH-VOLTAGE

DCSOURCE

DEVICEUNDERTEST


DISCHARGERESISTANCE

RD2k

CS330pF

Figure 18. ISO 10605 Contact Discharge ESD Test Circuit

STORAGECAPACITOR

HIGH-VOLTAGE

DCSOURCE

DEVICEUNDERTEST


DISCHARGERESISTANCE

RD0

CS200pF

Figure 19. Machine Model ESD Test Circuit

8/10/2019 Max 9247

16/17

MAX924

7


16 ______________________________________________________________________________________

Chip Information

PROCESS: CMOS

Package Information

For the latest package outline information and land patterns(footprints), go towww.maxim-ic.com/packages. Note that a

+, #, or - in the package code indicates RoHS status only.

Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of RoHS status.

PACKAGETYPE

PACKAGECODE

OUTLINE NO. LAND

PATTERN NO.

48 LQFP C48+5 21-0054 90-0093
http://www.maxim-ic.com/packageshttp://www.maxim-ic.com/packageshttp://pdfserv.maxim-ic.com/package_dwgs/21-0054.PDFhttp://pdfserv.maxim-ic.com/land_patterns/90-0093.PDFhttp://pdfserv.maxim-ic.com/land_patterns/90-0093.PDFhttp://pdfserv.maxim-ic.com/package_dwgs/21-0054.PDFhttp://www.maxim-ic.com/packages

8/10/2019 Max 9247

17/17


Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in

the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

17 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

Revision History

REVISION

NUMBER

REVISION

DATE DESCRIPTION

PAGES

CHANGED

2 5/08Corrected LQFP package, added +105C part, changed temperature limits

for +105C rated part, and added Machine Model ESD text and diagram16, 1519

3 4/09Added /V parts in the Ordering Informationtable and added new Power-

Supply Sequencing of MAX9247 and MAX9248/MAX9250 Video Linksection1, 14

4 4/12 Corrected errors in Absolute Maximum Ratingsand Pin Description sections 2, 6

Documents

Max 9247