Micron SDRAM Datasheet

8/13/2019 Micron SDRAM Datasheet

1/72

Products and specificat ions discussed h erein are subject to chang e by Micron w ithout not ice.

64Mb: x4, x8, x16 SDRAMFeatures

PDF: 09005a e f80725c0b /So urce: 09005a ef806fc13c Micron Technolog y, Inc., reserves t he rig ht to cha ng e pro duct s o r specif ica t ions w ithout no t ice.

64MSDRAM_1.fm - Rev. N 12/08 EN 1 2000 Micron Technolo gy, Inc. All right s reserved.

Synchronous DRAMMT48LC16M4A2 4 Meg x 4 x 4 banksMT48LC8M8A2 2 Meg x 8 x 4 banksMT48LC4M16A2 1 Meg x 16 x 4 banksFor th e lat est da ta sheet, refe r to Microns Web site: w w w.micron.com/sdram

Features PC100- and PC133-compliant Fully synchronous; all signals registered on positive

edge of system clock Internal pipelined operation; column address can be

changed every clock cycle Internal banks for hiding row access/precharge Programmable burst lengths: 1, 2, 4, 8, or full page Auto precharge, includes concurrent auto precharge

and auto refresh modes Self refresh modes: standard and low power

(not available on AT devices) Refresh 64ms, 4,096-cycle refresh (15.6s/row)

(commercial, industrial) 16ms, 4,096-cycle refresh (3.9s/row)

(automotive) LVTTL-compatible inputs and outputs Single +3.3V 0.3V power supply

Tab le 1: Address Tab le16 Meg x 4 8 Meg x 8 4 Meg x 16

Configuration 4 Meg x 4 x

4 banks

2 Meg x 8 x

4 banks

1 Meg x 16 x

4 banks

Refresh count 4K 4K 4K

Row

addressing

4K (A0A11) 4K (A0A11) 4K (A0A11)

Bank

addressing

4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)

Column

addressing

1K (A0A9) 512 (A0A8) 256 (A0A7)

Notes: 1. Refer to Micron technical note: TN-48-05.

2. Off-center parting line.

3. Contact Micron for product availability.

Part Number Example:MT48LC8M8A2TG-75:G

Options Marking Configurations 16 Meg x 4 (4 Meg x 4 x 4 banks) 8 Meg x 8 (2 Meg x 8 x 4 banks) 4 Meg x 16 (1 Meg x 16 x 4 banks)

16M48M8

4M16 Write recovery (tWR)

tWR = 2 CLK1 A2

Plastic package OCPL

2

54-pin TSOP II (400 mil) 54-pin TSOP II (400 mil) Pb-free,

RoHS-compliant 54-ball VFBGA 8mm x 8mm (x16 only) 54-ball VFBGA 8mm x 8mm, Pb-free,

RoHS-compliant (x16 only)

TGP

F4B43

Timing (cycle time) 7.5ns @ CL = 3 (PC133) 7.5ns @ CL = 2 (PC133) 6ns @ CL = 3 (x16 only)

-75-7E-6

Self refresh Standard

Low power

None

L Operating temperature range Commercial (0C to +70C) Industrial (40C to +85C) Automotive (40C to +105C)

NoneIT

AT3

Design revision :G
http://download.micron.com/pdf/technotes/ZT05.pdfhttp://-/?-http://-/?-http://-/?-http://-/?-http://-/?-http://download.micron.com/pdf/technotes/ZT05.pdf


2/72



64Mb: x4, x8, x16 SDRAMGeneral Description

Not es: 1. FBGA Device Decode r: ht tp://w w w.micron.com/support/FBGA/FBGA.asp

Gene ral DescriptionThe Micron64Mb SDRAM is a high-speed CMOS, dynamic random-access memory

containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with asynchronous interface (all signals are registered on the positive edge of the clock signal,CLK). Each of the x4s 16,777,216-bit banks is organized as 4,096 rows by 1,024 columnsby 4 bits. Each of the x8s 16,777,216-bit banks is organized as 4,096 rows by 512 columnsby 8 bits. Each of the x16s 16,777,216-bit banks is organized as 4,096 rows by 256columns by 16 bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selectedlocation and continue for a programmed number of locations in a programmedsequence. Accesses begin with the registration of an ACTIVE command, which is thenfollowed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 selectthe bank; A0A11 select the row). The address bits registered coincident with the READor WRITE command are used to select the starting column location for the burst access.

The SDRAM provides for programmable read or write burst lengths of 1, 2, 4, or 8 loca-tions, or the full page, with a burst terminate option. An auto precharge function may beenabled to provide a self-timed row precharge that is initiated at the end of the burstsequence.

The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-tion. This architecture is compatible with the 2nrule of prefetch architectures, but it alsoallows the column address to be changed on every clock cycle to achieve a high-speed,

Table 2: Key Timing Param ete rsCL = CAS (READ) lat en cy

Speed Grade Clock Frequency

Access Tim e

Setup Time Hold TimeCL = 2 CL = 3-6 166 MHz 5.5ns 1.5ns 1ns

-7E 143 MHz 5.4ns 1.5ns 0.8ns

-75 133 MHz 5.4ns 1.5ns 0.8ns

-7E 133 MHz 5.4ns 1.5ns 0.8ns

-75 100 MHz 6ns 1.5ns 0.8ns

Tab le 3: 64Mb SDRAM Part Numb ers

Part Numbers Architecture Package

MT48LC16M4A2TG 16 Meg x 4 54-pin TSOP II

MT48LC16M4A2P 16 Meg x 4 54-pin TSOP II

MT48LC8M8A2TG 8 Meg x 8 54-pin TSOP IIMT48LC8M8A2P 8 Meg x 8 54-pin TSOP II

MT48LC4M16A2TG 4 Meg x 16 54-pin TSOP II

MT48LC4M16A2P 4 Meg x 16 54-pin TSOP II

MT48LC4M16A2B41 4 Meg x 16 54-ba ll VFBGA

MT48LC4M16A2F41 4 Meg x 16 54-ba ll VFBGA
http://www.micron.com/support/FBGA/FBGA.asphttp://www.micron.com/support/FBGA/FBGA.asp


3/72



64Mb: x4, x8, x16 SDRAMAutom otive Temp erature

fully random access. Precharging one bank while accessing one of the other three bankswill hide the precharge cycles and provide seamless, high-speed, random-accessoperation.

The 64Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode

is provided, along with a power-saving, power-down mode. All inputs and outputs areLVTTL-compatible.

SDRAMs offer substantial advances in DRAM operating performance, including theability to synchronously burst data at a high data rate with automatic column-addressgeneration, the ability to interleave between internal banks in order to hide prechargetime, and the capability to randomly change column addresses on each clock cycleduring a burst access.

Auto m otive Tem peratureThe automotive temperature (AT) option adheres to the following specifications:

16ms refresh rate

Self refresh not supported Ambient and case temperatures cannot be less than 40C or greater than 105C


4/72


64MSDRAMTOC.f m - Rev. N 12/08 EN 4 2000 Micron Technolo gy, Inc. All right s reserved.

64Mb: x4, x8, x16 SDRAMTable of Contents

Table of Cont ents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Automotive Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Pin/Ball Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Operating Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Write Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

COMMAND INHIBIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18LOAD MODE REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21Bank/Row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35Burst Read/Single Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44Temperature and Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71


5/72


64MSDRAMLOF.fm - Rev. N 12/08 EN 5 2000 Micron Technolo gy, Inc. All right s reserved.

64Mb: x4, x8, x16 SDRAMList of Figures

List of Figures

Figure 1: 16 Meg x 4 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7Figure 2: 8 Meg x 8 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Figure 3: 4 Meg x 16 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 4: Pin Assignment (Top View) 54-Pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Figure 5: Ball Assignment (Top View, Ball Down) x16, 54-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10Figure 6: Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Figure 7: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Figure 8: Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Figure 9: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22Figure 10: READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Figure 11: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24Figure 12: Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25Figure 13: Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26Figure 14: READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27Figure 15: READ-to-WRITE With Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27Figure 16: READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28Figure 17: Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 18: WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30Figure 19: WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30Figure 20: WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31Figure 21: Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32Figure 22: WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32Figure 23: WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33Figure 24: Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34Figure 25: PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34Figure 26: Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35Figure 27: Clock Suspend During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36Figure 28: Clock Suspend During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36Figure 29: READ With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37Figure 30: READ With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38Figure 31: WRITE With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 32: WRITE With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39Figure 33: Example Temperature Test Point Location, 54-Pin TSOP: Top View . . . . . . . . . . . . . . . . . . . . . . . . . . .46Figure 34: Example Temperature Test Point Location, 54-Ball VFBGA: Top View . . . . . . . . . . . . . . . . . . . . . . . . .46Figure 35: Initialize and Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52Figure 36: Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53Figure 37: Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54Figure 38: Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55Figure 39: Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56Figure 40: READ Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57Figure 41: READ With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58Figure 42: Single READ Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59Figure 43: Single READ With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60Figure 44: Alternating Bank Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61Figure 45: READ Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Figure 46: READ DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63Figure 47: WRITE Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64Figure 48: WRITE With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65Figure 49: Single WRITE Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66Figure 50: Single WRITE With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67Figure 51: Alternating Write Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68Figure 52: WRITE Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69Figure 53: WRITE DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70Figure 54: 54-Pin Plastic TSOP II (400 mil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71Figure 55: 54-Ball VFBGA F4/B4 Package, 8mm x 8mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72


6/72


64MSDRAMLOT.fm - Rev. N 12/08 EN 6 2000 Micron Technolo gy, Inc. All right s reserved.

64Mb: x4, x8, x16 SDRAMList o f Table s

List o f Tables

Table 1: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Table 2: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2Table 3: 64Mb SDRAM Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 4: Pin/Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11Table 5: Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Table 6: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Table 7: Truth Table 1 Commands and DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18Table 8: Truth Table 2 CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39Table 9: Truth Table 3 Current State Bank n, Command to Bank n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40Table 10: Truth Table 4 Current State Bank n, Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42Table 11: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44Table 12: Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45Table 13: Thermal Impedance Simulated Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45Table 14: DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47Table 15: IDDSpecifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47Table 16: TSOP Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47Table 17: VFBGA Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47Table 18: Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .48Table 19: AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49


7/72



64Mb: x4, x8, x16 SDRAMFunctional Block Diagram s

Functional Block Diagram s

Figure 1: 16 Meg x 4 SDRAM

12

RAS#

CAS#

ROW-

ADDRESS

MUX

CLK

CS#

WE#

CKE

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODE REGISTER

10

COMMAND

DECODE

A0A11,

BA0, BA1

DQ M12

ADDRESS

REGISTER14

1024

(x4)

4096

I/O G ATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK0

MEMORYARRAY

(4,096 x 1,024 x 4)

BANK0

ROW-

ADDRESSLATCH

&

DECODER

4096

SENSE AM PLIFIERS

BANK

CONTROL

LOGIC

DQ0DQ3

4

4

DATA

INPUT

REGIS TER

DATA

OUTPUT

REGISTER

4

12

BANK1BANK2

BANK3

12

10

2

1 1

2

REFRESH

COU NTER


8/72





12

RAS#

CAS#

ROW-

ADDRESS

MUX

CLK

CS#

WE#

CKE

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODE REGISTER

9

COMMAND

DECODE

A0A11,

BA0, BA1

DQ M12

ADDRESS

REGISTER14

512

(x8)

4096

I/O G ATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(4,096 x 512 x 8)

BANK0

ROW-

ADDRESS

LATCH

&

DECODER

4096

SENSE AMP LIFIERS

BANK

CONTROL

LOGIC

DQ0DQ7

8

8

DATA

INPUT

REGIS TER

DATA

OUTPUT

REGISTER

8

12

BANK1BANK2

BANK3

12

9

2

1 1

2

REFRESH

COU NTER


9/72





12

RAS#

CAS#

ROW-

ADDRESS

MUX

CLK

CS#

WE#

CKE

COLUMN-

ADDRESS

COUNTER/

LATCH

8

A0A11,

BA0, BA1

DQML,

DQMH12

ADDRESS

REGIS TER14

256

(x16)

4096

I/O G ATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(4,096 x 256 x 16)

BANK0

ROW-

ADDRESS

LATCH

&

DECODER

4096

SENSE AM PLIFIERS

BANK

CONTROL

LOGIC

DQ0DQ15

16

16

DATA

INPUT

REGISTER

DATA

OUTPUT

REGIS TER

16

12

BANK1BANK2

BANK3

12

8

2

2 2

2

REFRESH

COUNTER

CONTROL

LOGIC

MOD E REGISTER

COMMAND

DECODE


10/72



64Mb: x4, x8, x16 SDRAMPin/Ball Assignm ents and Descriptio ns

Pin/Ball Assignm en ts and Description s

Figure 4: Pin Assignm ent (Top View ) 54-Pin TSOP

Not es: 1. The # symbo l indicat es signa l is active LOW. A da sh (-) indicat es x8 and x4 pin function is

same a s x16 pin f unction.

Figure 5: Ball Assignm ent (Top View , Ball Dow n) x16, 54-Ball VFBGA

Notes : 1. The ba lls a t A4, A5, and A6 are absent from the physical packag e. They are included to i llus-

trat e tha t row s 4, 5, an d 6 exist , but conta in no solder balls.

VDDDQ 0

VDD QDQ 1DQ 2VssQDQ 3DQ 4

VDD QDQ 5DQ 6VssQDQ 7VDD

DQMLWE#

CAS#

RAS#CS#BA0BA1A10

A0A1A2A3

VDD

1234567891011121314151617

18192021222324252627

5453525150494847464544434241403938

37363534333231302928

VssDQ15VssQDQ14DQ13VDD QDQ12DQ11VssQDQ10DQ 9VDD QDQ 8VssNCDQMHCLK

CKENCA11A9A8A7A6A5A4Vss

x8x16 x16x8 x4x4-

DQ 0-

NCDQ 1

-NC

DQ 2-

NCDQ 3

-NC-

NC--

----------

-NC-

NCDQ 0

-NCNC-

NCDQ 1

-NC-

NC--

----------

-DQ 7-NCDQ 6-NCDQ 5-NCDQ 4-NC--DQ M-

----------

-NC-NCDQ 3-NCNC-NCDQ 2-NC--DQ M-

----------

A

B

C

D

E

F

G

H

J

1 2 3 4 5 6 7 8

VSS

DQ14

DQ12

DQ10

DQ 8

DQ MH

NC/A12

A8

VSS

DQ15

DQ13

DQ11

DQ 9

NC

CLK

A11

A7

A5

VSSQ

VDD Q

VSSQ

VDD Q

VSS

CKE

A9

A6

A4

VDD Q

VSSQ

VDD Q

VSSQ

VDD

CAS#

BA0

A0

A3

DQ 0

DQ 2

DQ 4

DQ 6

DQ ML

RAS#

BA1

A1

A2

VDD

DQ 1

DQ 3

DQ 5

DQ 7

WE#

CS#

A10

VDD

9


11/72



64Mb: x4, x8, x16 SDRAMPin/Ball Assignm ents and Descriptio ns

Tab le 4: Pin/Ball Descriptio ns

TSOP PinNumbers

VFBGABall

Numbers Symbol Type Description

38 F2 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals aresampled o n t he po sitive edg e o f CLK. CLK also increment s the interna l

burst counter and controls the output registers.

37 F3 CKE Input Clock en a ble: CKE activat es (HIGH) a nd de a ctivat es (LOW) th e CLK

sig na l. Deactivating the clock provides PRECHARGE pow er-do w n a nd

SELF REFRESH ope ra tio n (a ll ba nks idle), ACTIVE pow er-do w n (row

a ctive in an y b a nk), o r CLOCK SUSPEND ope rat ion (burst/access in

prog ress). CKE is synchronous except a ft er th e d evice e nte rs pow er-

do w n an d self refresh mod es, w here CKE becom es asynchrono us until

a fte r exiting the same m od e. The input buff ers, including CLK, are

disab led during pow er-dow n an d self refresh mod es, providing low

stand by pow er. CKE ma y be t ied HIGH.

19 G9 CS# Input Chip select: CS# ena bles (reg iste red LOW) a nd disab les (reg iste red

HIGH) the comma nd decod er. All comma nds are m asked w hen CS# is

reg istere d HIGH, bu t READ/WRITE bu rsts alre a d y in pro g ress w ill

continue a nd DQM w ill retain its DQ mask capa bility w hile CS#

rema ins HIGH. CS# provides fo r externa l ba nk selection on system s

w ith multiple ba nks. CS# is considered part o f the comma nd cod e.

16, 17, 18 F9, F7, F8 WE# , CAS# ,

RAS#

Input Comm a nd inp uts: WE#, CAS#, and RAS# (a long w ith CS#) de fine t he

command being entered.

39 x4, x8:

DQ M

Input Input/out put m ask: DQM is an input ma sk sign al fo r w rite accesses an d

an output enab le signal for read accesses. Input d at a is masked w hen

DQM is sa mpled HIGH d uring a WRITE cycle. The ou tpu t buf fe rs are

placed in a High -Z state (tw o-clock la tency) whe n DQM is sam pled

HIGH during a READ cycle. On the x4 and x8, DQML (Pin 15) is a NC

an d DQMH is DQM. On the x16, DQML correspond s to DQ0DQ7 and

DQMH corresponds t o DQ8DQ15. DQML an d DQMH are con sidered

same sta te w hen referenced as DQM.

15, 39 E8, F1 x16:

DQML,

DQMH

20, 21 G7, G8 BA0, BA1 Input Ba nk ad dre ss input s: BA0 and BA1 def ine to w hich ba nk the ACTIVE,

READ, WRITE or PRECHARGE com ma nd is be ing a pplie d.

2326,

2934, 22,

35

H7, H8, J8,

J7, J3, J2,

H3, H2, H1,

G3, H9, G2

A0A11 Input Addre ss input s: A0A11 are samp led du ring th e ACTIVE com ma nd

(row -a dd ress A0A11) an d READ/WRITE comm a nd (colu mn -a dd ress

A0A9 [x4]; A0A8 [x8]; A0A7 [x16]; w ith A10 de fin ing a ut o

precharge ) to select on e locat ion out of t he mem ory array in the

respective bank. A10 is sa mpled during a precharg e comma nd t o

de termine w het her a ll ba nks are t o b e precha rged (A10[HIGH]) or

ba nk selecte d b y BA0, BA1 (A1[LOW]). The a d dre ss inpu ts a lso provid e

th e o p-cod e d uring a LOAD MODE REGISTER com ma nd .

2, 4, 5, 7, 8,

10, 11, 13,

42, 44, 45,47, 48, 50,

51, 53

A8, B9, B8,

C9, C8, D9,

D8, E9, E1,D2, D1, C2,

C1, B2, B1,

A2

DQ0DQ15 x16: I/O Da ta input /ou tpu t: Da ta bus fo r x16 (4, 7, 10, 13, 42, 45, 48, an d 51 a re

NCs for x8; and 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, and 53 are NCs for

x4).

2, 5, 8, 11,

44, 47, 50,

53

DQ0DQ7 x8: I/O Da ta input /ou tpu t: Da ta bus fo r x8 (2, 8, 47, 53 a re NCs for x4).

5, 11, 44,

50

DQ0DQ3 x4: I/O Dat a input /out put: Da ta bus for x4.

40 E2 NC No connect: These pins shou ld be left u nconne cted.


12/72



64Mb: x4, x8, x16 SDRAMFunctional Description

Functional DescriptionIn general, the 64Mb SDRAM (4 Meg x 4 x 4 banks, 2 Meg x 8 x 4 banks, and 1 Meg x 16 x 4banks) is a quad-bank DRAM that operates at 3.3V and includes a synchronous interface(all signals are registered on the positive edge of the clock signal, CLK). Each of the x4s16,777,216-bit banks is organized as 4,096 rows by 1,024 columns by 4 bits. Each of thex8s 16,777,216-bit banks is organized as 4,096 rows by 512 columns by 8 bits. Each of thex16s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selectedlocation and continue for a programmed number of locations in a programmedsequence. Accesses begin with the registration of an ACTIVE command which is thenfollowed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1select the bank, A0A11 select the row). The address bits (x4: A0A9; x8: A0A8; x16:

A0A7) registered coincident with the READ or WRITE command are used to select thestarting column location for the burst access.

Prior to normal operation, the SDRAM must be initialized. The following sectionsprovide detailed information covering device initialization, register definition,command descriptions and device operation.

Initialization

SDRAMs must be powered up and initialized in a predefined manner. Operationalprocedures other than those specified may result in undefined operation. After power isapplied to VDDand VDDQ (simultaneously) and the clock is stable (stable clock isdefined as a signal cycling within timing constraints specified for the clock pin), theSDRAM requires a 100s delay prior to issuing any command other than a COMMANDINHIBIT or NOP. Starting at some point during this 100s period and continuing at leastthrough the end of this period, COMMAND INHIBIT or NOP commands must beapplied.

Once the 100s delay has been satisfied with at least one COMMAND INHIBIT or NOPcommand having been applied, a PRECHARGE command should be applied. All banksmust then be precharged, thereby placing the device in the all banks idle state.

After the idle state, at least two AUTO REFRESH cycles must be performed. After theAUTO REFRESH cycles are complete, the SDRAM is ready for mode register program-ming. Because the mode register will power up in an unknown state, it must be loadedprior to applying any operational command. If desired, the two AUTO REFRESHcommands can be issued after the LOAD MODE REGISTER command.

36 G1 NC No con nect: Ma y be used a s add ress input s (A12) on the 256Mb an d512Mb de vices.

3, 9, 43, 49 A7, B3, C7,

D3

VDD Q Supply DQ pow er: Isola ted DQ pow er on the die for improved no ise

immunity.

6, 12, 46,

52

A3, B7, C3,

D7

VSSQ Supply DQ ground : Isola ted DQ ground on t he die fo r improved noise

immunity.

1, 14, 27 A9, E7, J9 VDD Supply Pow er supply: + 3.3V 0.3V.

28, 41, 54 A1, E3, J1 VSS Supply Ground.

Tab le 4: Pin/Ball Descriptio ns

TSOP PinNumbers

VFBGABall

Numbers Symbol Type Description


13/72




The recommended power-up sequence for SDRAMs:

1. Simultaneously apply power to VDDand VDDQ.

2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL-compatible.

3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timingconstraints specified for the clock pin.

4. Wait at least 100s prior to issuing any command other than a COMMAND INHIBITor NOP.

5. Starting at some point during this 100s period, bring CKE HIGH. Continuing at leastthrough the end of this period, 1 or more COMMAND INHIBIT or NOP commandsmust be applied.

6. Perform a PRECHARGE ALL command.

7. Wait at least tRP time; during this time NOPs or DESELECT commands must be given.All banks will complete their precharge, thereby placing the device in the all banksidle state.

8. Issue an AUTO REFRESH command.

9. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commandsare allowed.

10. Issue an AUTO REFRESH command.

11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commandsare allowed.

12. The SDRAM is now ready for mode register programming. Because the mode registerwill power up in an unknown state, it should be loaded with desired bit values prior toapplying any operational command. Using the LOAD MODE REGISTER command,program the mode register. The mode register is programmed via the MODE REGIS-TER SET command with BA1 = 0, BA0 = 0 and retains the stored information until it isprogrammed again or the device loses power. Not programming the mode registerupon initialization will result in default settings which may not be desired. Outputs

are guaranteed High-Z after the LOAD MODE REGISTER command is issued. Outputsshould be High-Z already before the LOAD MODE REGISTER command is issued.

13. Wait at least tMRD time, during which only NOP or DESELECT commands areallowed.

At this point the DRAM is ready for any valid command.

Note: If desired, more than two AUTO REFRESH commands can be issued in the sequence.After steps 9 and 10 are complete, repeat them until the desired number of AUTOREFRESH + tRFC loops is achieved.

Register Def inition

Mode Register

The mode register is used to define the specific mode of operation of the SDRAM. Thisdefinition includes the selection of a burst length, a burst type, a CL, an operating modeand a write burst mode, as shown in Figure 6 on page 15. The mode register isprogrammed via the LOAD MODE REGISTER command and will retain the stored infor-mation until it is programmed again or the device loses power.

Mode register bits M0M2 specify the burst length, M3 specifies the type of burst(sequential or interleaved), M4M6 specify the CL, M7 and M8 specify the operatingmode, M9 specifies the WRITE burst mode, and M10 and M11 are reserved for futureuse.


14/72


15/72




Figure 6: Mod e Register Definitio n

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved;this is referred to as the burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by the burst length, the burst typeand the starting column address, as shown in Table 5 on page 16.

3 = 0

1

2

4

8

Reserved

Reserved

Reserved

Full Page

M3 = 1

1

2

4

8

Reserved

Reserved

Reserved

Reserved

Operating Mode

St and ar d Op er a t io n

All other states reserved

0

0

Defined

0

1

Burst Type

S eq u en t i a l

Inter leaved

CAS Latency

Reserved

Reserved

2

3

Reserved

Reserved

Reserved

Reserved

Burst Length

M0

0

1

0

1

0

1

0

1

Burst Leng thCAS La tency BT

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Mod e Register (Mx)

Address Bus

9 7 6 5 4 38 2 1 0

M1

0

0

1

1

0

0

1

1

M2

0

0

0

0

1

1

1

1

M3

M4

0

1

0

1

0

1

0

1

M5

0

0

1

1

0

0

1

1

M6

0

0

0

0

1

1

1

1

M6M0M8 M7

Op Mo d e

A10A11

1011

Re se rve d WB

01

Write Burst Mode

Pr o gr ammed Bu rs t Lengt hSing le Locatio n Access

M9

Pr o gr amBA0, BA1,

M11, M10 = 0, 0to en sure compa t ibi li ty

w ith future de vices.


16/72




Not es: 1. For full-pag e a ccesses: y = 1,024 (x4); y = 512 (x8); y = 256 (x16).

2. For BL = 2, A1A9 (x4), A1A8 (x8), or A1A7 (x16) select t he blo ck-o f-tw o b urst; A0 selects

the s tart ing column w ithin the block.

3. For BL = 4, A2A9 (x4), A2A8 (x8), o r A2A7 (x16) select t he blo ck-o f-fo ur b urst; A0A1

select the start ing column w ithin the block.4. For BL = 8, A3A9 (x4), A3A8 (x8), o r A3A7 (x16) select t he blo ck-o f-eig ht bu rst; A0A2

select the start ing column w ithin the block.

5. For a f ull-pag e burst , the full row is selected and

6. A0A9 (x4), A0A8 (x8), or A0A7 (x16) select t he sta rtin g colum n.

7. Whenever a bounda ry of the b lock is reached w ithin a g iven seq uence above, the follow ing

access wra ps w ithin the block.

8. For BL = 1, A0A9 (x4), A0A8 (x8), o r A0A7 (x16) select th e u niq ue column to be a ccessed,

and mod e reg ister bit M3 is ignored.

CAS Latency

CL is the delay, in clock cycles, between the registration of a READ command and theavailability of the first piece of output data. The latency can be set to two or three clocks.

If a READ command is registered at clock edge nand the latency is mclocks, the data willbe available by clock edge n + m. The DQs will start driving as a result of the clock edgeone cycle earlier (n + m - 1), and provided that the relevant access times are met, the data

will be valid by clock edge n+ m. For example, assuming that the clock cycle time is suchthat all relevant access times are met, if a read command is registered at T0 and thelatency is programmed to two clocks, the DQs will start driving after T1 and the data willbe valid by T2, as shown in Figure 7 on page 17. Table 6 on page 17indicates the oper-ating frequencies at which each CL setting can be used.

Table 5: Burst Definitio n

BurstLe ng th St art in g Co lu mn A dd re ss

Order of Accesses Within a Burst

Type = Sequentia l Type = Inter leaved

2 A00 0-1 0-1

1 1-0 1-0

4 A1 A0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

8 A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full pa g e (y) n = A0A9/8/7

(location 0y)

Cn, Cn + 1, Cn + 2

Cn + 3, Cn + 4. ..

Cn - 1, Cn

Not supported


17/72




Reserved states should not be used as unknown operation or incompatibility with futureversions may result.

Figure 7: CAS Laten cy

Operating Mode

The normal operating mode is selected by setting M7 and M8 to zero; the other combi-nations of values for M7 and M8 are reserved for future use and/or test modes. The

programmed burst length applies to both read and write bursts.Test modes and reserved states should not be used because unknown operation orincompatibility with future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via M0M2 applies to both read and writebursts; when M9 = 1, the programmed burst length applies to read bursts, but writeaccesses are single-location (nonburst) accesses.

Tab le 6: CAS Late ncy

Speed

Allow able Operating Frequency (MHz)

CL = 2 CL = 3

-6 166

-7E 133 143

-75 100 133

CLK

DQ

T2T1 T3T0

CL = 3

LZ

D OU T

tOHt

COMMAND NO PREAD

tAC

NOP

T4

NOP

DONTCARE

UNDEFINED

CLK

DQ

T2T1 T3T0

CL = 2

LZ

DOU T

tOHt

COMMAND NO PREAD

tAC

NOP


18/72



64Mb: x4, x8, x16 SDRAMCommands

CommandsTruth Table 1 provides a quick reference of available commands. This is followed by a

written description of each command. Three additional Truth Tables appear followingOperation on page 21; these tables provide current state/next state information.

No t es: 1. A0A11 de f in e t h e o p -co de w r it t en t o t h e mo de r eg i st e r.

2. A0A11 provide row ad dress, and BA0, BA1 dete rmine w hich ba nk is ma de a ctive.

3. A0A9 (x4), A0A8 (x8), or A0A7 (x16) pro vide co lumn a dd ress; A10 (HIGH) ena ble s the

aut o precha rge f ea ture (nonpersistent), while A10 (LOW) disab les the a uto precharg e fe a-

ture; BA0, BA1 dete rmine wh ich ba nk is being read from o r writte n to .4. A10 (LOW): BA0, BA1 det ermine t he ba nk being precharg ed. A10 HIGH: All banks pre-

charged and BA0, BA1 are Don t Care.

5. This co mm a nd is AUTO REFRESH if CKE is (HIGH), SELF REFRESH if CKE is LOW.

6. Internal refresh counter controls row ad dressing; a ll inputs and I/Os are Don t Care except

fo r CKE.

7. Activat es or de a ctivat es the DQs during WRITEs (ze ro-clock dela y) a nd READs (tw o-clock

delay).

COMMAND INHIBIT

The command inhibit function prevents new commands from being executed by theSDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively dese-

lected. Operations already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM that isselected (CS# is LOW). This prevents unwanted commands from being registered duringidle or wait states. Operations already in progress are not affected.

Table 7: Truth Table 1 Com m ands and DQM OperationCKE is HIGH f o r a ll comm a nd s sho w n e xcept SELF REFRESH.

Nam e (Function) CS# RAS# CAS# WE# DQM ADDR DQs Notes

COMMAND INHIBIT(NOP) H X X X X X X

NO OPERATION (NOP) L H H H X X X

ACTIVE (Select ba nk a nd a ctivat e ro w ) L L H H X Ba nk/ro w X 2

READ

(Select ba nk an d column, a nd sta rt READ burst)

L H L H L/H8 Ba nk/co l X 3

WRITE

(Select ba nk an d colum n, a nd start WRITE burst)

L H L L L/H8 Ba nk/co l Va lid 3

BU RST TERMINATE L H H L X X Act ive

PRECHARGE

(Deact ivat e row in bank or ba nks)

L L H L X Co d e X 4

AUTO REFRESH o r SO FTREFRESH

(Ente r self refresh mod e)

L L L H X X X 5, 6

LOAD MOD E REGISTER L L L L X Op-co de X 1

Write ena ble/out put ena ble L Act ive 7

Write inhibit/ou tp ut High-Z H Hig h-Z 7


19/72




LOAD MODE REGISTER

The mode register is loaded via inputs A0A11. See mode register heading in RegisterDefinition on page 13. The LOAD MODE REGISTER command can only be issued whenall banks are idle, and a subsequent executable command cannot be issued until tMRD

is met.

ACTIVE

The ACTIVE command is used to open (or activate) a row in a particular bank for asubsequent access. The value on the BA0, BA1 inputs selects the bank, and the addressprovided on inputs A0A11 selects the row. This row remains active (or open) foraccesses until a precharge command is issued to that bank. A precharge command mustbe issued before opening a different row in the same bank.

READ

The READ command is used to initiate a burst read access to an active row. The value on

the BA0, BA1 inputs selects the bank, and the address provided on inputs A0A9 (x4), A0A8 (x8), or A0A7 (x16) selects the starting column location. The value on input A10determines whether auto precharge is used. If auto precharge is selected, the row beingaccessed will be precharged at the end of the read burst; if auto precharge is not selected,the row will remain open for subsequent accesses. Read data appears on the DQs subjectto the logic level on the DQM inputs two clocks earlier. If a given DQM signal was regis-tered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal

was registered LOW, the DQs will provide valid data.

WRITE

The WRITE command is used to initiate a burst write access to an active row. The valueon the BA0, BA1 inputs selects the bank, and the address provided on inputs A0A9 (x4),

A0A8 (x8), or A0A7 (x16) selects the starting column location. The value on input A10determines whether auto precharge is used. If auto precharge is selected, the row beingaccessed will be precharged at the end of the write burst; if auto precharge is notselected, the row will remain open for subsequent accesses. Input data appearing on theDQs is written to the memory array subject to the DQM input logic level appearing coin-cident with the data. If a given DQM signal is registered LOW, the corresponding data

will be written to memory; if the DQM signal is registered HIGH, the corresponding datainputs will be ignored, and a write will not be executed to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank orthe open row in all banks. The bank(s) will be available for a subsequent row access a

specified time (t

RP) after the precharge command is issued. Input A10 determineswhether one or all banks are to be precharged, and in the case where only one bank is tobe precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated asDont Care. After a bank has been precharged, it is in the idle state and must be acti-vated prior to any READ or WRITE commands being issued to that bank.

Auto Precharge

Auto precharge is a feature that performs the same individual-bank precharge functiondescribed above, without requiring an explicit command. This is accomplished by using

A10 to enable auto precharge in conjunction with a specific READ or WRITE command.


20/72




A precharge of the bank/row that is addressed with the READ or WRITE command isautomatically performed upon completion of the READ or WRITE burst, except in thefull-page burst mode, where auto precharge does not apply. Auto precharge is nonper-sistent in that it is either enabled or disabled for each individual READ or WRITE

command.Auto precharge ensures that the precharge is initiated at the earliest valid stage within aburst. The user must not issue another command to the same bank until the prechargetime (tRP) is completed. This is determined as if an explicit PRECHARGE command wasissued at the earliest possible time, as described for each burst type in Operation onpage 21.

BURST TERMINATE

The BURST TERMINATE command is used to truncate either fixed-length or full-pagebursts. The most recently registered READ or WRITE command prior to the BURSTTERMINATE command will be truncated, as shown in the Operation section of this datasheet. The BURST TERMINATE command does not precharge the row; the row will

remain open until a PRECHARGE command is issued.

AUTO REFRESH

AUTO REFRESH is used during normal operation of the SDRAM and is analogous toCAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonper-sistent, so it must be issued each time a refresh is required. All active banks must bePRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESHcommand should not be issued until the minimum tRP has been met after thePRECHARGE command as shown in the Operationsection.

The addressing is generated by the internal refresh controller. This makes the addressbits Dont Care during an AUTO REFRESH command. Regardless of device width, the64Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (commercial and indus-trial) or 16ms (automotive). Providing a distributed AUTO REFRESH command every15.625s (commercial and industrial) or 3.906s (automotive) will meet the refreshrequirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESHcommands can be issued in a burst at the minimum cycle rate (tRFC), once every 64ms(commercial and industrial) or 16ms (automotive).

SELF REFRESH

The SELF REFRESH command can be used to retain data in the SDRAM, even if the restof the system is powered down. When in the self refresh mode, the SDRAM retains data

without external clocking.

The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE

is disabled (LOW). After the SELF REFRESH command is registered, all the inputs to theSDRAM become Dont Care, with the exception of CKE, which must remain LOW.

After self refresh mode is engaged, the SDRAM provides its own internal clocking,causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in selfrefresh mode for a minimum period equal to tRAS and may remain in self refresh modefor an indefinite period beyond that.


21/72




The procedure for exiting self refresh requires a sequence of commands. First, CLK mustbe stable (stable clock is defined as a signal cycling within timing constraints specifiedfor the clock pin) prior to CKE going back HIGH. After CKE is HIGH, the SDRAM musthave NOP commands issued (a minimum of two clocks) for tXSR, because time is

required for the completion of any internal refresh in progress.Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every15.625s or less, as both SELF REFRESH and AUTO REFRESH utilize the row refreshcounter.

Self refresh is not supported on automotive temperature devices.

Operation

Bank/Row A ctivatio n

Before any READ or WRITE commands can be issued to a bank within the SDRAM, a rowin that bank must be opened. This is accomplished via the ACTIVE command, whichselects both the bank and the row to be activated (see Figure 8).

After opening a row (issuing an ACTIVE command), a READ or WRITE command may beissued to that row, subject to the tRCD specification. tRCD (MIN) should be divided bythe clock period and rounded up to the next whole number to determine the earliestclock edge after the ACTIVE command on which a READ or WRITE command can beentered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period)results in 2.5 clocks, rounded to 3. This is reflected in Figure 9 on page 22, which coversany case where 2 < tRCD (MIN)/tCK 3. (The same procedure is used to convert otherspecification limits from time units to clock cycles).

A subsequent ACTIVE command to a different row in the same bank can only be issuedafter the previous active row has been closed (precharged). The minimum timeinterval between successive ACTIVE commands to the same bank is defined by tRC.

A subsequent ACTIVE command to another bank can be issued while the first bank isbeing accessed, which results in a reduction of total row-access overhead. The minimumtime interval between successive ACTIVE commands to different banks is defined bytRRD.


22/72




Figure 8: Activat ing a Specific Row in a Specific Bank

Figure 9: Exam ple: Meet ing tRCD (MIN) When 2 < tRCD (MIN)/tCK 3

READs

READ bursts are initiated with a READ command, as shown in Figure 10 on page 23.

The starting column and bank addresses are provided with the READ command, andauto precharge is either enabled or disabled for that burst access. If auto precharge isenabled, the row being accessed is precharged at the completion of the burst. For thegeneric READ commands used in the following illustrations, auto precharge is disabled.

During READ bursts, the valid data-out element from the starting column address will

be available following the CL after the READ command. Each subsequent data-outelement will be valid by the next positive clock edge. Figure 11 on page 24shows generaltiming for each possible CL setting.

Upon completion of a burst, assuming no other commands have been initiated, the DQswill go High-Z. A full-page burst will continue until terminated. (At the end of the page, itwill wrap to column 0 and continue.)

CS#

WE#

CAS#

RAS#

CKE

CLK

A0A10, A11 ROWADDRESS

DONTCARE

HIGH

BA0, BA1 BANKADDRESS

CLK

T2T1 T3T0

t

COMMAND NOPACTIVEREAD or

WRITENOP

RCD (MIN)

tRCD (MIN) + 0.5 tCK

tCK tCK tCK

DONTCARE


23/72




Data from any READ burst may be truncated with a subsequent READ command, anddata from a fixed-length READ burst may be immediately followed by data from a READcommand. In either case, a continuous flow of data can be maintained. The first dataelement from the new burst follows either the last element of a completed burst or the

last desired data element of a longer burst which is being truncated.The new READ command should be issued xcycles before the clock edge at which thelast desired data element is valid, where x= CL -1. This is shown in Figure 12 on page 25for CL = 2 and CL = 3; data element n + 3is either the last of a burst of four or the lastdesired of a longer burst. The 64Mb SDRAM uses a pipelined architecture and thereforedoes not require the 2n rule associated with a prefetch architecture. A READ commandcan be initiated on any clock cycle following a previous READ command. Full-speedrandom read accesses can be performed to the same bank, as shown in Figure 13 onpage 26, or each subsequent READ may be performed to a different bank.

Figure 10: READ Com m and

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMNADDRESS

A0A9: x4A0A8: x8

A0A7: x16

A10

BA0, BA1

DONTCARE

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANKADDRESS

A11: x4A9, A11: x8

A8, A9, A11: x16


24/72




Figure 11: CAS Latency

CLK

DQ

T2T1 T3T0

CL = 3

LZ

D OU T

tOHt

COMMAND NOPREAD

tAC

NO P

T4

NO P

DONTCARE

UNDEFINED

CLK

DQ

T2T1 T3T0

CL = 2

LZ

D OU T

tOHt

COMMAND NO PREAD

tAC

NO P


25/72




Figure 12: Consecut ive READ Bursts

No t e : Ea ch READ co mma n d ma y b e t o a n y b a n k. DQM is LOW.

DONTCARE

CLK

DQDOUT

n

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,COL n

NOP

BANK,COL b

DOUTn+ 1

DOUTn+ 2

DOUTn + 3

DOUTb

READ

X = 1 cycle

CAS Lat ency = 2

CLK

DQDOUT

n

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS


BANK,COL n

NOP

BANK,COL b

DOUTn + 1

DOUTn + 2

DOUTn + 3

DOUTb

READ NOP

T7

X = 2 cycles

CAS Late ncy = 3

TRANSITIONING DATA


26/72




Figure 13: Rando m READ Accesses

No t e : Ea ch READ co mma n d ma y b e t o a n y b a n k. DQM is LOW.

Data from any READ burst may be truncated with a subsequent WRITE command, anddata from a fixed-length READ burst may be immediately followed by data from a

WRITE command (subject to bus turnaround limitations). The WRITE burst may beinitiated on the clock edge immediately following the last (or last desired) data elementfrom the READ burst, provided that I/O contention can be avoided. In a given systemdesign, there may be a possibility that the device driving the input data will go Low-Zbefore the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occurbetween the last read data and the WRITE command.

The DQM input is used to avoid I/O contention, as shown in Figures 14and 15onpage 27. The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITEcommand (DQM latency is two clocks for output buffers) to suppress data-out from theREAD. Once the WRITE command is registered, the DQs will go High-Z (or remainHigh-Z), regardless of the state of the DQM signal, provided the DQM was active on theclock just prior to the WRITE command that truncated the READ command. If not, thesecond WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in,then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid.

CLK

DQ

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP

BANK,COL n

DONTCARE

DOUTn

DOUTa

DOUTx

DOUTm

READ READ READ NOP

BANK,COL a

BANK,COL x

BANK,COL m

CLK

DQDOUT

n

T2T1 T4T3 T5T0

COMMAND

ADDRESS

READ NOP

BANK,

COL n

DOUTa

DOUTx

DOUTm

READ READ READ NOP

BANK,

COL a

BANK,

COL x

BANK,

COL m

CAS Lat ency = 2

CAS Lat ency = 3

TRANSITIONING DATA


27/72




The DQM signal must be de-asserted prior to the WRITE command (DQM latency iszero clocks for input buffers) to ensure that the written data is not masked. Figure 14shows the case where the clock frequency allows for bus contention to be avoided

without adding a NOP cycle, and Figure 15shows the case where the additional NOP is

needed.Figure 14: READ-to -WRITE

Note: CL = 3 is used fo r il lustra t ion. The READ command m ay be to any ba nk, and the WRITE

command may b e to any ba nk. If a burst o f on e is used, then DQM is not required.

Figure 15: READ-to-WRITE With Extra Clock Cycle

Note: CL = 3 is used fo r il lustra t ion. The READ command m ay be to any ba nk, and the WRITE

command may be to any bank.

DONTCARE

READ NOP NOP WRITENOP

CLK

T2T1 T4T3T0

DQ M

DQ DOUT n

COMMAND

D INb

ADDRESSBANK,COL n

BANK,COL b

DS

tHZ

t

tCK

TRANSITIONING DATA

DONTCARE

READ NOP NOPNOP NOP

DQ M

CLK

DQ DOUT n

T2T1 T4T3T0

COMMAND

ADDRESSBANK,COL n

WRITE

D INb

BANK,COL b

T5

DS

tHZ

t

TRANSITIONING DATA


28/72




A fixed-length READ burst may be followed by, or truncated with, a PRECHARGEcommand to the same bank (provided that auto precharge was not activated), and a full-page burst may be truncated with a PRECHARGE command to the same bank. ThePRECHARGE command should be issued xcycles before the clock edge at which the last

desired data element is valid, where x= CL -1. This is shown in Figure 16for eachpossible CL; data element n + 3is either the last of a burst of four or the last desired of alonger burst. Following the PRECHARGE command, a subsequent command to thesame bank cannot be issued until tRP is met. Note that part of the row precharge time ishidden during the access of the last data element(s).

In the case of a fixed-length burst being executed to completion, a PRECHARGEcommand issued at the optimum time (as described above) provides the same operationthat would result from the same fixed-length burst with auto precharge. The disadvan-tage of the PRECHARGE command is that it requires that the command and addressbuses be available at the appropriate time to issue the command; the advantage of thePRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.

Full-page READ bursts can be truncated with the BURST TERMINATE command, and

fixed-length READ bursts may be truncated with a BURST TERMINATE command,provided that auto precharge was not activated. The BURST TERMINATE commandshould be issuedx cycles before the clock edge at which the last desired data element isvalid, wherex = CL = -1. This is shown in Figure 17 on page 29for each possible CL; dataelement n + 3is the last desired data element of a longer burst.

Figure 16: READ-to -PRECHARGE

No te: DQM is LOW.

CLK

DQDOUT

n

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS


BANK,COL n

NOP

DOUT

n+ 1

DOUT

n+ 2

DOUT

n+ 3

PRECHARGE NOP

T7

DONTCARE

CLK

DQDOUT

n

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,COL n

NOP

DOUT

n + 1

DOUT

n + 2

DOUT

n + 3

PRECHARG E NOP

X = 1 cycle

CL = 2

CL = 3

X = 2 cycles

TRANSITIONING DATA


29/72




Figure 17: Term inatin g a READ Burst

No te: DQM is LOW.

WRITEs

WRITE bursts are initiated with a WRITE command, as shown in Figure 18 on page 30.

The starting column and bank addresses are provided with the WRITE command, andauto precharge is either enabled or disabled for that access. If auto precharge is enabled,the row being accessed is precharged at the completion of the burst. For the generic

WRITE commands used in the following illustrations, auto precharge is disabled.

During WRITE bursts, the first valid data-in element will be registered coincident withthe WRITE command. Subsequent data elements will be registered on each successivepositive clock edge. Upon completion of a fixed-length burst, assuming no othercommands have been initiated, the DQs will remain High-Z, and any additional input

data will be ignored (see Figure 19 on page 30). A full-page burst will continue untilterminated. (At the end of the page, it will wrap to column 0 and continue.)

Data for any WRITE burst may be truncated with a subsequent WRITE command, anddata for a fixed-length WRITE burst may be immediately followed by data for a WRITEcommand. The new WRITE command can be issued on any clock following the previous

WRITE command, and the data provided coincident with the new command applies tothe new command.

DONTCARE

CLK

DQDOUT

n

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOPNOP

DOUT

n+ 1

DOUT

n+ 2

DOUT

n+ 3

BURSTTERMINATE

ACTIVE

t RP

T7

CLK

DQDOUT

n

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOPNOP

DOUT

n+ 1

DOUT

n+ 2DOUT

n+ 3

BURSTTERMINATE

ACTIVE

t RP

T7

X= 1 cycle

CL = 2

CL = 3

X= 2 cycles

BANK a,

COL n

BANK a,

ROW

BANK

(aor a ll)

BANK a,

COL n

BANK a,

ROW

BANK

(aor a ll)

TRANSITIONING DATA


30/72




An example is shown in Figure 20 on page 31. Data n + 1is either the last of a burst of twoor the last desired of a longer burst. The 64Mb SDRAM uses a pipelined architecture andtherefore does not require the 2nrule associated with a prefetch architecture. A WRITEcommand can be initiated on any clock cycle following a previous WRITE command.

Full-speed random write accesses within a page can be performed to the same bank, asshown in Figure 21 on page 32, or each subsequent WRITE may be performed to adifferent bank.

Figure 18: WRITE Com ma nd

Figure 19: WRITE Burst

No t e : NOTE: B L = 2 . DQM is LOW.

DONTCAREVALID ADDRESS

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMNADDRESS

A10

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

A0A9: x4A0A8: x8A0A7: x16

A11: x4A9, A11: x8

A8, A9, A11: x16

BA0, BA1 BANKADDRESS

CLK

DQD INn

T2T1 T3T0

COMMAND

ADDRESS

NOP NOP

DONTCARE

WRITE

D INn+ 1

NOP

BANK,COL n

TRANSITIONING DATA


31/72




Figure 20: WRITE-to-WRITE

Note: DQM is LOW. Each WRITE command may be to a ny bank.

Data for any WRITE burst may be truncated with a subsequent READ command, anddata for a fixed-length WRITE burst may be immediately followed by a subsequent READcommand. After the READ command is registered, the data inputs will be ignored, and

writes will not be executed. An example is shown in Figure 22 on page 32. Data n + 1iseither the last of a burst of two or the last desired of a longer burst.

Data for a fixed-length WRITE burst may be followed by, or truncated with, aPRECHARGE command to the same bank (provided that auto precharge was not acti-vated), and a full-page WRITE burst may be truncated with a PRECHARGE command tothe same bank. The PRECHARGE command should be issued tWR after the clock edge at

which the last desired input data element is registered. The auto precharge moderequires a tWR of at least one clock plus time, regardless of frequency. In addition, whentruncating a WRITE burst, the DQM signal must be used to mask input data for the clock

edge prior to, and the clock edge coincident with, the PRECHARGE command. Anexample is shown in Figure 23 on page 33. Data n + 1is either the last of a burst of two orthe last desired of a longer burst. Following the PRECHARGE command, a subsequentcommand to the same bank cannot be issued until tRP is met.

In the case of a fixed-length burst being executed to completion, a PRECHARGEcommand issued at the optimum time (as described above) provides the same operationthat would result from the same fixed-length burst with auto precharge. The disadvan-tage of the PRECHARGE command is that it requires that the command and addressbuses be available at the appropriate time to issue the command; the advantage of thePRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.

CLK

DQ

T2T1T0

COMMAND

ADDRESS

NOPWRITE WRITE

BANK,COL n

BANK,COL b

DINn

DINn+ 1

DINb

DONTCARETRANSITIONING DATA


32/72




Figure 21: Random WRITE Cycles

Note: Each WRITE command may be to a ny bank. DQM is LOW.

Figure 22: WRITE-to-READ

Note: The WRITE command may be to any bank, and the READ command ma y be to any bank.

DQM is LOW. CL = 2 fo r illustra tio n.

DONTCARE

CLK

DQ D INn

T2T1 T3T0

COMMAND

ADDRESS

WRITE

BANK,COL n

DINa

DINx

DINm

WRITE WRITE WRITE

BANK,COL a

BANK,COL x

BANK,COL m

TRANSITIONING DATA

DONTCARE

CLK

DQ

T2T1 T3T0

COMMAND

ADDRESS

NOPWRITE

BANK,COL n

D INn

DINn+ 1

DOUTb

READ NOP NOP

BANK,COL b

NOP

DOUTb+ 1

T4 T5

TRANSITIONING DATA


33/72




Figure 23: WRITE-to-PRECHARGE

Note: DQM could remain LOW in this example if the WRITE burst is a f ixed length o f tw o.

Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATEcommand. When truncating a WRITE burst, the input data applied coincident with theBURST TERMINATE command will be ignored. The last data written (provided thatDQM is LOW at that time) will be the input data applied one clock previous to theBURST TERMINATE command. This is shown in Figure 24 on page 34, where data nisthe last desired data element of a longer burst.

PRECHARGE

The PRECHARGE command (Figure 25 on page 34) is used to deactivate the open row in

a particular bank or the open row in all banks. The bank(s) will be available for a subse-quent row access some specified time (tRP) after the PRECHARGE command is issued.Input A10 determines whether one or all banks are to be precharged, and in the case

where only one bank is to be precharged, inputs BA0, BA1 select the bank. When allbanks are to be precharged, inputs BA0, BA1 are treated as Dont Care. After a bank hasbeen precharged, it is in the idle state and must be activated prior to any READ or WRITEcommands being issued to that bank.

DONTCARE

DQ M

CLK

DQ

T2T1 T4T3T0

COMMAND

ADDRESS BANK a,COL n

T5

NOPWRITE PRECHARGE NOPNOP

D INn

D INn + 1

ACTIVE

t RP

BANK(aor all)

t WR

BANK a,ROW

DQ M

DQ

COMMAND

ADDRESS BANK a,COL n

NOPWRITE PRECHARGE NOPNOP

D INn

D INn+ 1

ACTIVE

t RP

BANK

(aor all)

t WR

BANK a,

ROW

T6

NOP

NOP

t WR @ t CLK 15ns

t WR = t CLK < 15ns

TRANSITIONING DATA


34/72




Power-Down

Power-down occurs if CKE is registered LOW coincident with a NOP or COMMANDINHIBIT when no accesses are in progress. If power-down occurs when all banks areidle, this mode is referred to as precharge power-down; if power-down occurs when

there is a row active in any bank, this mode is referred to as active power-down. Enteringpower-down deactivates the input and output buffers, excluding CKE, for maximumpower savings while in standby. The device may not remain in the power-down statelonger than the refresh period (tREF or tREFAT) since no refresh operations areperformed in this mode.

The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKEHIGH at the desired clock edge (meeting tCKS). See Figure 26 on page 35.

Figure 24: Term inatin g a WRITE Burst

No te : DQMs a re LOW.

Figure 25: PRECHARGE Com m an d

DONTCARE

CLK

DQ

T2T1T0

COMMAND

ADDRESSBANK,COL n

WRITEBURST

TERMIN ATENEXT

COMMAND

D INn

(ADDRESS)

(D ATA)

TRANSITIONING DATA

CS#

WE#

CAS#

RAS#

CKE

CLK

A10

DONTCARE

HIGH

All Banks

Bank Selected

A0A9

BA0,1 BANKADDRESS

VALID ADDRESS


35/72




Figure 26: Pow er-Dow n

Clock Suspend

The clock suspend mode occurs when a column access/burst is in progress and CKE isregistered LOW. In the clock suspend mode, the internal clock is deactivated, freezingthe synchronous logic.

For each positive clock edge on which CKE is sampled LOW, the next internal positiveclock edge is suspended. Any command or data present on the input pins at the time of asuspended internal clock edge is ignored; any data present on the DQ pins remainsdriven; and burst counters are not incremented, as long as the clock is suspended. (Seeexamples in Figures 27and 28on page 36.)

Clock suspend mode is exited by registering CKE HIGH; the internal clock and relatedoperation will resume on the subsequent positive clock edge.

Burst Read/Single Write

The burst read/single write mode is entered by programming the write burst mode bit(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in theaccess of a single column location (burst of one), regardless of the programmed burstlength. READ commands access

Documents

Micron SDRAM Datasheet