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5/10/2009 A. Matsuzawa 1
Mixed signal systems and integrated circuits
Akira Matsuzawa
Tokyo Institute of Technology
5/10/2009 A. Matsuzawa 2
Contents
• Mixed signal systems• High speed A/D converters• High speed D/A converters• Sigma delta A/D and D/A converters• Wireless systems and RF CMOS circuits• PLL and related systems
5/10/2009 A. Matsuzawa 3
Aim of this lecture
• Understanding basic current mixed signal systems– Wireless transceiver
• Understanding basic mixed signal circuit building blocks: basic operation method and basic design method
– A/D and D/A converter– Sigma-delta modulation– Phase Lock Loop and Delay Lock Loop– Low Noise Amplifier– Frequency Mixer– Voltage Controlled Oscillator and Frequency Synthesizer
5/10/2009 A. Matsuzawa 4
1. Mixed signal systems
5/10/2009 A. Matsuzawa 5
Current electronics andmixed signal technology
5/10/2009 A. Matsuzawa 6
Exciting digital consumer electronics world
SemiconductorTechnology
MediaProcessorBetter Look
Better SoundHigher Quality
Anywhere
ExcitingMultimedia
with System LSISolutions
ExcitingMultimedia
with System LSISolutions
Audio and Video
BroadcastingCommunication
Network
System and SoftwareTechnologies
Storage Media
Anytime
New consumer electronics era has been emerged.Key technologies are digital multimedia and System on a Chip.
5/10/2009 A. Matsuzawa 7
LCD Driver
LCD Drivers
LCD driver is a simple example of mixed signal LSI
5/10/2009 A. Matsuzawa 8
LCD Driver
Start
Shift Resigter 64
Flip-Flop
384 * 6 bits Latch
384 * 6 bits Latch
6bits*3=186bits*3=18
Carry
6bits*3=18
384 * Voltage Scalling DA Converter
D00-07D20-27D40-47
Flip-Flop
D10-17D30-37D50-57
384 * 6 bits level shifter
sele
ctor
1 64
6
6
6
6
6 6
6
6
Cotroler6bit *R,G,B*2=36bit
384 output
#1 #2 #8
XGA: 1024*RGB (=3072) → 3072/384=8LSIs
subpixel pixel
LCD driver is an array of DA converters
5/10/2009 A. Matsuzawa 9
Home Home ServerServer
NetworkNetwork
ITSITS
CS/BSCS/BS
WW--CDMACDMA
HII StationHII Station
DVDDVDDVCDVC
Digital TVDigital TV
Image of current electronicsDigital consumer electronics and networking drive current electronics.
ADSL, FTTH
DAB
Digital TV
Home network
Ethenet
IEEE 1394, USB, Blue tooth, Wireless LAN
5/10/2009 A. Matsuzawa 10
Mixed signal technology :Digital networkings
Side-streamDescramber
&Trellis, Viterbi decoder
DACDACDACDAC
250Mbaud (PAM-5)
ADCADCADCADC
3-NEXTCanceller
Echo Canceller
DFE
Slicer
Clock Recovery
FFE
TX1TX2
TX3TX4
Pulse Shaping
Side-streamScramber
&Trellis,Viterbi
Symbol EncoderLine
I/F 6b, 125MHz ADC, DAC
Analog circuit
Mixed signal technology enables high speed digital networking.
Digital circuit
Error correction
Equalization Encryption
Noise cancellation
Digital
Data and clock recovery
Data conversion
Analog
5/10/2009 A. Matsuzawa 11
x-DSL
ADSL:0.1MHz-1.1MHZVDSL:2.0MHz-3.5MHz
○ADSL-service, 0.5-8Mbps(Dwn)/1Mbps (Up) for 5~6Km○VDSL-service, 13-52Mbps(Dwn) for 0.3-1.5Km ,
RX-in
Anti-aliazingFilter
ADCAdaptive DFE
Deci-mationFilter
DDFS
Error CorrectionFEC
TX-out
ReconstractionFilter
DAC
Inter-polationFilter
DDFS
Error CorrectionFEC
○ 96-tap Decision Feedback Equalizer(DFE)
○ 4~256-QAM modulation→ 60MHz 10-bit ADC and DAC for VDSL→ 5MS/s 14-bit ADC and DAC for ADSL
○ T=8 Read-Solomon Forward Error Correction (FEC)
ADSL and VDSL use the mixed signal technology
5/10/2009 A. Matsuzawa 12
Mixed signal tech. ; Digital read channel
Variable Gain Amp.Variable
Gain Amp.Analog
FilterAnalog
FilterA to D
ConverterA to D
ConverterDigital
FIR FilterDigital
FIR FilterViterbiError
Correction
ViterbiError
Correction
ClockRecoveryClock
RecoveryVoltage
ControlledOscillator
Voltage ControlledOscillator
DataOut
Data In(Erroneous)
Data Out(No error)
Analog circuit
Digital circuit
Digital storage also needs high speed mixed signal technologies.
Pickup signal
5/10/2009 A. Matsuzawa 13
Mixed signal SoC for DVD RAM system
0.18um- eDRAM
24M Tr16Mb DRAM
500MHzMixed Signal
Goto, et al., ISSCC 2001
This enables high readability for weak signal from DVD RAM pickup.
World fastest and highly integrated mixed signal CMOS SoC
5/10/2009 A. Matsuzawa 14
Mixed signal SoC
PixelOperationProcessor
PixelOperationProcessor
IOProcessor
IOProcessor
AVDecode
Processor
AVDecode
Processor
Back -EndBack -End
SystemCont-roller
SystemCont-roller
CPU1CPU1CPU2CPU2
VCOVCO
ADCADC
Gm-CFilterGm-CFilter
PRMLRead
Channel
PRMLRead
ChannelServo DSPServo DSP
AnalogFront EndAnalog
Front End
Front-EndFront-EndAnalog FE+Digital R/C
0.13um, Cu 6Layer, 24MTr
Okamoto, et al., ISSCC 2003
Mixed signal SoC can realize full system integration for DVD application. Embedded analog is the key.
5/10/2009 A. Matsuzawa 15
Recent developed mixed signal CMOS LSIs
5G RF LAN 12b 50MHz ADC 2ch12b 50MHz DAC 2ch
AFE for ADLS 12b 20MHz ADC+DAC
Digital network1394b (1GHz)
AFE for Digital Camera12b 20MHz ADC+AGC
2GHz RF CMOS
AFE (Analog Front End)
5/10/2009 A. Matsuzawa 16
Application area in mixed signal CMOS tech.
NetworkCommunication
NetworkCommunication
RecordingRecording
OutputOutput
InputInput
・Cellular phone: PDC, W-CDMA・RR-Net: Bluetooth, IEEE802.11・Broad cast: STB, DTV, DAB
・Optical:FTTH, OC-xx・Metal: ADSL, VDSL, Power line modem
・Serial: IEEE1394, USB, Ethernet・Parallel: DVI, LVDS
・DVD, VDC, HDD
Wireless
Wired
・LCD, PDP, EL, Audio drive
・Camera, Others
Power supplyPower supply ・ Switching supply, Every LSIs (On-chip)
Almost all the products need mixed signal CMOS LSI tech.
5/10/2009 A. Matsuzawa 17
Digital technology in real world
• High robustness• Programmability• Time shift (memory)• Error correction• High Scalability
Pure digital
Media(Cable, Disc, Air, etc) Real world
Damaged digital
Recovered digital
Advantages of Digital Tech.
Mixed signal technology(Analog+Digital)
Mixed signal technology(Analog+Digital) Reconstruction
But, digital can address this issue by own advantages,but needs the help of analog tech.
NoiseDistortionInterferenceLimited bandwidth
Not only digital, but also analog;ADC, DAC, Filter, and PLL are needed
Digital signal suffers heavy damage in real world.
5/10/2009 A. Matsuzawa 18
Role of current analog technology
InterfaceDigital signalProcessingand control
Powersupply
ClockGeneration
Outer world
Energy conversion
Wireless com.
Wired com.
Recording
Image
Audio
Motor
Sensor
Analog: Physical aspectsDigital: Meta-physics
(Brain)
(Sense and actuate organ; Mouse, Eye, Ear, Nose, etc.)
(Digestive organ, Circulatory organ)
The role of current analog technology is an interface between digital technology and outer physical world. Analog supports digital.
5/10/2009 A. Matsuzawa 19
Basic technology for digital network and storage
AnalogProcessing
AnalogProcessing
DataConverter
DataConverter
Communicationprocessing
Communicationprocessing
Data compression
Data compression
NetworkStorage media
・Mod/ Demod・Channel select・Error correction・Protocol・Encryption
・MPEG2, 4・DSP・Codec
・A/D Converter・D/A Converter
・RF・Optical I/F・Cable drive・Signal Generation
Analog technology Digital technology
Analog and data converter technologies are needed for digital network and digital storage
5/10/2009 A. Matsuzawa 20
'85 '90 '951
10
100
50
20
5
2
Perf
orm
ance
Inde
x N
umbe
r
Perfec TV
DVCApplied System
6b,800MHz
8b,120MHz
10b,20MHz
10b, 30MHz
8b,20MHz
10b, 300MHz
10b, 20MHz,30mW
HDTV
Camera
MUSE Receiver
Video Camera
Wide-TV
HDTV
DigitalCamera
6b, 80MHz
8b, 100MHz
Video Switcher
Digital OSC
Digital OSC
Development of ADCs for digital consumer products
DVDBip / BiCMOS
CMOS
6b, 1GHz
Development of ADCs has contributed to the progress of digital consumer electronics.
5/10/2009 A. Matsuzawa 21
Progress in A/D converter; video-rate 10b ADC
1980 1982 1993 Now
Board Level (Disc.+Bip)20W
$ 8,000
Conventional product World 1st Monolithic
Bipolar (3um)2W
$ 800
World lowest power
CMOS (1.2um)30mW$ 2.00
CMOS (0.15um)10mW$0.04
SoC Core
ADC is a key for mixed signal technology.We have reduced the cost and power of ADC drastically;1/ 2,000 in Power and 1/200,000 in cost!
CMOS technology attained it.
Analog Devices Inc.
dulling past 20 years
Our development
Our development
Our development
5/10/2009 A. Matsuzawa 22
1
10
100
1000
10000
1980 1985 1990 1995 2000 2005 2010Year
Pow
er (m
W)
2
5
20
50
200
500
2000
5000 FlashTwo-stepSubrangingFolding/InterpolatingPipeline
OthersLook-ahead Pipeline
1
10
100
1000
10000
1980 1985 1990 1995 2000 2005 2010Year
Pow
er (m
W)
2
5
20
50
200
500
2000
5000 FlashTwo-stepSubrangingFolding/InterpolatingPipeline
OthersLook-ahead Pipeline
FlashTwo-stepSubrangingFolding/InterpolatingPipeline
OthersLook-ahead Pipeline
0.1
1.0
10.0
100.0
1980 1985 1990 1995 2000 2005 2010Year
Are
a si
ze (m
m2)
0.2
0.5
2.0
5.0
20.0
50.0FlashTwo-stepSubrangingFolding/InterpolatingPipeline
OthersLook-ahead Pipeline
0.1
1.0
10.0
100.0
1980 1985 1990 1995 2000 2005 2010Year
Are
a si
ze (m
m2)
0.2
0.5
2.0
5.0
20.0
50.0FlashTwo-stepSubrangingFolding/InterpolatingPipeline
OthersLook-ahead Pipeline
FlashTwo-stepSubrangingFolding/InterpolatingPipeline
OthersLook-ahead Pipeline
Power reduction Area reduction
Power and area reduction of video-rate 10b ADCs
Power and area of ADC have been reducing continuously.Currently, ADC can be embedded on a chip
5/10/2009 A. Matsuzawa 23
0.1
1.0
10.0
100.0
0.1 1 10
Process node (m)
Pow
er/M
Hz
(mW
/MH
z)
0.2 0.3 0.5 0.7 2 3 5 7
0.2
0.5
2.0
5.0
20.0
50.0
FlashTwo-stepSubrangingFolding/InterpolatingPipeline
OthersLook-ahead Pipeline
0.1
1.0
10.0
100.0
0.1 1 10
Process node (m)
Pow
er/M
Hz
(mW
/MH
z)
0.2 0.3 0.5 0.7 2 3 5 7
0.2
0.5
2.0
5.0
20.0
50.0
FlashTwo-stepSubrangingFolding/InterpolatingPipeline
OthersLook-ahead Pipeline
FlashTwo-stepSubrangingFolding/InterpolatingPipeline
OthersLook-ahead Pipeline
0.1
1.0
10.0
100.0
0.1 1 10Process node (m)
Are
a si
ze (m
m2)
0.2 0.5 2 5
0.2
0.5
2.0
5.0
20.0
50.0
FlashTwo-stepSubrangingFolding/InterpolatingPipeline
OthersLook-ahead Pipeline
0.3 0.70.1
1.0
10.0
100.0
0.1 1 10Process node (m)
Are
a si
ze (m
m2)
0.2 0.5 2 5
0.2
0.5
2.0
5.0
20.0
50.0
FlashTwo-stepSubrangingFolding/InterpolatingPipeline
OthersLook-ahead Pipeline
FlashTwo-stepSubrangingFolding/InterpolatingPipeline
OthersLook-ahead Pipeline
0.3 0.7
M. Hotta et al. IEICE 2006. June
Power and area reduction of video-rate 10b ADCs
5/10/2009 A. Matsuzawa 24
Early stage mixed signal CMOS LSI for CE
6b Video ADC
8b low speed ADC;DAC
Digital Video filter
8b CPU
1993 Model: Portable VCR with digital image stabilizing
Success of CMOS ADC and DAC enabled low cost mixed signal CMOS LSI.This also enabled low cost and low power digital portable AV products.
System block diagram
5/10/2009 A. Matsuzawa 25
Mixed signal system: Digital Camera
Current camera system uses digital technology.
5/10/2009 A. Matsuzawa 26
Ultra-high speed ADCs
8b, 120MHz, (1984)
World fastest 8b ADC
8b, 600MHz ADC (1991)
World fastest 8b ADC
6b, 1GHz ADC (1991)
World fastest in production(Dual Parallel method)
Ultra-high speed ADCs have been developed.
5/10/2009 A. Matsuzawa 27
Digital Oscilloscope
松下通信工業:10b 100MHz OSC (1986年)
横河電機: 8b 1GHz (1994年)
Ultra-high speed ADCs have realized Digital Oscilloscopes.
5/10/2009 A. Matsuzawa 28
Progress in high-speed ADC
0.1
10
Pd/2
N[m
W]
Reported Pd of CMOS ADCs
Conversion rate [x100Msps]
1
1mW/Gsps
10mW/Gsps
This Work
101
1 order down
6b, 1GHz ADC2W,1.5um Bipolar
6b, 800MHz ADC400mW, 2mm2
0.25umCMOS
7b, 400MHz ADC50mW, 0.3mm2
0.18umCMOS
ISSCC 2002
ISSCC 2000
ISSCC 1991
World fastest CMOS ADC
World lowest Pd HS ADC
World fastest 6b ADC
High speed ADC has reduced its power and area down to be embedded.
5/10/2009 A. Matsuzawa 29
System: DVD player
ConsoleConsolePanelPanel
HeadHeadAmpAmp
DemodulationDemodulationECCECC
ACAC--3 Output3 Output
MPEG 2MPEG 2VideoVideo
ACAC--3 Audio3 Audio
System ControllerSystem ControllerMCUMCU
CDCDDEMDEM
16M16MSDRAMSDRAM
DriverDriver
Optical DiscOptical Disc Optical Optical HeadHead
Pre AmpPre AmpStereo OutputStereo Output
Video OutputVideo Output
CopyCopyProtectionProtection
PhotoPhoto--receptivereceptiveCompoundCompound
ServoServoDSPDSP
AnalogAnalogFront EndFront End
ODCODC
AV DecoderAV DecoderRed Laser UnitRed Laser Unit
Servo DSPServo DSP System Controller MCUSystem Controller MCU
4M4MDRAMDRAM
Red LaserRed Laser
::FirstFirst--Gen.Gen.
::SecondSecond--Gen.Gen.
::ThirdThird--Gen.Gen.
::FourthFourth--Gen.Gen.
ReadReadChannelChannel
OSAPI
High-speedAnalog-Digital
32bit MCUDRAM Embedded Media Core
Processor
MPEGAlgorithm
Analog
Memory
Current electrical system is complicated and needs analog and memory.
5/10/2009 A. Matsuzawa 30
Full DVD system integration in 0.13um tech.
PixelOperationProcessor
PixelOperationProcessor
IOProcessor
IOProcessor
AVDecode
Processor
AVDecode
Processor
Back -EndBack -End
SystemCont-roller
SystemCont-roller
CPU1CPU1CPU2CPU2
VCOVCO
ADCADC
Gm-CFilterGm-CFilter
PRMLRead
Channel
PRMLRead
ChannelServo DSPServo DSP
AnalogFront EndAnalog
Front End
Front-EndFront-EndAnalog FE+Digital R/C
0.13um, Cu 6Layer, 24MTrOkamoto, et al., ISSCC 2003
Advanced mixed signal SoC has been successfully developed.
5/10/2009 A. Matsuzawa 31
Cost reduction in DVD Recorder
’2000 Model
’2003 Model
One-chip integration for hole DVD system has been realized.This makes circuit board simpler and contribute to the cost down,as well as performance up.
5/10/2009 A. Matsuzawa 32
Scaled CMOS technology
Seven latticesGate
Si
SiO2
100nm
Transistor Cu Interconnection
Current Scaled CMOS technology is very artistic.
Matsushita’s 0.13um CMOS technology
5/10/2009 A. Matsuzawa 33
CMOS as analog device
--++Embed in CMOS
--++Digital calibration
--++Analog calibration
--++Offset cancel
+-Low Sub. effect
CMOS is 10x to 100x of Bip.++--1/f noise
CMOS is 10x of Bip.++--Voltage mismatch
Almost same++fT
This results in Cp issue-+Low Capacitance
CMOS is ¼ of Bip.+-High gm
--++Low Input current
--++Switch actionCommentBipolarCMOS
Only CMOS can realizeswitched capacitor circuits
CMOS has a variety of techniquesto address the self issues
CMOS has many issues as analog device,but also has a variety of circuit techniques
5/10/2009 A. Matsuzawa 34
GHz operation by CMOS
inT
Cgmf2
Cutoff frequency of MOS becomes higher than that of Bipolar.Over several GHz operations have attained in CMOS technology
1995 2000 2005
1G
10G
100G
100M
Freq
uenc
y (H
z)
200M
500M
2G
5G
20G
50GfT : Bipolar (w/o SiGe)
fT
Year
eff
satTpeak
Lvf2
D R/C for HDDIEEE 1394
/60 (CMOS )Digital circuits
fT : CMOS
0.35um
0.25um0.18um
0.13um
fT
CellularPhone
/10 (CMOS )
CDMA
RF circuits
5GHz W-LAN
5/10/2009 A. Matsuzawa 35
World first 1394b transceiverFor 1Gbps networking
0.25um 3AL_CMOS
5Gbps Eye pattern
0.18um 4AL_CMOS
Test chip for 5Gbps wire line
Digital consumer needs over GHz wire line networking.CMOS has attained 5Gbps data transfer.
CMOS technology for over GHz networking
5/10/2009 A. Matsuzawa 36
Basic issue of analog in LSL technology
RuleDesign 1
tox
L
W
XjLeff
0.7x
Perf
orm
ance
(Log
)
Scaling
(Log)
Integration2
1L
Speed 5.1
1L
Dynamic range =
5.1LNoise + Mismatch+Distortion
Signal swing
Scaling Rule
Scaling can realize higher integration and higher speed yet low power for digital circuits.In contrast, analog performance is used to be degraded with scaling.
Architectural and circuit technology development has been needed.
5/10/2009 A. Matsuzawa 37
Wireless systems
PA
NLA
N
UWBBluetoothZigBee
802.11n(100M)
802.11a/g(54M)
IEEE802.11b(11M)
4G
2010
IEEE802.15
A-PHSPHS
HSDPA (14M)
W-CDMA(384k)
PDC
EV-DV(5.2M)
cdma2000-1XEV-DO(2.4M)
cdma20001x(144K)
IEEE802.20(4M)
EDGEGPRSGSM
2005年~
PA
NLA
NC
ellu
lar
UWBBluetoothZigBee
802.11n(100M)
802.11a/g(54M)
IEEE802.11b(11M)
4G
2010
IEEE802.15
A-PHSPHS
HSDPA (14M)
W-CDMA(384k)
PDC
EV-DV(5.2M)
cdma2000-1XEV-DO(2.4M)
cdma20001x(144K)
IEEE802.20(4M)
EDGEGPRSGSM
Data rate
The number of wireless standards are increasing
5/10/2009 A. Matsuzawa 38
Technology edge RF CMOS LSI
M. Zargari (Atheros), et al., ISSCC 2004, pp.96 K. Muhammad (TI), et al., ISSCC2004, pp.268
Discrete-time Bluetooth0.13um, 1.5V, 2.4GHz
Wireless LAN, 802.11 a/b/g0.25um, 2.5V, 23mm2, 5GHz
Many RF CMOS LSIs have been developed for many standards
5/10/2009 A. Matsuzawa 39
Current status of RF CMOS chip
• Current products– Bluetooth: 2.4GHz, CSR etc., major– Wireless LAN: 5GHz, Atheros etc., major– CDMA : 0.9GHz-1.9GHz, Qualcomm, becomes major– Zigbee: 2.4GHz, not yet, however must use CMOS– TAG: 2.4GHz, Hitachi etc., major
Major Cellular phone standard, GSM uses SiGe-BiCMOS technology
RF CMOS was a university research theme, however currently becomes major technology in wireless world.
5/10/2009 A. Matsuzawa 40
Why CMOS?
• Low cost– Must be biggest motivation– CMOS is 30-40% lower than Bi-CMOS
• High level system integration– CMOS is one or two generation advanced– CMOS can realize full system integration
• Stable supplyment and multi-foundries– Fabs for SiGe-BiCMOS are very limited. Slow price decrease and limited product capability
• Easy to use– Universities and start-up companies can use CMOS with low
usage fee, but SiGe is difficult to use such programs.
5/10/2009 A. Matsuzawa 41
Multi-standard issue
IMT-2000RF
GSMRF
BluetoothRF
GPSRF
GPSBB
BluetothBB
GSMBB
IMT-2000BB
MCU
Power
ReconfigurableRF DSP
Unification
Yrjo Neuvo, ISSCC 2004, pp.32
Unified wireless system
Multi-standards and multi chipsFuture cellular phone needs 11 wireless standard!!
Reconfigurable RF circuit is strongly needed for solving multi-standard issue.
Current
Future
5/10/2009 A. Matsuzawa 42
Scalable circuit design for wireless systems
Scalable and reconfigurable design is needed for addressing the multi-standard wireless systems
Changeable: ADC/DAC resolution and bandwidth
5/10/2009 A. Matsuzawa 43
Basics of analog to digital and digital to analog conversion
5/10/2009 A. Matsuzawa 44
Basic mixed signal system
DSPADC DACPre
Filter(low pass)
PostFilter
(low pass)AGC
Clock
Time continuous Time discrete Time continuous
Mixed signal systems has DSP, ADC, DAC, and pre/post filter basically.The signals are converted between time continuous and time discrete.
5/10/2009 A. Matsuzawa 45
Sampling theory
n
nTttv )( dtetvT
VeVtvT
TTntj
n
n
Tntj
n
2/
2/
22
)(1,)(
-fm +fm
F(x(t))
Time
Volta
gex(t)
Time domain Frequency domain
Time domain Frequency domainT: period 0 fc 2fc 3fc 4fc
Signal
SamplingPulse
1,1 2 njn e
TV
The signal has bandwidth of fm. Periodical sampling pulse has a period of T.
fc=1/T
Fourier expansion
n
Tntj
eT
tv21)(
5/10/2009 A. Matsuzawa 46
Sampling
n
nTttv )(
1
)()(n
cc fnfXfnfXfXtvtxFT: period
Time
x
x(t)
Time
x0 fc 2fc 3fc 4fc
X(t)v(t)
nTtnTxtvtxn
)()(
Sampling
Signal
SamplingPulse
Sampling process can be treated as the product of the signal and the sampling pulse
x(t)
v(t)
Frequency
Sampled signals have multi-sidebands at Nfc
5/10/2009 A. Matsuzawa 47
Frequency spectrum in sampled data.
nTtnTxtvtxn
)()(2
cos2cos2111)(1
2 jxjx
nn
Tntj eex
Tnt
Te
Ttv
.......23cos222cos22cos211)( tftftfT
tv ccc
.......23cos)(222cos)(22cos)(2)(1)()( tftxtftxtftxtxT
tvtx ccc
Thus x(t)v(t) can be regarded as a AM modulated signal that the career signal of which frequency is nfc and the modulated signal is x(t)
If simply assuming x(t) is single tone: xocos (2πfat)
tftftfTxtvtx c
n
aao 2cos2cos22cos)()(
1
12cos2cos2cos
n
acacao tfnftfnftf
Tx
)cos()cos(21coscos BABABA
Sampled signal has a sideband of +/- fa at around nfc
5/10/2009 A. Matsuzawa 48
Signal reconstruction from sampled data
fmfc-fm
fc+fm 2fc+fm2fc-fm
fc 2fc0
fmfc-fm
fc+fm2fc+fm2fc-fm
fc 2fc0
Signal overlap
Signal can not be separated
Signal non-overlap
Signal can be separated to reconstruct
2c
mff
2c
mff
Low pass filter
fc/2
If signal bandwidth is less than fc/2, signal can be reconstructed perfectly.
Nyquist condition
1
)()()(n
cc fnfXfnfXfXtvtxF F(x(t)v(t)): Fourier transform of x(t)v(t)X(f): Fourier transform of the analog signal
5/10/2009 A. Matsuzawa 49
Reconstruction from sampled signals
nTtnTxtvtxn
)()(
20
21
)(c
c
G
Sampled signal:
Time
x
Time
x
x(t)0dB
ωc/2
Angular frequency
Ideal Low pass filter
Pass Stop
Sampled signal Reconstructed signal
Ideal Low pass filter:
nTtf
nTtfnTxtyc
c
n
sin)()(
tftftv
c
c
sin)(
Sampled signal can be reconstructed to be continuous signal through low pass filter.
For the unit impulse signal
)()()( nTtvnTxtyn
5/10/2009 A. Matsuzawa 50
Reconstruction by sampling function
Original signal
Sampling
再生過程 Reconstruction
Sampling function
nTtf
nTtfnTxtyc
c
n
sin)()(
tf
tftSc
c
sin)(
cfT 1
Signal can be reconstructed by the convolution between sampling signal and sampling function.
)()()( nTtSnTxtyn
5/10/2009 A. Matsuzawa 51
Aliasing effect
Frequencies are folded
csigc
sigalias
csigccsigalias
fnffnffnf
fnfnfnfff
12
12:1
212:
Noise
Accumulated Noise
Signals of which frequencies are higher than fc/2 are folded to the lower frequencies L.T. fc/2.
Nose which spreads wide frequency is also folded to lower frequency and accumulated.
Low pass filter is needed
Caution!!
Sampled signal is conventionally Noisy
5/10/2009 A. Matsuzawa 52
Special technique: Under sampling
2GHz
Bandwidth is 8MHz
Carrierfc=20MHz
2GHz carrier
20MHz sampling
8MHz signal
Under sampling technique
By using under sampling technique, we can obtain modulated signal from very high carrier frequency.However, very low SNR due to noise accumulation.
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Reconstruction process
Interpolated signals
Sampled signals
Reconstructed signals and interpolation
Conversion period
Conversion frequency
Spectrum of reconstructed signals
Spectrum of over sampled signals
Folding noise
Folding noise
Required LPF spec.
Original signal
Reconstructed signals has also folding frequency components.Thus DAC need post low pass filter. The interpolation technique can relax the required LPF spec.
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Aperture effect in DAC
Time
x
Time
x
Ideal impulse train Actual Step pulse train in DAC output
DSP DAC
Frequency characteristics of DAC
Sign
al in
tens
ity
c
c
ff
ff
fA
sin
)(
Aperture effect
High frequency signal of DAC is decreased
Use aperture correction filter that has inverse frequency characteristics.
Reduce the pulse width by using small duty pulse
Increase the conversion frequency using over sampling technique
Due to the aperture effect, the higher frequency component of the output signal from DACIs decreased. Sometime some technique is needed.
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Frequency spectrums in ADC and DAC
Input signal to ADC
Signal in ADC and DSP
Signal from DAC without the aperture effect
Signal from DAC with the aperture effect
Folding
Re-folding
Aperture effect
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Quantization
+
Nominal full-scale
Effective full-scale
Analog input
Dig
ital o
utpu
t
Ideal line
Minimum step (1LSB)
Quantizationerror
Input signal Quantized signal
Quantization noise
Analog to Digital Converter
Quantized signal = Input signal + Quantization noise
0 to 2N-1
0 to 2N
LSB (Least Significant Bit)
Quantization step
Ideal quantization error
ADC has a finite resolution number and the signal is quantized.This causes error called “quantization error”.
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Quantization noise and SNR
qx
qxqxp
5.0,0
5.0,1)(
25.0
5.0
2
231)(
qdxxpxNq
2
22
21
qSN
)(76.102.6
)5.1log(102log20log10/
dBNNSSNR N
qrmsrms
Step: q
Full scale:
Ideal quantization error
Signal intensity
qS N2
Probability density of quantization error
Noise power
Signal power
Signal to Noise Ratio
Quantization causes noise and this noise power reduces with increase of resolution number.Principal signal to noise ratio (dB) of N bit ADC is about 6N+2.The higher resolution of ADC realizes the higher SNR for signal processing.
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SNR increase by increasing fsc
Frequency
Frequency
fc=10MHz
fc=20MHz
fc/2=10MHz
fc/2=5MHz
Signal=2MHz
Signal=2MHz
fb=5MHz
Half noise powerIs removed
Quantizationnoise
Quantizationnoise
Conversionclock
Conversionclock
NoiseAfter LPF
2x conversion rate
Total Noise power is same,but power density is lower
b
crmsrms
ffNSNR
2log1076.102.6/
fc: Conversion frequencyfb: Bandwidth of LPF
We can increase SNR by increasing of conversion frequency with low pass filter.
3dB higher SNR by 2x higher fc