Multi-bunch Feedback System Review and Challenges for 1-2GHz

Multi-bunch Feedback System Review and Challenges for 1-2GHz

Japan Synchrotron Radiation Research Institute (JASRI)SPring-8

T. Nakamura

CFA Beam Dynamics Mini Workshop on Low Emittance Rings 2011, 2011-10-05

Collective Effect Study at SPring-8Calculation of Impedance of Beam Pipe Components by MAFIAInstability Simulation Based on the estimated Impedance with Home made Codes

CISR : Coupled-bunch Instability Simulation (C++)SISR : Single-Bunch Instability Simulation

http://www.spring8.or.jp/pdf/en/ann_rep/95/p157-158.pdfhttp://www.spring8.or.jp/pdf/en/ann_rep/95/p159-160.pdfhttp://www.spring8.or.jp/pdf/en/ann_rep/95/p161-162.pdfhttp://acc-physics.kek.jp/SAD/SAD2006/Doc/Slide/Nakamura.pdf

Observation of CSRhttp://www.pasj.jp/web_publish/pasj2009pubfinal/papers/

wpbta05.pdfResistive-Wall Impedance of ID shielded by Cu Sheet

http://accelconf.web.cern.ch/accelconf/p01/PAPERS/TPPH129.PDFObservation of Fast Ion Instability and Cure by gap in Bunch Trains

http://accelconf.web.cern.ch/accelconf/p01/PAPERS/TPPH127.PDFCure of Transverse Instabilities by Chromaticity Modulation

http://accelconf.web.cern.ch/accelconf/p95/ARTICLES/WAC/WAC14.PDF

http://accelconf.web.cern.ch/AccelConf/IPAC10/papers/thobra02.pdf

http://acc-web.spring8.or.jp/~nakamura

Feedback* Detect Oscillation by Beam Position Monitor (BPM)* Calculate the Kick to Damp its Oscillation* Drive Kicker with Power Amplifier

Multi-bunch Feedback (Bunch-by-bunch Feedback)

* Suppression of Instabilities* Fast Damping of Oscillation excited by Injection perturbation

Bunch-by-bunch Feedback (BBF)Control Oscillation Bunch-by-bunch ( independently )

Digital : ADC, DAC sampling rate = bunch rate ( fB )Required Frequency in baseband (kicker amplifier) ~ fB /2

* BBF Processor with FPGA based 508MS/s Processor (world first?) => SPring-8, PF, TLS, SOLEIL, SSRF, HLS, PLS (PLS-II), and several ion rings. * Simultaneous suppression of 10mA/bunch mode-coupling insta. + 0.05mA/bunch train multi-bunch Insta.

BPM KickerStorage Ring

fB : Bunch rate 500MHz -> 2GHz

DACsampling rate

fB

ADC sampling rate

fB

Position History(Turn-by-turn)

for Each Bunches

Digital Feedback ProcessorFPGA

Kick Signal

PositionSignal

A BA-B

Digital Bunch-by-bunch Feedback System

~ fB/ 2

180 deg.hybrid

PowerAmp.

FIRfilter

Front End

Kickfor

Each Bunches

FIR Filter(Digital Signal Processing)


KickFIRfilter

Current Turn

Output = KickInput = Bunch Position (turn-by-turn) y0x-1

-90 deg Phase Shift

€

yn = ak xn −kk =1

N

∑

HOW?

FIR filterNumber of Taps

FIR filter in FPGA

x-2

x-3

0-1-2-3-4-5-6-7-8-9Turn No

9-tap FIR Filter for SPring-8 Storage Ring9 Position History => Feedback Kick

Larger Taps Smaller Noise PowerNarrower Tune Acceptance....

Number of Taps > One PeriodFor Smaller Noise Power

Phase vs. TuneGain vs. Tune

FIR filter coefficients ak

QH QV

QV QH

T. Nakamura, et al. http://accelconf.web.cern.ch/AccelConf/e04/PAPERS/THPLT068.pdf

€

yn = ak xn −kk =1

N

∑

2GHz system for CLIC DR

2GHz system for CLIC DR

Higher frequency (Design)2 GHz 4 x

500MHz ( SPring-8 )Smaller beam size (Design)

2 um ( β = 5m)　 1/2 x 5um ( SPring-8 )

Stronger Damping (Assumption, 1/10 x τRadiation )

0.2 ms 1/2 x 0.5 ms ( SPring-8 )

Noise effect on Beam Size4 x 2 x 2 ~ One order Higher than

SP8

BPM Kicker

DACsampling rate

fB

ADC sampling rate

fB


for Each Bunches

Kickfor

Each Bunches

Digital Feedback ProcessorDigital Signal Process

Kick Signal

PositionSignal

A BA-B


~ fB/ 2

180 deg.hybrid

PowerAmp.Front End

Storage Ring


FIRfilter

Front-EndRF Direct Sampling and Baseband Sampling

Front-EndRF Direct Sampling and Baseband Sampling : 500MHz

DownConversion

BasebandSampling

180

deg

hybr

id

∆∆ = A-B

A

B

ADC Bandwidth > 250MHz

30kHz

250MHz

30 kHz ~ 250 MHz

Baseband signal

500MHz ± 30kHz

BPM Signal ∆

250MHz ~ 750 MHz

DirectSampling(SPring-8)

ADC Wide Bandwidth > 1.5 fRF = 750MHz

500MHz

LPF~ 300MHz

T. Nakamura, et al., http://cern.ch/AccelConf/e08/papers/thpc128.pdf

0.5 fB – 1.5 fB

1/2 fB

~ fB

fB ± 1/2 fB 500 ± 250MHz

Front-EndRF Direct Sampling and Baseband Sampling : 2 GHz

ADC : ~ 3 GHz

180

deg

hybr

id

∆∆ = A-B

A

B

ADC : ~ 1GHz

2 GHz

DirectSampling

DownConversion

BasebandSampling

30kHzBaseband signal

~2 GHz

2GHz ± 1GHz

BPM Signal ∆

1 GHz ~ 3 GHz

tens kHz ~ 1 GHz

LPF~ 1.5 GHz

NS ADC12D1800RF (2.8GHz(-3dB))

~ fB

fB – 1.5fB

1GHz0.5 fB

Front-EndRF direct sampling

* Less Components => Less tuning points* High Frequency

requires Wide bandwidth of ADCsuffers Large noise by ADC sampling jitter

Baseband Sampling* More Components* Low Frequency

Smaller effect of ADC sampling jitter Jitter of Mixing signal (500MHz, 2GHz) is small

Square Wave Mixing* More Components * Much LOWER Frequencyhttp://accelconf.web.cern.ch/AccelConf/e04/PAPERS/THPLT068.pdf

BPM Kicker

DACsampling rate

fB

ADC sampling rate

fB


for Each Bunches

Kickfor

Each Bunches

Digital Feedback ProcessorDigital Signal Process

Kick Signal

PositionSignal

A BA-B


~ fB/ 2

180 deg.hybrid

PowerAmp.

FIRfilter

Front End

Storage Ring


DigitalFeedback Processor

FPGA ( Field Programmable Gate Array )User Reconfigurable Hardware Logic

FastParallelLow cost


ADC sampling timing

Signal Divider fBADC

ADC

ADC

ADC

Digital Feedback Processor


DAC

MultiplexerFIR

FIRFIRFIR

Front End

SPring-8 Processor (2004)tested/installed at ~ten storage rings

fB / 4 (<300MHz)FPGA

A BA-B ~500 ns

fB : Bunch rate Harmonics = 4n

http://accelconf.web.cern.ch/AccelConf/ica05/proceedings/pdf/P3_022.pdf


fBDe-

Multiplexer

ADC

DAC

MultiplexerFIR

FIRFIRFIR

Digital Feedback Processor

BPM Kicker

Front End

A BA-B

FPGAfB / 4 (<300MHz)

with RecentFast ADC

fB

Storage Ring

fB : Bunch rate Harmonics = 4n

Dimtel

Bunch-by-bunch Feedback System for 2GHzBPM KickerStorage Ring

2GHz : Bunch rate

Harmonics = 12n ( 2652 = 12 x 7 x 13 x 17)

167 MHz

AD9739A

2GS/s DAC

A BA-B

DAC

Multiplexer

Multiplexer

1GS/s

Multiplexer

Xilinx Virtex-6/7

FIRFIRFIR

FIRFIRFIRFIRFIRFIR

FIRFIRFIR

De-Multiplexer

De-Multiplexer

De-Multiplexer

De-Multiplexer

1, 13,

2, 14,

5, 17,

6, 18,

NS ADC12D1800

Power Divider

1GS/s ADC

1GS/s ADC

Front End

De-

Multiplexer

De-

Multiplexer

2GS/s ADC 500MHzFPGA

12-bit

Bunch-by-bunch Feedback System for 2GHz

FPGA


2GHz : Bunch rate

Harmonics = 8n

250MHzFIRFIR

FIRFIR

FIRFIR

FIRFIR

A BA-B

2GS/s ADC 500MHz

NS ADC12D1800Multiplexer

1GS/s

Multiplexer

1GS/s ADC

1GS/s ADC

De-

Multiplexer

De-

Multiplexer

Xilinx Virtex-6/7

De-Multiplexer

De-Multiplexer

De-Multiplexer

De-Multiplexer

1, 9,

5, 13,

2, 10,

AD9739A

2GS/s DAC

DAC

Multiplexer

Front End 14-bit

12-bit

Power Divider

Step size = 0.25 umAcceptance = 1mm (+/- 0.5mm)

ADC resolution (How many bits ?)Step size << Beam size 2um (CLIC DR), 5um (SP8)Acceptance < Maximum Amplitude 0.2 – 0.3 mm

for SPring-8 by Injection perturbation

Acceptance 1 mm (+/- 0.5mm)

Number of Step = Acceptance / Step Size = 1mm / 0.25um = 4000 = 12bits

Beam size : 2um ~ noise level

Step size : 0.25um Maximum Amplitude

for SPring-8

0.2-0.3 mm

=> 12-14 bit ADC

But Noise is much larger than step size

Digital Feedback Processor for 2GHz

Required Specifications and CandidatesADC Bandwidth > 3 GHz for RF Direct Sampling

> 1 GHz for Baseband SamplingNS ADC12D1800RF

DAC Sampling Rate > 2 GS/s Bandwidth > 1 GHz Analog Devices AD9739A

FPGA FIR filter > 167 MHz ( 2GHz / 12 )

Xilinx Virtex-6/7

CLIC Pre-Damping Ringbunch rate 2GHz, Harmonics 2652 = 12 x 13 x 17

baseband

RF direct

Effect of Noise

Excitation of Betatron motion

Noise => Feedback System => Kicker

< 1/10 of Beam Sizes

Increase Effective Beam Size

Noise Sources

Beam Position Monitor NoiseThermal noiseAmplifier

Noise by AD samplingSampling Jitter

ADC, BPM signal timing jitter, …

Position Resolution

Revolution Freq. T0 4.8 µs

Total Damping Time τ ~ τFB 0. 5 ms

Amplitude σx < 0.1 x Beam Size 5 µm

Position Resolution σδ = 10σx < m for one passage

€

σ x =T0τ

τ FB

σ δResidual oscillation excited by Noise

KickerFeedback Beam

High Position Resolution is required€

σ x = 0.1σ δ

T. Nakamura, et al., EPAC’04, http://accelconf.web.cern.ch/AccelConf/e04/PAPERS/THPLT068.pdfT. Nakamura, NanoBeam ’05, http://atfweb.kek.jp/nanobeam/files/proceeding/proc-WG3b-12.pdf http://beam.spring8.or.jp/nakamura/papers/Nanobeam05/proc-WG3b-12.pdf

Residual Oscillation Excited by Noise

SPring-8

x + δNoise in Position Signal (BPM resolution, AD conversion, … )

Position Resolution σδ = 2µm for one passage

Residual Oscillation Excited by Noise

E ~ 3GeV, C ~ 400m , T0 = 1.3 µs Ver. Emittance εV 1 pm (Norm. 5 nm)Rad. Damping Time τβ 2 ms

€

σ x =T0τ

τ FB

σ δ

Feedback Damping Time τ ~ τFB = 0.2 ms ~ 0.1 x

τβ

Allowable Amplitude σx < 0.1 x Beam Size σV

~ 0.1 σδ

CLIC Damping Ring

Beam size (Ver.) σV 2 um ( βV = 5m)

Just the assumption

ADC Performance on Noise

ADC Noise Level < σδ < 2 um (DR) Acceptance < 1 mm (+/- 0.5mm)

Maximum Amplitude 0.2 – 0.3 mm for SPring-8 by Injection perturbation

ADC S/N ratio > 1 mm / 2 um = 500 = 54 dB

σx ~ 0.1 σδ < 0.1 x Beam size : 2 um (DR)Position Resolution

* The most of noise comes from Jitter of ADC clock* SNR in spec. sheets is defined for almost full swing signal

For feedback, it’s Residual Signal it might be possible to keep small

=> lower SNR than Spec sheet

SNR

76 dB

073 dB

77 dB

50 dB

60 dB

75 dB

74 dB

300MHzInput Frequency

SNRBaseband

RF direct

Input Frequency0 3 GHz2 GHz1 GHz

AD 9467-250(16bit, 250MS/s, 60fs jitter )

ADC12D1800RF (12bit, 2GS/s, 0.2 ps jitter)

ADC S/N ratio (SNR) > 54 dB

ADC Noise by Sampling Jitter

ADC Sampling Timing Jitter

Ext. Clock, ADC inside, …

∆τ

∆x = x 2πf ∆τ

Noise can be reduced by reducing Residual Signal

Noise

x

Residual Signal In A-B

Residual Signal at input to ADCand

Jitter of ADC Sampling=> Noise

BPM Difference Signal

Create Difference Signal (A-B) of Two BPM Electrodes (A,B)By adjusting Signal Level and Timing

Open or Short End(100 % Reflection)

BPM

0.1dB/step = 1%/step

BPM

180 deg. Hybrid

A

B

ADCA-B

1% ~ 100um

Residual Signal of BPM at ADC InputReflections at Connections <= uncontrollable Shape Difference of BPM Electrodes => Bad Cancelation at 180 deg. Hybrid => Residual Signal

Attenuator

Attenuator

~ 1%/step

A-B2ns

6dB

6dB

BPMOpen or Short End(100 % Reflection)

Reflection180 deg. Hybrid

A

B1GHz BW

4GHz BW BPM signal40mm

(bad BPM)

Residual Signal and Jitter of ADC Sampling => Noise

∆x= +160μm

( 0 dB )

2nsADC Sampling Timing

(-0.2dB = -2%)∆x = -160μm

80μm

BPM A-B Signal

to ADC

Noise by Sampling Jitter

σδ = x (rms)

∆x

by reflection...

(0.2dB = 2%)

Residual Signal

T. Nakamura, K. Kobayashi, and Z. Zhou, http://cern.ch/AccelConf/e08/papers/thpc128.pdf

6dB

6dB

BPM

A

B

A-B180 degHybrid

= 0.003 for 1 GHz= 0.009 for 3 GHz

= 0.25 μm for 1 GHz= 1.8 μm for 3 GHz

OK for 2GHz

ADC Sampling Timing Jitter

ADC

A-B

A-B

A-B

σδ < 2 m

BaseBand

RF direct

∆τ = 0.5 ps

(rms)

Noise

x=200μm for 3GHz€

xx

= 2πf∆τ

x= 80 μm for 1GHz

High Resolution Beam Position MonitorFor SPring-8 0.2 nC bunch ( 100mA x 2 ns ) one passage of 2ns separation (wide band)

σδ = 10σx < m

High Resolution BPM by Shorted Stripline Structure

Beam

20 mm

45 mm

V

H

σδ = σV = 5m

Almost OK for < m

1/4 part x 10 higher Resolution than Button BPM

T. Nakamura, http://accelconf.web.cern.ch/AccelConf/d05/PAPERS/POW027.PDF

for Ne /bunch =1.2×109

one passage(1/3.4 of CLIC DR)

Beam Position Monitor for 2 GHz

* Many BPMs for High Resolution Measurement (reduction of noise)

to achieve < 2um resolution for one passage

Smaller Size for Fast Response (high frequency)Lower signal level => Worse Resolution

Reduction of Beam Pipe boreResolution ~

1/(bore)2Sensitivity (∆V/V)/∆x ~ 1/(bore)

Reduction of Noise by Residual Signal

Cutoff < 3 GHz (TE modes)BPM at high beta for large beam size

Kicker

Kick by sin wave input = Field Strength x Kicker Length x F

€

F = 12L /c

cosωtdt−L / c

L / c∫ =sin ωL /c( )

ωL /c

= Reduction Factor for sin wave input

Kick to the bunch = Integral of 2L/c period

t2L/c

Input

t = 0 LBunch

t = L/c Bunch

Kicker

€

Leff = Lsin ωL /c( )

ωL /c

Effective Length

Kicker Transit Time Factor and Effective Length

Transit Time Factor

Effec

tive

Leng

thL = 0.3m

L = 0.15mL = 0.075m

2L/c =2 x 0.3m/c = 1/500MHz

t

For 1GHz ( fB = 2GHz)

Many Short ( ~ 0.075m ) Kickers are requiredfor 1 GHz ( fB = 2GHz )

Kicker Transit Time Factor and Effective Length

at High Beta for smaller number or lower amplifier

power

90x40-1 V

Ex = 8V/m

Ey = 8V/m

0 V

0 V 0 V

Diagonal Kicker

Ex = 9 V/m

Ey = 18 V/m -1 V

-1 V

0 V

0 V

-1V70x40

Ex = 19 V/m

Ey = 8V/m -1 V0 V

0V

Orthogonal Kicker B

Orthogonal Kicker COrthogonal Kicker A

90x40

Stripline Kickers in SPring-8

90x40

Ey = 12V/m

Ex = 16 V/m-1 V0V

0V

-1VSUS

SUS

Cu

SUSLength 30cm

Length 30cm

Length 7cm

Length 40 cm

Power Amplifier for Kicker* Frequency : a few tens kHz – 1 GHz

AR, R&K, ...

* Kick Strength~ Amplitude of beam (injection, ... )

x Feedabck Damping Time

Kicker Power ~ (Kick Strength ) 2

Reduce Amplitude of beam

YES : Multi-bunch Feedback For 2GHz is Possible with Current Technologies for ADC, DAC, FPGA, BPM, Kicker,

...

The development cost~ 300 k Euro including several processorsSPring-8 case in 2004, we paid Tokyo Electron Device

20 M JPY ( 150 k Euro at the rate in 2004 )3 Processors for 500MHz,FPGA program,Linux device driver / Application for

USB controlHalf year after specification was fixed

Acknowledgement:K. Kobayashi (SPring-8) for development of SPring-8 feedbackTokyo Electron Device Limited (http://www.teldevice.co.jp/eng/index.html)

for the help at the development of SPring-8 feedback and discussion on performance of current FPGA

Multi-bunch Feedback For 2GHz Bunch rate ?

Lower NoiseMore Number of Bits

If

are Required

How aboutSquare Wave Mixing Front-End

Lower Noise, More Bits => Square Wave Mixing Front-End

Lower NoiseMore Number of Bits

16-bit ADC ( AD 9467-250 ) Slow Sampling Rate < 250 MHz

Low Input Frequency < 300MHz for S/N ratio > 70dB

If

are RequiredSNR

73 dB

300MHz0MHz

AD 9467-250(16bit, 250MS/s)

Square Wave Mixing (24-way)Sampling Rate : 2 GS/s => 167 MS/sBandwidth : 1 GHz => 150 MHz

Big margin for Sampling Jitter!

SNR

Low jitter Frequency divider fB => fB/12 is required (or Frequency Multiplier fB/12 => fB )

75 dB

Square Wave Mixing : 6-way (500MHz/2 -> 117 MHz)85 MHz=500/6.

1ns

2ns

117MHz6ns

ADC

ADC

ADC

ADC

ADC

ADC

500MHz, 6-way250 MHz => 117MHz85 MS/s

Signal Divider

2GHz , 24-way 1GHz => ~ 117MHz, 167MS/s

T. Nakamura, et al. http://accelconf.web.cern.ch/AccelConf/e04/PAPERS/THPLT068.pdf

Contamination from Neighboring bunches

ADC sampling

Frequency Response by contamination

Low Jitter !!

Simultaneous suppression of 10mA/bunch mode-coupling instability + 0.05mA/bunch train multi-bunch Instability

By Bunch Current Sensitive Automatic Attenuator

EPAC’08, GenoaICALEPCS’09, Kobe

High Resolution BPM

Bunch Current x Position

Bunch Current

Singlet

10 mA 0.05mA/bunch

High EfficiencyKicker

Bunch train

Bunch Current Sensitive Automatic Attenuator

Digital Control

AnalogControl

ADC

ADC

ADC

ADCSignal Divider

Position

DAC

FPGABunch Current => Attenuation

A BA+B A-B

Storage Ring

Kick Signal

508MS/s

FPGA12-bitADC12-bitADC12-bitADC12-bitADC

Signal Divider

Digital Signal

Processing( FIR filter )

SPring-8 Feedback Processor

DAC

( Fast Variable Attenuator )

　 1/Bunch Current


Documents

Multi-bunch Feedback System Review and Challenges for 1-2GHz