New Computer Architecture Chapter 3-2 Arithmetic for computersnyx.skku.ac.kr/wp-content/uploads/2017/08/CA-lec3-2.pdf · 2017. 9. 19. · 성균관대소프트웨어대학신동군

1성균관대소프트웨어대학신동군

Computer Architecture

Chapter 3-2

Arithmetic for computers


Integer Multiplication

• “Paper and pencil” exampleMultiplicand 1000

Multiplier x 1001

1000

0000

0000 Shift after each step

+ 1000

Product 01001000

• m bits x n bits = m+n bit product

• Binary rules

– 0 => place 0 ( 0 x multiplicand)

– 1 => place a copy ( 1 x multiplicand)

• 3 versions of unsigned multiply hardware algorithm

– successive refinement


Multiplication Hardware Version 1

• 64-bit Multiplicand reg/ALU/Product reg

• 32-bit multiplier reg


Multiplication Algorithm Version 1

Initially 0


Multiplication Example (11x9)

Iter. Step Product Multiplicand Multiplier Action

0 0 00000000 00001011 1001 Initialize

1 1a. 00001011 00001011 1001 Add

1 2,3 00001011 00010110 0100 Shifts

2 1 00001011 00010110 0100 Test-no add

2 2,3 00001011 00101100 0010 Shifts

3 1 00001011 00101100 0010 Test-no add

3 2,3 00001011 01011000 0001 Shifts

4 1a. 01100011 01011000 0001 Add

4 2,3 01100011 10110000 0000 Shifts

01100011 = 1 + 2 + 32 + 64 = 99


Observations on Multiplication Version 1

• 1 clock per step => ~ 100 clocks per multiply

– Frequency(multiply) is much lower than Frequency(add)

• Amdahl’s law on uncommon cases

• Half the bits of the multiplicand are always 0

– 64-bit adder is wasted

• 0’s inserted in right of multiplicand as shifted

– LSBs of product never changed once formed

• Instead of shifting the multiplicand to the left we can shift the product to the right...



• 32-bit Multiplicand reg/ALU/Multiplier reg

• 64-bit Product reg




Observation on Multiplication Version 2

• Product register wastes space (lower half = 0)

• Combine Product register and Multiplier register



• 32-bit Multiplicand reg/ALU

• 64-bit Product reg, (no Multiplier reg)




Multiplication Example (11x9)

Iter. Step Product Multiplicand Action

0 0 00001001 1011 Initialize

1 1a. 10111001 1011 Add

1 2 01011100 1011 Shift

2 1 01011100 1011 Test-no add

2 2 00101110 1011 Shift

3 1 00101110 1011 Test-no add

3 2 00010111 1011 Shift

4 1a. 11000111 1011 Add

4 2 01100011 1011 Shift

Note: Multiplier in Product Register is underlined

How about 13x7 ?


Observations on Multiplication Version 3

• 2 steps/bit because Multiplier and Product shifts are combined

• MIPS registers Hi,Lo are left and right half of Product• mflo, mfhi

• MIPS instruction– mult rs, rt / multu rs, rt 64-bit product in HI/LO– mfhi rd / mflo rd

• Move from HI/LO to rd• Can test HI value to see if product overflows 32 bits

– mul rd, rs, rt Least-significant 32 bits of product –> rd• Signed multiplication

– one solution: make both positive– leave out the sign bit, run for 31 steps– set sign bit negative if signs of inputs differ– Better solution: Booth’s Algorithm

• multiply two’s complement signed numbers• uses same hardware as before• can also be used to reduce the number of steps


Faster Multiplication Hardware

1

Log2(32) or five 32-bit add times rather than 32 add times


Division: Paper and Pencil

• Example (unsigned): 74 / 8 = 9 Remainder 2

• Algorithm:

– If Partial Remainder > Divisor• then Quotient bit = 1; Remainder = Remainder - Divisor

• else Quotient bit = 0

– Shift down next dividend bit

• 3 versions of divide, successive refinement

1001

10010101000

1000

10101000

10

Divisor

Quotient

Dividend

Remainder


Division Hardware Version 1

• 64-bit Divisor reg (divisor in upper half)

• 64-bit ALU

• 64-bit Remainder reg

• 32-bit Quotient reg

Initially dividend

Initially divisor in left half


Division Algorithm Version 1

N+1 steps for N-bitQuotient and Remainder


Division Example

Example: 7 / 3 = 2; remainder 1.Iter Step Remainder Divisor Quotient Action

0 0 000111 011000 000 Initialize

1 1 101111 011000 000 Subtract

1 2b. 000111 011000 000 Restore; sll; Q0=0

1 3 000111 001100 000 Shift divisor

2 1 111011 001100 000 Subtract

2 2b. 000111 001100 000 Restore; sll; Q0=0

2 3 000111 000110 000 Shift divisor

3 1 000001 000110 000 Subtract

3 2a. 000001 000110 001 sll; Q0=1

3 3 000001 000011 001 Shift divisor

4 1 111110 000011 001 Subtract

4 2b. 000001 000011 010 Restore; sll; Q0=0

4 3 000001 000001 010 Shift divisor


Observations on Division Version 1

• Half the bits in divisor always 0

– Half of 64-bit adder is wasted

– Half of divisor is wasted

• Instead of shifting the divisor right, we can shift the remainder left

• The first step cannot produce a 1 in quotient bit (otherwise the quotient will be too big)

– switch order to shift first and then subtract, saves 1 iteration



• 32-bit Divisor register, 32 -bit ALU, 64-bit Remainder register, 32-bit Quotient register



Start

0. Remainder = Dividend << 1;

1. Remainderhi = Remainderhi - Divisor

TestRemainder

2a. Quotient << 1;Quotient ++;

2b. Remainderhi = Remainderhi+Divisor;Quotient<<1;

32Repetitions?

Affects UpperHalf of Remainder

Takes n Steps forN-bit Quotient and

Remainder

Done

3. Remainder<< 1;

Remainder 0 Remainder < 0

No

Yes


Observations on Division Version 2

• Remainder register loses a bit every cycle

• Quotient gains a bit every cycle

• We can eliminate the Quotient register by combining it with the Remainder register

– Shift both to the left in one statement (by shifting the Remainder left as before and putting quotient in LSBs).

– Loop contains only two steps:• subtract

• restore/leave and shift

– Consequence of combining two registers and new order of operations in loop:

• remainder shifted left one time too many.

– Final correction step must shift back remainder in the left halfof the register.



•32-bit Divisor reg, 32 -bit ALU, 64-bit Remainder reg, (0-bit Quotient reg)



Start

0. Remainder = Dividend << 1;

1. Remainderhi = Remainderhi - Divisor

TestRemainder

2a. Remainder << 1;Remainder ++;

2b. Remainderhi = Remainderhi+Divisor;Remainder <<1;

32Repetitions?

Done. Remainderhi >>1

Remainder 0 Remainder < 0

No

Yes


Another Divide Example

• Example: 14 / 3 = 4; remainder 2.

Iter Step Remainder Divisor Action

0 0 0001 1100 0011 Initialize

1 1 1110 1100 0011 Subtract: Remainder<0

1 2b. 0011 1000 0011 Restore; shift in 0

2 1 0000 1000 0011 Subtract; Remainder>=0

2 2a. 0001 0001 0011 Shift in a 1





3 0010 0100 0011 Shift remainder right

Rem. Quot.


Observations on Divide Version 3

• Same Hardware as Multiply:

– ALU to add or subtract

– 64-bit register to shift left or shift right

• Hi and Lo registers in MIPS

– combine to act as 64-bit register for multiply and divide

• Instructions

– div rs, rt / divu rs, rt

– No overflow or divide-by-0 checking

• Software must perform checks if required

– Use mfhi, mflo to access result

Restoring vs. Nonrestoring Division

(r + d) x 2 - d = r x 2 + d x 2 - d = r x 2 + d

Restore & subtract nonrestore & add


Divide Example (Nonrestoring)

• Example: 14 / 3 = 4; remainder 2.

Iter Step Remainder Divisor Action

0 0 0001 1100 0011 Initialize


1 2b. 1101 1000 0011 shift in 0

2 1 0000 1000 0011 Add; Remainder>=0

2 2a. 0001 0001 0011 Shift in a 1


3 2b. 1100 0010 0011 shift in 0

4 1 1111 0010 0011 Add; Remainder<0

4 2b. 0100 0100 0011 Restore (add 0011); shift in 0

3 0010 0100 0011 Shift remainder right

Rem. Quot.


Signed Division

• The simplest is:

– to remember signs,

– make positive, and

– complement quotient and remainder if necessary

• Dividend = Quotient x Divisor + Remainder

– +7 / +2 = 3 x 2 + 1

– -7 / +2 = -3 x 2 - 1 = -4 x 2 + 1

• Dividend and Remainder are defined to have same sign

• Quotient negated:

– if Divisor sign and Dividend sign disagree

- (x ÷ y) ≠ (-x) ÷ y


Floating Point (a brief look)

• We need a way to represent

– numbers with fractions, e.g., 3.1416

– very small numbers, e.g., .000000001

– very large numbers, e.g., 3.15576 ×109

• Representation:

– sign, exponent, significand: (–1)sign × significand × 2exponent

– more bits for significand gives more accuracy

– more bits for exponent increases range

• IEEE 754 floating point standard:

– single precision: 8 bit exponent, 23 bit significand

– double precision: 11 bit exponent, 52 bit significand


IEEE 754 floating-point standard

• Leading “1” bit of significand is implicit

• Exponent is “biased” to make sorting easier

– all 0s is smallest exponent; all 1s is largest

– bias of 127 for single precision and 1023 for double precision

– summary:

• Example:

– decimal: -.75 = - ( ½ + ¼ )

– binary: -.11 = -1.1 x 2-1

– floating point: exponent = 126 = 01111110

– IEEE single precision: 10111111010000000000000000000000

Why place the exponent before the significand?

Bias)(ExponentS 2Fraction)(11)(x


IEEE 754 Encoding

Single precision Double precision Object represented

Exponent Fraction Exponent Fraction

0 0 0 0 0

0 Nonzero 0 Nonzero denormalized number

1-254 Anything 1-2046 Anything floating-point number

255 0 2047 0 Infinity

255 Nonzero 2047 Nonzero NaN

Smallest positive normalized number:1.0000 0000 0000 0000 0000 000two x 2-126

Smallest positive denormalized number:0.0000 0000 0000 0000 0000 001two x 2-126

-127 (x)

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New Computer Architecture Chapter 3-2 Arithmetic for computersnyx.skku.ac.kr/wp-content/uploads/2017/08/CA-lec3-2.pdf · 2017. 9. 19. · 성균관대소프트웨어대학신동군