Nonlinearity and Mismatch - 國立中興大學cc.ee.nchu.edu.tw/~aiclab/teaching/AIC/lect13.pdf · Nonlinearity and Mismatch 類比電路設計(3349) - 2004 Analog-Circuit Design

1

Ching-Yuan Yang

National Chung-Hsing UniversityDepartment of Electrical Engineering

Nonlinearity and Mismatch

類比電路設計(3349) - 2004

13-1 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

Overview

ReadingB. Razavi Chapter 13.

IntroductionIn this lecture, we study two imperfections that prove critical in high-precision analog design and trade with many other performance parameters. These effects are nonlinearity and mismatch.We first define metrics for quantifying the effects of nonlinearity. Next, we study nonlinearity in differential circuits and feedback systems and examine several linearization techniques. We then deal with the problem of mismatch and dc offsets in differential circuits. Finally, we consider a number of offset cancellation methods and describe the effect of offset cancellation on random noise.

2


General considerations of nonlinearity

Input/output characteristic of a nonlinear system

Distortion in a common-source stageFor a small input swing, the output is a reasonable replica of the input but for large swings the output exhibits “saturated” level.


General considerations of nonlinearity (cont’d)

Distortion in a differential pair

Variation of small-signal gain in a nonlinear amplifier

3


Definition of nonlinearity

Approximate the input/output characteristic by a Taylor expansion:y(t) = α1 x(t) + α2 x2(t) + α3 x3(t) + ⋅⋅⋅

For small x, y(t) ≈ α1 x(t), indicating that α1 is the small-signal gain in the vicinity of x ≈ 0.

Specify the maximum deviation of the characteristic from an ideal one:


Harmonic distortion

Approximate the input/output characteristic by a Taylor expansion:y(t) = α1 x(t) + α2 x2(t) + α3 x3(t) + ⋅⋅⋅

If x(t) = A cosωt, theny(t) = α1 A cosωt + α2 A2 cos2ωt + α3 A3 cos3ωt + ⋅⋅⋅

=Higher-order terms yield higher harmonics. In particular, even-order terms and odd-order terms result in even and odd harmonics, respectively. Notethat the magnitude of the nth harmonic grows roughly in proportion to the nth power of the input amplitude.Harmonic distortion: the effect is quantified by summing the power of all of the harmonics (expect that of the fundamental) and normalizing the result to the power of the fundamental. Such a metric is called the “total harmonic distortion” (THD).

For a third-order nonlinearity:

Harmonic distortion is undesirable in most signal processing applications, including audio and video systems.

[ ] [ ] L+++++ )3cos(cos34

)2cos(12

cos3

32

21 ttAtAtA ωωαωαωα

( ) ( )( )23

31

33

222

4/34/2/

AAAATHD

αααα

+

+=

4


Nonlinearity of differential circuits

Differential circuits exhibit an odd-symmetric input/output characteristic, i.e., f(−x) = −f(x).y(t) = α1x(t) + α3x3(t) + α5x5(t) + ⋅⋅⋅, indicating that a differential circuit driven by a differential signal produces no even harmonics.Single-ended and differential amplifiers providing a small-signal voltage gain:

For the single-ended common-source stage,

The amplitude of 2nd harmonic normalized to that of the fundamental is

( ) DTHGSoxnDmv RVVL

WCRgA −=≈ µ

( )

( ) ( )

( ) [ ])2cos(141cos

cos21cos

21

cos21

2

222

20

tVL

WCtVVVL

WCI

tVL

WCtVVVL

WCVVL

WC

tVVVL

WCI

moxnmTHGSoxn

moxnmTHGSoxnTHGSoxn

mTHGSoxnD

ωµωµ

ωµωµµ

ωµ

++−+=

+−+−=

+−=

( )THGS

m

F

HD

VVV

AA

−=

42 ⋅⋅⋅⋅⋅ (A)


For the differential amplifier,

If |Vin| << VGS − VTH, then

Since , we obtain

If , then

2221 )(4

21

inTHGSinoxnDD VVVVL

WCII −−=− µ

−

−−=

−

−−≈

−−−=−

2

33

2

2

2

2

21

)(8coscos)(

)(81)(

)(41)(

THGS

mmYHGSinoxn

THGS

inYHGSinoxn

THGS

inYHGSinoxnDD

VVtVtVVVV

LWC

VVVVVV

LWC

VVVVVV

LWCII

ωωµ

µ

µ

4)3cos(cos3cos3 ttt ωωω +

=

2

3

2

3

21 )(32)3cos(cos

)(323

THGS

mm

THGS

mmmDD VV

tVgtVV

VVgII−

−

−

−=−ωω

2

3

)(83

THGS

mm VV

VV−

>>

2

23

)(32 THGS

m

F

HD

VVV

AA

−≈ ⋅⋅⋅⋅⋅ (B)

5


Discussion

The differential circuit exhibits much less distortion than its single-ended counterpart while providing the same voltage gain and output swing.For example, if Vm = 0.2(VGS − VTH), (A) and (B) yield a distortion of 0.5% and 0.125%, respectively.While achieving a lower distortion, the differential pair consumes twice as much as power as the CS stage because ISS = 2I. The key point, however, is that even if the bias current of M0 is raised to 2I, (A) predicts that the distortion decreases by only a factor of (with W/L maintained constant).

2


Feedback system incorporating a nonlinear feedforward amplifier

Assume that the amplifier in the system has an input-output characteristic y ≈ α1x + α2x2. If x(t) = Vmcosωt, then the output contains a fundamental component and a 2nd harmonic:y ≈ acosωt + bcos2ωt.

Determine a and b :ys = x(t) − β y(t) = Vmcosωt − β(acosωt + bcos2ωt) = (Vm − βa)cosωt − βbcos2ωty(t) = α1 ys + α2 ys

2

=

Thus,

Assume α2 and b are small quantities, yielding and hence

( ) ( )[ ] ( )L+

−+−+−−− taVbtbaVaV m

mm ωβαβαωββαβα 2cos2

cos2

2121

( )( ) ( )2

22

121aVbbaVba m

mβαβαββαα −

+−=−−=

( )31

22

1

1

11

21 βαα

βαα

+=

+= m

mVbVa

( )aVa m βα −≈ 1

6


Normalize the amplitude of 2nd harmonic to that of the fundamental:

Without feedback, the amplitude of 2nd harmonic to that of the fundamental:

The relative magnitude of the second harmonic has dropped by a factor of(1 + βα1)2 in the feedback system.

Gain error and nonlinearity in a feedback system

( )211

2

111

2 βααα

+= mV

ab

1

2

1

222

22/

αα

αα m

m

m

F

HD VV

VA

A==


Capacitor nonlinearity

Assuming C1 = MC2, and C2 ≈ C0(1 + α1V ), we obtain

and

since

The last two terms under the square root are usually much less than unity, we can write

210000 11 2

0 VMCVMCdVCQ inVin α

+== ∫21

000 22 2 outoutV

VCVCdVCQ out α+== ∫

( )012

021

121 2111

ininout VMVMVQQ ααα

+++−=⇒=

( ) 20

10 2

1 ininout VMMMVV α−+≈

The nonlinearity results from the voltage dependence of the capacitor.

7


Linearization techniques

Common-source stage with resistive degeneration

For a CS stage, degeneration reduces the signal swing applied between the gate and the source of the transistor, thereby making the input/output characteristic more linear.Neglecting body effect, the overall transconductance of the stage as

which for large gmRS approaches 1/RS, an input-independent value. The amount of linearity depends on gmRS rather on RS alone. Resistive degeneration presents trade-off between linearity, noise, power dissipation, and gain.

Sm

mm Rg

gG+

=1


Linearization techniques (cont’d)

Source degeneration applied to a differential pair

M3 operating in deep triode region. M3 and M4 operating in deep triode region.

8


Linearization techniques (cont’d)

Post-correction – voltage amplifier viewed as a cascade of two nonlinear stages.

Differential pair with nonlinear I/V characteristic

Diode-connected devices with nonlinear I/V characteristic

2,1

2

2,1

12121

22

−

=−=−

LWC

I

LWC

IVVVVoxn

D

oxn

DGSGSinin

µµ

4,3

4

4,3

343

22

−

=−=

LWC

I

LWC

IVVVoxnoxn

GSGSout

µµ


Circuit having input/output characteristic

( )

4,3

2,1

21

4,3

2,1

4,3

2

4,3

143

22

=⇒

−

=

−

=−=

LWL

W

A

VV

LWL

W

LWC

I

LWC

IVVV

v

inin

oxn

D

oxn

DGSGSout

µµ

a quantity independent of the bias current of the transistors.

9


Mismatch

Random mismatches due to microscopic variations in device dimensions

Reduction of length mismatch as a result of increasing the width

Mismatches lead to three significant phenomena: dc offsets, finite even-order distortion, and lower common-mode rejection.


DC offsets

Differential pair with offset measured at the output, and with its offset referred to the input.

With Vin = 0 and perfect symmetry, Vout = 0, but in the presence of mismatches, Vout ≠ 0.The circuit suffers from a dc offset equal to the observed value of Voutwhen Vin = 0.In practice, it is meaningful to specify the input-referred offset voltage, defined as the input level that forces the output voltage to go to zero. Note that |VOS,in| = | VOS,out|/Av.

10


DC offsets (cont’d)

Effect of offset in an amplifier

Accuracy limitation of an amplifier due to offset


- Calculate the offset voltage of a differential pair

Assuming both the input transistors and the load resistors suffer from mismatch.The device mismatches are incorporated as:

VTH1 = VTH, VTH2 = VTH + ∆VTH; (W/L)1 = W/L, (W/L)2 = W/L + ∆(W/L); R1 = RD, R1 = RD +∆R.

For Vout = 0, we must have ID1R1 = ID2R2, where ID1 = ID, ID2 = ID +∆ID.

Assuming ∆ID /ID and ∆(W/L)/(W/L) << 1, then

THD

D

oxn

DTH

oxn

DTH

oxn

D

GSGSinOS

V

LW

LW

II

LWCIV

LWC

IV

LWC

I

VVV

∆−

∆+

∆+−⋅=−

−+

=

−=

1

11

)/(222

2

2

21

1

1

21,

µµµ

( ) THD

D

oxn

DinOS V

LWLW

II

LWCIV ∆−

∆+

∆−⋅=

)/()/(

2/2

, µ

11


Recall that ID1R1 = ID2R2 and hence IDRD = (ID + ∆ID)(RD + ∆RD) ≈ IDRD + ID∆RD + RD∆ID. Consequently, ∆ID /ID ≈ −∆RD /RD, and

Approximately,

The dependence of VOS,in on device mismatches and bias conditions.The contribution of load resistor mismatch and transistor dimension mismatch increase with the equilibrium overdrive.The threshold voltage mismatch is directly referred to the input.

Thus, it is desirable to minimize VGS − VTH by lowering the tail current or increasing the transistor widths.Since mismatches are independent statistical variables,

where square quantities represent standard deviations.

THD

D

oxn

DinOS V

LWLW

RR

LWCIV ∆−

∆+

∆⋅=

)/()/(

)/(2

21

, µ

THD

DTHGSinOS V

LWLW

RRVVV ∆−

∆+

∆−=

)/()/(

2,

2222

2, )/(

)/(2 TH

D

DTHGSinOS V

LWLW

RRVVV ∆+

∆+

∆

−

=


Even-order distortion

Effect of mismatch on second-order distortion

If x1(t ) = Acosωt, then the second harmonic has an amplitude equal to (α2 −β2)A2 /2, i.e., proportional to the mismatch between the second-order coefficients of the input/output characteristic.

In circuits dissipating a high power, thermal gradients across the chip may create asymmetries. For example, if one transistor of the differential pair is closer to a high-power output stage than the other transistor, then mismatches arise between the threshold voltages and the mobilities of the two transistors.

The differential output is given byy1 − y2 = (α1x1 − β1x2) + (α2x1

2 − β2x22) + (α3x1

3 − β3x23)

which, for x1 = −x2, reduces toy1 − y2 = (α1 + β1)x1 + (α2 − β2)x1

2 + (α3 + β3)x13

12


Lower common-mode rejection

Effect of CM noise in the presence of resistor mismatch

Mismatch between M1 and M2

( ) 121 ++∆

−=−SSmm

DmDMCM Rgg

RgA

ACM−DM : CM to DM conversion∆gm = gm1 − gm2

( ) ( )[ ]SSmmmmm

mm Rggggg

ggCMRR 2121

21 1 ++∆+

=


Offset cancellation techniques

Output offset storage

When all of the node voltages are settled and AvVOS is stored across C1 and C2, a zero differential input results in a zero difference between VX and VY. After S1 and S2amplifying only changes in differential input voltage.

Proper setting of the common-mode level during offset cancellation:

If Av is large, AvVOS may saturate the amplifier output.

Control of amplification and offset cancellation modes by a clock:

13


Offset cancellation techniques (cont’d)

Input offset storage

The approach incorporates two series capacitors at the input and places the amplifier in a unity-gain negative-feedback loop during offset cancellation.

Vout =VXY and (Vout − VOS)(−Av) = Vout

The circuit reproduces the amplifier’s offset at node X and Y, storing the result on C1 and C2.For a zero differential input, the differential output is equal to VOS. Therefore, the input-referred offset voltage of the overall circuit (after S3,4 turn off) equals to VOS/Av. In reality, however, when S3,4 turn off, their charge injection mismatch may saturate the amplifier if Av is very large.

OSOSv

vout VV

AAV ≈+

=1


The general drawback of input and output storage techniques is that they introduce capacitors in the signal path in op amps and feedback systems. The bottom-plate parasitic of the capacitors may reduce the magnitude of the poles in the circuits, thereby degrading the phase margin. Even in open-loop amplifiers, this parasitic may limit the settling speed, intensifying the speed-power trade-off.

14



Addition of an auxiliary storage to remove the offset of an amplifier

To resolve the above issues, the offset cancellation scheme can isolate the signal path from the offset storage capacitors through the use of an auxiliaryamplifier.Aaux amplifies the differential voltage V1 stored across C1 and C2 and subtracts the result from the output of A1. If VOS1A1 = V1Aaux, then for Vin = 0, Vout =0, and the circuit is free from offset. The key point here is that C1and C2 do not appear in the signal path.



Auxiliary amplifier placed in a feedback loop during offset cancellation

Operation: Suppose that first only S1,2 are on, yielding Vout = VOS1A1A2. Now, assume S3,4 turn on, placing A2 and Aaux in a negative feedback loop. Then, Vout = VOS1A1A2 /(A2Aaux) = VOS1A1 /Aaux. Stored across C1 and C2, the value V1 = VOS1A1.Drawbacks:• Two voltage gain stages in the signal path may not be desirable in a high-

speed op amp.• Addition of the output voltages of A1 and A2 is quite difficult.

15



Improved auxiliary amplifier placed in a feedback loop during offset cancellation

Realization

Gm stage is simply a differential pair (OTA) and R stage represents a transimpedance amplifier.


Analysis

[Gm1VOS1 − Gm2(Vout − VOS2)]R = Vout

This value is stored on C1 and C2 after S3,4 turn off. The offset voltage referred to the main input is therefore given by

, assume Gm2R >> 1.

If Gm2R and Gm1R are large, then VOS,tot is very small.Upon turning off, S3,4 may inject slightly unequal charges onto C1 and C2, respectively, creating an error voltage that is not corrected because the feedback loop is open.

RGRVGRVGV

m

OSmOSmout

2

2211

1++

=

RGV

RGV

RGV

GG

RGV

RGVV

m

OS

m

OS

m

OS

m

m

m

OS

m

outtotOS

1

2

2

1

2

2

1

2

2

1

1, 11

+≈+

++

==

16


Reduction of noise by offset cancellation

The offset of a differential amplifier can be viewed as a noise component havinga very low frequency. We therefore expect that periodic offset cancellation canpotentially reduce the (low-frequency) noise of the circuit as well.

Front end of a sampler

The noise of A1 directly corrupts Vin. The 1/f noise of A1 proves especially problematic if the signal spectrum extends from zero to only a few megahertz, because the 1/f noise corner frequency is typically around 500kHz to 1MHz.


Reduction of noise by offset cancellation (cont’d)

Front end of a sampler with offset cancellation applied to the first stage

17


Sequence of operations in the sampler: the amplifier undergoes offset cancellation before every sampling operation.

From t1 to t2, only high-frequency noise components of A1 change VXY significantly. In other words, offset cancellation suppresses noise frequencies below roughly 1/∆t. (∆t = t2 − t1)

The input is disable and the offset of A1 is stored on C1 and C2.

The input is enabled and amplified by A1and A2 and stored on C3 and C4.

The sampling switches are turned off.


Reduction of noise by offset cancellation (cont’d)

Variation of 1-MHz and 10-MHz noise components in a time interval of 10 ns.

For a sinusoid of amplitude A and frequency f, the maximum slew rate is equal to 2π fA and hence the maximum variation in ∆t seconds is 2π fA∆t. Normalizing this value to the amplitude, we obtain the change for 1-MHz and 10-MHz components as ∆V1/A = 6.3% and ∆V1/A = 63%, respectively.

Noise frequencies below a few megahertz do not have sufficient time to change if the sampling occurs only 10 ns after the end of offset cancellation.

18


Alternative definition of CMRR

In fully differential circuits, the finite output impedance of the tail current source and asymmetries limit the common-mode rejection.Common-mode rejection can be viewed as the change in the output offset divided by the change in the input CM level.

Noting that ∆VOS,out /ADM is in fact the input-referred offset voltage, we have

inCM

outOSDMCM V

VA

,

,

∆∆

=−

DM

outCM

inCM

DMCM

DM

AVV

AACMRR

,

,

∆∆

==−

inOS

inCM

VV

CMRR,

,

∆∆

=


PMOS differential pair:

In Fig.(a), body effect is eliminated and the threshold voltages of M1 and M2

are independent of the input CM level.

In Fig.(b), M1 and M2 experience body effect and, if they suffer from mismatches in their body effect coefficients, then the difference between VTH1 and VTH2, i.e., the input offset voltage, varies with the input CM level, degrading the common-mode rejection.

Without body effect With body effect

Documents

Nonlinearity and Mismatch - 國立中興大學cc.ee.nchu.edu.tw/~aiclab/teaching/AIC/lect13.pdf · Nonlinearity and Mismatch 類比電路設計(3349) - 2004 Analog-Circuit Design