Nonvolatile Memory With Extremely Low-Leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistor

2258 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 9, SEPTEMBER 2012

Nonvolatile Memory With Extremely Low-LeakageIndium-Gallium-Zinc-Oxide Thin-Film TransistorHiroki Inoue, Takanori Matsuzaki, Shuhei Nagatsuka, Yutaka Okazaki, Toshinari Sasaki, Kousei Noda,Daisuke Matsubayashi, Takahiko Ishizu, Tatsuya Onuki, Atsuo Isobe, Yutaka Shionoiri, Kiyoshi Kato,

Takashi Okuda, Jun Koyama, and Shunpei Yamazaki, Life Fellow, IEEE

Abstract—Emerging nonvolatile memory with an oxide–semi-conductor-based thin-film transistor (TFT) using indium-gal-lium-zinc-oxide (IGZO) was developed. The memory is called non-volatile oxide–semiconductor random access memory (NOSRAM).The memory cell of the NOSRAM (NOSRAM cell) consists ofan IGZO TFT for data writing, a normal Si-based p-channelmetal-oxide-semiconductor (PMOS) for data reading, and a cellcapacitor for storing charge and controlling the PMOS gatevoltage. The IGZO TFT and the cell capacitor are formed over thePMOS. Owing to extremely low-leakage-current characteristicsof the IGZO TFT, the charge stored in the 2-fF cell capacitoris maintained for a long time. This long data retention realizedinnovative nonvolatile memory. The NOSRAM cell fabricatedwith the 0.8- m process technology demonstrated an ON/OFF ratioof 10 and an endurance over 10 write cycles. In addition,NOSRAM with a memory capacity of 1 Mb was fabricated; thecell size was 12.32 m and the cell array size was 13.5 mm .The 1-Mb NOSRAM achieved basic operation at 4.5 V or less,write operation at 150 ns/page, read distribution of data “1” with

0.10 V, and a data retention over 60 days at 85 C.

Index Terms—Capacitor, complementary metal-oxide-semicon-ductor (CMOS), indium-gallium-zinc-oxide (IGZO), nonvolatilememory, oxide semiconductor, p-channel metal-oxide-semicon-ductor (PMOS), random access memory, thin-film transistor(TFT).

I. INTRODUCTION

N ONVOLATILE memories are used in a variety of appli-cations ranging from instruction codes in system LSI to

data storage, bringing great convenience to human life. Fur-ther improvement in various aspects of performances such aslow-power operation and logic process compatibility gives greatbenefits to customers.Emerging nonvolatile memories such as phase-change

random access memory (PRAM) [1], [2] and resistive randomaccess memory (RRAM) [3], [4] have been actively developedin recent years and have advantages in terms of low-voltageoperation and high-speed data writing and reading. However,

Manuscript received November 03, 2011; revised April 18, 2012; acceptedApril 19, 2012. Date of publication July 06, 2012; date of current version August21, 2012. This paper was approved by Associate Editor Peter Gillingham.H. Inoue is with the TFT Circuit Design Division, Semiconductor En-

ergy Laboratory Company, Ltd., Kanagawa 243-0036, Japan (e-mail:[email protected]).T. Matsuzaki, S. Nagatsuka, Y. Okazaki, T. Sasaki, K. Noda, D. Matsu-

bayashi, T. Ishizu, T. Onuki, A. Isobe, Y. Shionoiri, K. Kato, T. Okuda, J.Koyama, and S. Yamazaki are with the Semiconductor Energy Laboratory Com-pany, Ltd., Kanagawa 243-0036, Japan.Digital Object Identifier 10.1109/JSSC.2012.2198969

these memories have limited endurance and a small ON/OFFratio of approximately or less.Emerging nonvolatile memory developed in this work can

solve the above-mentioned problems and is called nonvolatileoxide semiconductor random access memory (NOSRAM) [5],[6]. The NOSRAM is nonvolatile memory utilizing the fact thatan oxide-semiconductor-based thin-film transistor (TFT) [7],[8] using indium-gallium-zinc-oxide (IGZO) [9], [10] has ex-tremely low leakage current [11], [12]. The memory cell of theNOSRAM (NOSRAM cell) consists of an IGZO TFT, a normalSi-based p-channel metal-oxide-semiconductor (PMOS), and acell capacitor. Peripheral circuits are constituted by a normalcomplementary MOS (CMOS) including a Si-based n-channelMOS (NMOS) and the PMOS.This paper describes the structure and operation principle of

the NOSRAM cell and the characteristics of 1-Mb NOSRAM.Section II explains the IGZO TFT leakage current character-istics and the structure, operation, and characteristics of theNOSRAM cell. Section III shows the driving method of the1-Mb NOSRAM. Section IV presents the demonstration oflow-voltage operation and high-speed write operation of the1-Mb NOSRAM that is fabricated using the IGZO TFT stackedover a 0.8- m standard CMOS.

II. NOSRAM CELL

A. IGZO TFT Leakage Current Characteristics

A TFT made of IGZO has electron mobility higher than thatof a TFTmade of amorphous Si and can be formed by a thin-filmprocess [7], [8]. The IGZO TFT has extremely low leakage-cur-rent characteristics. The procedure for measuring extremely lowleakage current has been reported in several papers [11], [12],and the leakage current was measured with a similar procedure.Fig. 1 shows the circuit configuration for measuring leakage cur-rent. The rate of change of the voltage writteninto the parasitic capacitor through the writing IGZO TFT ismeasured by using the source follower, and the leakage current

of the IGZO TFT which is a device under test (DUT) iscalculated by

(1)

The channel width of the DUT is made to be as largeas 10 000 m, so that the rate of change of the voltage

due to charge loss depends on the DUT leakagecurrent . As a result, is determined bythe DUT leakage current . As shown in Fig. 2, the

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INOUE et al.: NONVOLATILE MEMORY WITH EXTREMELY LOW-LEAKAGE IGZO TFT 2259

Fig. 1. Circuit configuration for measuring leakage current.

Fig. 2. Arrhenius plot of IGZO TFT leakage current.

IGZO TFT leakage current is found to be 50 yA m at85 C, which is extremely low. Note that y (yocto) is .Further, from the – characteristics measured by a semi-conductor parameter analyzer, the NMOS leakage current is0.3 pA m at 85 C under the following measurement condi-tions: channel width/channel length m mand 1V/3 V. Accordingly, the IGZO TFT leakagecurrent is estimated to be 1/1 000 000 000 lower than that ofa Si-based MOS. This extremely low leakage current is veryeffective in holding charge for a long time.

B. Strcuture and Operation

A circuit diagram and a cross-sectional view of the NOSRAMcell are shown in Fig. 3(a) and (b), respectively. As shownin Fig. 3(a), the NOSRAM cell consists of an IGZO TFT fordata writing, a PMOS for data reading, and a cell capacitorfor storing charge and controlling the PMOS gate voltage.The NOSRAM cell is fabricated using the 0.8- m processtechnology. The device features are as follows: of theIGZO TFT is 0.8 m 0.8 m, the capacitance of the cellcapacitor is 2 fF, and of the PMOS is 0.8 m 0.8 m.Note that the reason for using the PMOS is that the NOSRAMcell can be driven with positive voltage. The operation of theNOSRAM cell is described in detail in Section III. isa write word line, is a write-and-read word line, BL is abit line, and SL is a source line. As shown in the cross-sectionalview in Fig. 3(b), in the NOSRAM cell, the IGZO TFT and thecell capacitor are formed over the PMOS. The structural feature

Fig. 3. NOSRAM cell structure. (a) Circuit diagram. (b) Cross-sectional view.

of the NOSRAM cell is that the source/drain (S/D) electrodesof the IGZO TFT, the cell capacitor electrode, and the PMOSgate are electrically connected without a via hole. Specifically,the S/D electrodes of the IGZO TFT and the cell capacitorelectrode are formed using the same metal layer, and the metallayer is positioned above the PMOS gate, thereby connectingthese electrodes.In the write operation, is “HIGH” to turn on the

IGZO TFT, and charge is stored in the cell capacitor throughthe IGZO TFT from BL. When is “LOW” and thusthe IGZO TFT is turned off, the charge is isolated by the cellcapacitor insulator, the PMOS gate insulator, and the turned-offIGZO TFT. Since the IGZO TFT leakage current is extremelylow, stored charge is expected to be retained for a long time. Inthe read operation, the PMOS threshold voltage is changed bythe amount of charge stored in the cell capacitor whenis regarded as the gate electrode of the PMOS. Data are distin-guished whether the PMOS is turned on or off depending on thethreshold voltage. The retention time is determined by the timewhen a certain amount of charge is lost from the cell capacitorand can be obtained by

(2)

where is a difference between a write voltage and a voltagecausing data misreading, is the IGZO TFT leakage cur-rent, is the leakage current of the capacitor insulator, andis the PMOS gate leakage current, and is defined as 2 V,because data misreading occurs when a written 3-V voltage isdecreased to 1 V. The reason for 2 V is described in de-tail in Section III. As shown in Fig. 2, the leakage currentof the IGZO TFT with 0.8 m is 40 yA at 85 C. Further,and were measured while the DUT in Fig. 1 was replaced

with the capacitor and a MOS capacitor including a gate insu-lator which is the same as that in the PMOS. As a result, the


Fig. 4. characteristics of data “1” and data “0” in NOSRAM cell.

Fig. 5. Endurance of NOSRAM cell.

leakage current of the 2-fF capacitor insulator was 20 yA at85 C, and the PMOS m 0.8 m gate leakagecurrent was 10 yA at 85 C. The insulators of the IGZO TFTand the cell capacitor are 30-nm-thick silicon oxides, and thePMOS gate insulator is a 20-nm-thick silicon oxide. From (2),the retention time is estimated at 1.8 years at 85 C. The resultshows that the NOSRAM can be expected to operate as non-volatile memory, but the retention time needs to be further ex-tended.

C. Characteristics

The characteristics of the NOSRAM cell areshown in Fig. 4. In order to write data, 0 V was applied toand 4.5 Vwas applied to to turn on the IGZOTFT, anddata was input from BL. Then, 1 V was applied toto turn off the IGZO TFT. As for data, 3 V was data “1” and0 V was data “0.” The threshold voltage window widthbetween data “1” and data “0” is 3 V from Fig. 4. The ON/OFFratio at 0 V is as large as approximately . Thismeans that data misreading due to noise can be avoided and theNOSRAM is superior to PRAM and RRAM [1]–[4].The results of measuring endurance of the NOSRAM cell are

shown in Fig. 5. The measurement conditions are the same asthose used for measuring the characteristics shownin Fig. 4. Fig. 5 shows that the endurance was over . Notethat is calculated with the square root extrapolation method.

Fig. 6. Block diagram of 1-Mb NOSRAM.

III. 1-MB NOSRAM SCHEMA

Here, we describe themethod for driving the 1-MbNOSRAMin the write operation and read operation. A block diagram ofthe 1-Mb NOSRAM is shown in Fig. 6. The 1-Mb NOSRAMconsists of a 1-Mb NOSRAM cell array, 1024 row drivers, 1024page buffers, and 128 SL drivers. The 1-Mb NOSRAM cellarray consists of 1024 bit 1024 pages. The page size is 1024bit. One SL is provided for every eight columns of NOSRAMcells. The 1024 BLs are connected to the respective 1024 pagebuffers.The power supply voltage VDD is 3 V. The voltage corre-

sponding to the data “1” and the voltage corresponding to thedata “0” for writing are represented byVdata“1” and Vdata“0”,respectively (Vdata“1” is 3 V and Vdata“0” is 0 V). The volt-ages of three signal lines , , and SL are as fol-lows. The signal line is explained first. The “HIGH”voltage VH of is 4.5 V. A 4.5 V VH is adopted toavoid degradation of 3 V write due to drop when goingthrough the IGZO TFT. The “LOW” voltage of is VL.The voltage VL is 1 V so that data can be retained. This is be-cause a depletion mode of the IGZO TFT cannot be avoidedunder present circumstances. Next, the signal line is ex-plained. The “HIGH” voltage of is VH, and the “LOW”voltage is 0 V.When is VH, the PMOS gate voltage in theNOSRAM cell is boosted to Vdata“1” by capacitive cou-pling. Since the BL and SL voltages are VDD or lower, PMOS

in the NOSRAM cell is higher than PMOS , that is, thePMOS is turned off. The NOSRAM cell including the PMOScan be unselected by application of the positive voltage (VH) to

. Then, the signal line SL is explained. The SL voltage isa read voltage VR during the read operation. The SL voltage onstandby and during the write operation is 0 V. In order to ex-tend the time for retaining data “1,” VR is 1.5 V, which is lowerthan VDD (3 V). This is because in (2) is obtained fromVdata“1” VR and is 2 V when is 0.5 V.The write operation is performed as follows. The BL voltage

changes toVdata“1” orVdata“0”, the voltage of write data, andthen the selected voltage changes from VH to 0 V and theselected voltage changes from VL to VH. The IGZOTFT is turned on, and the cell capacitor is charged with the BL


Fig. 7. Simplified circuit diagram of page buffer.

Fig. 8. Die photograph of 1-Mb NOSRAM.

TABLE ISUMMARY OF 1-MB NOSRAM FEATURES

voltage. The selected is connected to gate electrodesof 1024 IGZO TFTs, which means the write operation can beperformed on 1024 NOSRAM cells.The read operation is conducted as follows. The SL voltage

changes from 0 V to VR, and the selected voltagechanges from VH to 0 V. In the case where data “0” has beenwritten, Vdata“0” VR is satisfied and the PMOS inthe NOSRAM cell is turned on, so that a current flows fromSL to BL. In other words, the BL voltage increases from 0 Vto VR. In the case where data “1” has been written,Vdata“1” VR is satisfied, and the PMOS in the NOSRAMcell is turned off and no current flows from SL to BL. Thatis, the BL voltage does not change from 0 V. The page buffer

Fig. 9. Shmoo plot of 1-Mb NOSRAM.

Fig. 10. Relation between write time of 1-bit NOSRAM cell and .

Fig. 11. Write characteristics of 1-Mb NOSRAM (measured waveform of BL).

latches data after the BL voltage is changed, whereby the datais read. Since is connected to cell capacitors in 1024NOSRAM cells, the read operation can be performed on the1024 NOSRAM cells.The 1024-bit data are temporarily stored in the page buffers

to be read and written from/to the NOSRAM cells. A simpli-fied circuit diagram of the page buffer is shown in Fig. 7. Thepage buffer has two functions: one is to store 1024 bit of writedata and then change the BL voltage to the voltage of the writedata; and the other is to latch read data and then store 1024 bitof the read data. Input data (IN) as write data is stored in thepage buffer when a page buffer writing control signal WEB is“HIGH.” In the write operation for the NOSRAM cell, the BL


Fig. 12. Operation waveforms of 1-Mb NOSRAM. (a) Write operation. (b) Read operation.

voltage changes to the voltage of write data when a NOSRAMcell writing control signal PWEB is “HIGH.” At the begin-ning of a latch operation for reading data from the NOSRAMcell, a latch control signal LATB changes to “HIGH” so thatthe inverter does not operate. Next, the selected voltagechanges to 0 V and the BL voltage changes, and after that, LATBchanges to “LOW” so that the inverter operates. The read data islatched by and stored in the page buffer. The reference voltagefor read data is an inversion voltage (VR/2) of the inverter inthe page buffer.

IV. MEASUREMENT RESULTS OF 1-MB NOSRAM

A die photograph of the 1-Mb NOSRAM is shown in Fig. 8.The 1-Mb NOSRAM was fabricated by using the 0.8- m stan-dard CMOS process and the IGZO TFT process. Peripheral cir-cuits such as row decoders and page buffers were composed of aCMOS. The cell size is 12.32 m and the cell array size is 13.5mm . The specifications and measurement results of the 1-MbNOSRAM are summarized in Table I.A Shmoo plot with the write time as the axis and VDD/VH

as the axis is shown in Fig. 9. If the operating voltages VDDand VH are lowered, a current flowing from the page buffer toBL and a current flowing to the IGZO TFT in the NOSRAMcell are decreased and thus the write time is extended. A writespeed of 150 ns/page is obtained at operating voltages VDD of3 V and VH of 4.5 V. Note that a current of approximately 3mA was measured as the current necessary for 1 page (1024bit) write.The write speed of the 1-Mb NOSRAM is 150 ns/page. The

1-Mb NOSRAM is slightly inferior in speed to PRAM andRRAM, the speeds of which is less than 100 ns [1]–[4]. Thewrite time is determined by the time for switching the IGZOTFT, the time for charging and discharging the cell capacitor,the time for charging and discharging BL, and the time fordriving the peripheral circuits. First, the time for switching theIGZO TFT and the time for charging and discharging the cellcapacitor are considered. Fig. 10 shows the relation between

the write time of a 1-bit NOSRAM cell and the window.The write operation is performed by applying a voltage pulseof 4.5 V to the gate electrode of the IGZO TFT. The pulseduration is the write time. Fig. 10 shows that data are correctlywritten into the NOSRAM cell in a write time of 10 ns. Next,the time for charging and discharging BL is explained. Fig. 11shows the write characteristics of the 1-Mb NOSRAM. FromFig. 11, the measured waveform of BL in the write operationrises approximately 80% in 40 ns after the start of BL charging;that is, BL can operate at high speed 3 V/4.5 V .In other words, the 1-Mb NOSRAM can write data in less than100 ns. These results indicate that the 1-Mb NOSRAM canwrite data at high speed because of improvement in peripheralcircuits.The measurement result of the operation waveforms at a write

time of 150 ns is shown in Fig. 12(a). Each signal line valueis obtained by microprobing. The write time refers to a periodfrom rising to falling of the signal for PWEB. It is confirmedthat the BL voltage increases when data “1” is written, whereasthe BL voltage is not changed when data “0” is written. Themeasurement result of the operation waveforms at a read timeof 900 ns is shown in Fig. 12(b). The read time refers to a periodfrom rising to falling of the signal for LATB in the page buffer.It is confirmed that the BL voltage is not changed when data “1”is read, whereas the BL voltage increases when data “0” is read.It is thus verified that the basic operation of the experimentalchip is successful.Since the write voltage can be directly applied to the cell ca-

pacitor according to the operating principle of the NOSRAM,the 1-Mb NOSRAM has a very small distribution with0.10 V ( : standard deviation) with 2.10 V as shownin the read distribution of data “1” in Fig. 13. Note that thenumber of bits observed below 2.10 V VR corresponds to a de-fect caused by the fact that the pattern of memory cells laid outat the edge of the memory cell array is not a designed shape.The defect is due to the difference in the pattern density betweenmemory cells at the edge and memory cells in the middle of the


Fig. 13. Read distribution of data “1” of 1-Mb NOSRAM.

Fig. 14. Data retention of 1-Mb NOSRAM.

memory cell array and therefore can be removed by using thedummy pattern technique.Data retention at 85 C of 1-Mb NOSRAM where data “1”

is written into all of the NOSRAM cells is shown in Fig. 14.in the NOSRAM cell is VL. Data “1” is held even

after 60 days, which proves that the amount of charge held inthe cell capacitor of the NOSRAM cell is hardly changed. Theresults verify the feature of the NOSRAM utilizing extremelylow leakage current of the IGZO TFT.

V. CONCLUSION

The 1-Mb NOSRAM was fabricated with the 0.8- mprocess technology by forming an IGZO TFT with extremelylow leakage-current characteristics and a cell capacitor overa PMOS. The NOSRAM cell achieved an ON/OFF ratio of, and an endurance over write cycles. The 1-Mb

NOSRAM performed the basic operation at operating voltages3 V/4.5 V, and achieved high-speed writing of

150 ns/page, read distribution of data “1” with 0.10 V,

and a data retention over 60 days at 85 C. The NOSRAMhas potential as nonvolatile memory that surpasses othernonvolatile memories under development in terms of ON/OFFratio and endurance. The future challenges are to verify thescalability of the IGZO TFT leakage current and to examinethe retention of scaled NOSRAM.

ACKNOWLEDGMENT

The authors would like to thank Prof. T. Asano of KyushuUniversity for his comment and advice on this paper writing.

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Hiroki Inoue received the Associate degree in elec-trical engineering from Ariake National College ofTechnology, Fukuoka, Japan, in 2004.He joined Semiconductor Energy Laboratory Co.,

Ltd., Atsugi, Japan, in 2004, where he has beenworking on the development of LSI circuits andmemories.


Takanori Matsuzaki received the B.E. and M.E. de-grees in electrical engineering from TokyoUniversityof Science, Tokyo, Japan, in 2001 and 2003, respec-tively.He joined Semiconductor Energy Laboratory

Co., Ltd, Atsugi, Japan, in 2003, where he has beenworking on the development of LSI circuits andmemories.

Shuhei Nagatsuka received the B.E. degree in elec-tronic engineering from The University of Electro-Communications, Tokyo, Japan, in 2004.He joined Semiconductor Energy Laboratory Co.,


Yutaka Okazaki received the B.S. degree in scienceand M.S. degree in science and engineering fromNagoya Institute of Technology, Nagoya, Japan, in2001 and 2003, respectively.He joined Semiconductor Energy Laboratory Co.,

Ltd., Atsugi, Japan, in 2003, where he has been en-gaged in the development of process technology ofSi-based transistors and oxide–semiconductor-basedTFTs.

Toshinari Sasaki received the B.S. andM.S. degreesfrom Waseda University, Tokyo, Japan, in 2003 and2005, respectively.He joined Semiconductor Energy Laboratory Co.,

Ltd, Atsugi, Japan in 2005, where he has been en-gaged in the development of process technology ofoxide–semiconductor-based TFTs.

Kousei Noda received the B.E. and M.E. degreesfrom Kyushu Institute of Technology, Kitakyushu,Japan, in 2003 and 2005, respectively.He joined Semiconductor Energy Laboratory Co.,

Ltd., Atsugi, Japan, in 2005, where he has beenworking on the development of process technologyof Si-based transistors.

Daisuke Matsubayashi received the B.S. degreefrom Keio University, Kanagawa, Japan, in 2005,and the M.S. and Ph.D. degrees from the Universityof Tokyo, Tokyo, Japan, in 2007 and 2010, respec-tively, all in physics.He joined Semiconductor Energy Laboratory Co.,

Ltd., Atsugi, Japan, in 2010, where he has beenengaged in the development of LSI circuits usingoxide–semiconductor-based TFTs.

Takahiko Ishizu received the B.E. and M.E. degreesin engineering from Osaka Prefecture University,Osaka, Japan, in 2008 and 2010, respectively.He joined Semiconductor Energy Laboratory

Co., Ltd., Atsugi, Japan in 2010, where he has beenworking on the development of LSI circuits andmemories.

Tatsuya Onuki received the B.S. and M.S. degreesfrom University of Tsukuba, Tsukuba, Japan, in 2008and 2010, respectively.He joined Semiconductor Energy Laboratory Co.,


Atsuo Isobe received the B.E. andM.E. degrees fromNagoya Institute of Technology, Nagoya, Japan, in1996 and 1998, respectively.He joined Semiconductor Energy Laboratory Co.,

Ltd., Atsugi, Japan, in 1998, where he has been en-gaged in the development of process technology ofSi-based transistors and oxide–semiconductor-basedTFTs.

Yutaka Shionoiri received the B.E. and M.E. de-grees from Chiba University, Chiba, Japan, in 1994and 1996, respectively.He joined Semiconductor Energy Laboratory Co.,


Kiyoshi Kato received the B.S., M.S., and Ph.D.degrees in physics from the University of Tokyo,Tokyo, Japan, in 1994, 1996, and 1999, respectively.He joined Semiconductor Energy Laboratory

Co., Ltd, Atsugi, Japan, in 1999, where he has beenworking on the development of LSI circuits usingTFTs.

Takashi Okuda received the B.S. and M.S. degreesin instrumentation engineering from Keio University,Kanagawa, Japan.He was engaged in the development of various

large-scale MOS memories from 1975 to 2008with NEC Corporation and mainly directed thedevelopment of prototype 64 Mb-4 Gb DRAMs. Heis now a technical adviser to Semiconductor EnergyLaboratory Co., Ltd., Atsugi, Japan.


Jun Koyama received the B.S. degree in physicsfrom Rikkyo University, Ikebukuro, Japan, in 1980.He joined Semiconductor Energy Laboratory Co.,

Ltd., Atsugi, Japan, in 1992. Since then, he has beenworking on the development of thin-film transistorsand circuits.

Shunpei Yamazaki (LF’11) received the B.E., M.E.,Ph.D., and honorary degrees from Doshisha Univer-sity, Japan, in 1965, 1967, 1971, and 2011 respec-tively.He is the Founder and President of Semiconductor

Energy Laboratory Co., Ltd., Atsugi, Japan.Dr. Yamazaki is a Life Fellow of the IEEE, a

member of the Japan Society of Applied Physics, anda foreign member of the Royal Swedish Academy ofEngineering Sciences. He was awarded Medal withPurple Ribbon by the Japanese Prime Minister’s

Office for the innovation of MOS LSI element technology in 1997 and wasthe winner of the Okochi Memorial Technology Prize in 2010. He is a holderof Guinness World Record under the category of “most patents held by anindividual” for the total of 6314 patents as of March 2011.

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Nonvolatile Memory With Extremely Low-Leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistor