Modeling, Design, Fabrication and Characterization of First Large 2.5D Glass Interposer as a

Superior Alternative to Silicon and Organic Interposers at 50 micron bump pitch

Brett Sawyer, Hao Lu, Yuya Suzuki

†, Yutaka Takagi

‡, Makoto Kobayashi

±, Vanessa Smet, Taiji Sakai

*, Venky Sundaram

and Rao Tummala

3D Systems Packaging Research Center, Georgia Institute of Technology,

813 Ferst Dr. N.W., Atlanta, GA 30332. † Zeon Corporation, Kawasaki, Kanagawa, Japan

‡ NGK Spark plug Co., Ltd., Komaki, Aichi, Japan * Fujitsu Laboratories Ltd., Atsugi, Kanagawa, Japan

± Namics Corporation, Niigata, Japan

Email: bsawyer@gatech.edu

Abstract

This paper describes the first design and fabrication of a

large 2.5D glass interposer with 50 µm pitch chip-level

interconnections made of 6 layers of 3 µm re-distribution

(RDL) wiring. Many applications including high-performance

networking and cloud computing data centers require ultra-

high-bandwidth of the magnitude of 512 GB/s. Silicon-based

2.5D interposers are the only approaches being pursued by the

industry to meet this need, enabled by sub-micron BEOL

wiring in the wafer fabs. Such interposers, however, are too

expensive for most applications. Glass interposers are superior

to silicon interposers due to their high dimensional stability,

low loss tangent, and large panel processing ultimately

leading to lower cost. This paper presents the design,

fabrication and electrical characterization, leading to the first

fabrication of 2.5D glass interposers with 50 µm I/O pitch

with 3 µm lines. Double-sided panel processing utilizing thin,

low-loss dryfilm polymer dielectrics and SAP copper plating,

with differential spray etching techniques, was used to

fabricate 3 m wide transmission lines on 25mm x 30mm

glass interposers processed on a 300 m thick 150mm x

150mm glass panels. A six-metal layer test vehicle with two

daisy chain, 10mm x 10mm test chips at 100 µm spacing, was

fabricated and assembled by thermo-compression bonding of

Cu microbumps and SnAg solder caps. Ultra-fine 3 µm

escape routing was demonstrated on a two-metal layer test

vehicle. High frequency characterization of 3 µm lines

showed low loss of 0.12 dB/mm at 2 GHz.

Introduction

System bandwidth for high-performance applications are

expected to require 512 GB/s to 1 TB/s in the near future. The

only way to meet this need is by ultra-fine pitch

interconnections between logic and memory devices either in

3D with vertical TSV interconnections or by horizontal 2.5D

interconnections, as shown in Fig. 1a and 1b. The industry has

also been aggressively developing through silicon via (TSV)

technology for high-bandwidth memory (HBM) [1] to support

high channel density. To achieve both, the industry began to

pursue back-end-of-line (BEOL) silicon wafers in both 2.5D

and 3D silicon interposers [2, 3] capable of sub-micron wiring

dimensions. However, electrical loss associated with silicon is

a limiting factor. High permittivity and high loss tangent of

silicon limit silicon interposer technology to single-sided

signal routing with short, wide I/O interconnections.

Furthermore, silicon interposers are limited by high cost,

resulting from small number of interposers from each 200 or

300 mm wafers. Low-TCE and coreless organic substrates

have improved electrical performance [4], but are limited in

pitch due to their dimensional instability affecting layer-to-

layer via registration; in body size, and thinness due to high

warpage during substrate fabrication and assembly.

(a.)

(b.)

Figure 1. High bandwidth (a.) 3D and (b) 2.5D package

architectures.

Glass interposers have been demonstrated with superior

electrical properties and with 5um wiring lines [5]. This paper

goes beyond the prior work in glass to fabricate the first 2.5D

glass interposer in large body size with 3 µm RDL wiring at

50 µm I/O pitch, as shown in Figure 2. The main

contributions of this work include: (a) the first analysis of

double-sided RDL signal routing for wide I/O applications,

(b) 3 µm RDL routing demonstration on glass using low cost,

panel-based fabrication processes, (c) simultaneous thermo-

compression bonding (TCB) of chips with side-by-side

assembly processes, and (d) characterization of 3 µm width

transmission line structures up to 5 mm signal length on glass.

Figure 2. 2.5D glass interposer cross section with 50 um I/O

Pitch.

Interposer

PCB

Logic

Stacked Memory

Fine Pitch TSV

Die Stacked Memory

Interposer

PCB

Fine L/S RDL

Non-Performance Critical Signal Line

High Performance ASICHBM

Package Substrate

20-50 μm FLI pitch

10 μm/50 μm μvia diameter/pitch

3-5 μm L/S

≤ 100 μm

Double Sided Signal Routing

Glass Interposer (≥ 25 mm x ≥ 30 mm)

> 2500 I/O

100 μm

978-1-4799-2407-3/14/$31.00 ©2014 IEEE 742 2014 Electronic Components & Technology Conference

The second section of the paper describes the electrical

modeling and design of re-distribution layers (RDL) which

includes an investigation of escape routing capacity and signal

integrity of high density die-to-die interconnections. The third

section discusses the details of a 2.5D glass interposer test

vehicle designed to study the substrate fabrication process and

assembly. The fourth section presents the details of the glass

interposer fabrication and multiple-chip assembly processes.

Such a test vehicle demonstrates 3 m RDL wiring as well as

side-by-side die chip assembly. The final section presents

high frequency characterization, performed on 3 m CPW

transmission line structures, demonstrating the superior

electrical performance of glass over silicon and organic

interposers.

Design and Modeling

High-performance applications require interposers and

packages that can support a wide, high-density, and high

aggregate bandwidth data bus (signal speeds up to 1 Gbps).

The first step in the design of a 2.5D glass interposer was the

modeling and analysis of a wide I/O channel that uses double-

sided signal routing, to accurately predict the transmission

line insertion loss and line-to-line coupling noise. The

objective was to establish a set of design rule targets for RDL

and chip-level interconnections in 2.5D glass interposers.

High-density Die-to-Die Routing on Glass

An initial set of design rules was assumed as shown in

Table 1, based on previous processing experience with

through vias (TPV) and multi-layer, double-sided RDL on

glass interposers. The routing layer design was based on, but

not limited to a 2.5D interposer with side-by-side HBM and

logic ICs (see Figure 2)

Table 1. Initial Design Rule Targets for 2.5D glass

interposers.

Design Parameter Target

Minimum L/S 3/3 μm

μ-via pad/size/pitch 16/10/50 μm

TPV pad1/size/pitch 50/30/50 μm

RDL Stack-up2 3/0/3

Bump pitch/die spacing 20-50 μm/ ≤ 100 μm 140 μm bottom pad size 2ultra-fine feature size on all metal layers

A routing study was performed based on these design

rules. The three goals for this routing study were to (a) reduce

layer count (and consequently cost), (b) use GSSG and GS

transmission structures for better signal integrity, and (c)

demonstrate escape routing for up to 24 signal rows on a die

with 96/55 m face-centered rectangular (FCR) stagger ball

pattern.

Figure 3 shows an isometric view of the escape routing

study performed in Cadence APD [7]. Using GSSG and GS

transmission line structures, 2492 die-to-die interconnections

are required between logic and memory—indicating the need

for a logic die with 20 m FLI pitch. Assuming a 15mm x

15mm logic die with 250 m die edge keep out and 20 m

FLI pitch, four exterior in-line signal rows are needed.

Routing at 20 m FLI pitch is possible using a fan-in/fan-out

escape technique at target design rules in Table 1.

Figure 3. HBM escape routing study on a six-metal layer

2.5D glass interposer.

Insertion Loss and Crosstalk in High-density Channels

Minimum line and space requirements identified in Table

1 have two consequences on signal integrity for high-density

die-to-die interconnects. First, insertion loss increases with

decreasing line width. Second, the number of ground and

supply lines that can be routed from a die limits the line-to-

line shielding. Therefore, worst-case insertion loss, far-end

crosstalk (FEXT) and near-end crosstalk (NEXT) were

analyzed using 3D-EM simulation [7]. The stack-up in this

analysis was based on the routing study results in Figure 3 and

is shown in Figure 4 below.

Figure 4. Routing structure in four-metal layer, double-sided

glass interposer used for electrical modeling.

The routing density is lower on TPV layers due to the

increased via pad size. Decreased signal density on these

signal layers is represented by port 5 and 6 in the data bus

cross-section in Figure 4. The signal integrity analysis for

insertion loss and crosstalk did not include a direct

comparison between glass and silicon since through interposer

lines were not included in the model and signal length was

only 1.5 mm.

The worst-case insertion loss for an 8-bit data bus section

is shown in Figure 5. The insertion loss plot is for a signal line

on the TPV signal layer (port 5). Up to f = 18.5 GHz,

insertion losses less than 0.67 dB/mm are observed. The worst

case line-to-line coupling for the 8-bit data bus section is

shown in Figure 6. The NEXT and FEXT plots shown

correspond to a signal line on the TPV signal layer (port 5).

At low frequency up to f = 6 GHz crosstalk between data lines

is less than 20 dB.

stacked μ-via

50 μm φ TPV

M1

M2

M3

M4

M5

G S S GG S S G

G S S GS G S

1 2

3 4

5 6

7 8

743

The simulated channel performance is adequate for wide

I/O, low data rate per channel applications such as HBM.

Figure 5. Worst-case insertion loss for an 8-bit high-density

die-to-die data bus.

Figure 6. Worst-case crosstalk on high-density die-to-die data

bus.

Time Domain Analysis of Double-side High-density

Channel

A five-metal layer GSSG structure was modeled to better

understand the effect of multiple RDL microvia and TPV

transitions on line performance. Insertion loss simulations and

time domain analyses were performed to observe the

performance of double-side signal routing scheme for a 2.5D

interposer architecture. In this analysis, a direct comparison

with wafer silicon interposer technology is beneficial to

quantify the performance benefits of glass over silicon. The

design rules shown in Table 1 were again used for the glass

interposer. The design rules for silicon were based on

published literature [8, 9].

Figure 7. Insertion loss of through package lines in high-

density die-to-die data bus

Double-sided signal routing performance was compared

for the glass and silicon interposer structures as shown in

Figure 7. Superior electrical performance was demonstrated

for glass over the range of frequencies analyzed. Highest

insertion loss for glass occurred at f = 16 GHz, with S21 of

1.11 dB, while highest insertion loss for silicon occurred at f =

18 GHz, with S21 of 2.65 dB.

To further assess whether double-sided signal routing was

feasible for glass interposers, a time domain analysis was

conducted to simulate full channel performance for those

signal lines routed through the interposer and bottom most

signal layer (M5 in Figure 2).

Figure 8. Eye diagram of backside GSSG structure driven

with 1 Gbps data signal (rise time tr, fall time tf = 100 ps).

A GSSG structure was chosen for this analysis to capture

the effect of line-to-line coupling on channel performance.

Signal routing density is expected to be adequate to support

this transmission line structure, as the M5 signal layer is not

limited by TPV pad size. The results of this time domain

analysis for a 1 Gbps pseudo-random bit sequence (PRBS)

input signal are shown in Figure 8. Large eye opening for

these signals lines demonstrates the feasibility of double-sided

signal routing on glass interposers.

Test Vehicle Design

Routing studies as well as the modeling and simulation

analysis above justify the need for 3 m wiring technology on

2.5D glass interposers, for escape routing at 20-50 m bump

pitch. Similar feature sizes have been demonstrated on

organic [10] and silicon [2] interposers using high-cost,

single-side thin film processes such as vacuum deposition and

chemical mechanical polishing (CMP). The double-side

process used in this study can be scaled to large panels, using

lamination of dry film polymer dielectrics and wet chemical

plating technologies, leading to much lower cost than wafer

processes [11].

Three types of structures were included in the test vehicle

layout: (a) ultra-fine line and space escape routing, (b)

transmission lines to characterize 3 m signal widths at high

frequencies, and (c) fine bump pitch daisy chains for 2.5D

assembly process optimization and reliability testing.

Test Vehicle Structure A - Escape routing

The escape routing coupon was a 25mm x 30mm body

size 2.5D glass interposer with 879 die-to-die

interconnections. The test vehicle was designed for two 10

mm x 10 mm dies with a die-to-die spacing of 100 m, and

chip-level interconnection pitch of 50 m. A bump landing

pad size of 20 m on the top metal layer of the glass

Glass Core Stack Silicon Core Stack

(a.) (b.)

100 umGlass

10 um ZIF

10 um ZIF5um

50 um

40 um

16 um

30 um

10 um

100 um10 Ω·cmsilicon

4um SiO2 (low κ)

5 um BCB

10 um

20 um

2um

1um SiO2 (thermal)

1um SiN

10 um

5 um

100 um

37.5 um

1.8 um

744

interposer enables the routing of 4 interior signal rows in one

layer with 3 m wiring technology. Outside the die shadow,

the traces fan-out to 5 m lines, with 500 m length between

the dies. Consequently, the largest line length at 3/3 m was

approximately 300 m.

Test Vehicle Structure B- High-frequency Structures

High-frequency test structures include 24 co-planar

waveguide (CPW) variants. Six different signal widths were

implemented in the design: (i) 3 m, (ii) 5 m, (iii) 10 m,

(iv) 15 m, (v) 20 m, and (vi) 25 m. For each signal width,

four different signal lengths were included: (a) 660 m, (b) 5

mm, (c) 15 mm, and (d) 25 mm.

Test Vehicle Structure C - 2.5D Two Chip Assembly

The 2.5D assembly coupon also used a 25mm x 30mm

body size glass interposer with 87 die-to-die interconnections.

A coarser line and space of 40 m is used for this coupon to

implement a serpentine daisy chain connection between die.

The 2.5D assembly coupon uses the same die design

described above for the escape routing coupon, namely, two

10mm x 10mm dies with 50 m FLI pitch (5 row in-line

design) and central area array at 150 m pitch with 100 m

die-to-die spacing. The micro-bumps were 15 m in diameter,

with a 5 m Cu height and a 10 m high SnAg cap.

Fabrication and Assembly

The test vehicles were fabricated on a 150mm x 150mm

square glass panel that is 300 m thick. For the initial fine line

routing process optimization and electrical characterization

test structures, a simple two-metal layer glass panel (1/0/1

stack up) was fabricated. The chip-level interconnect

reliability test structures were fabricated on a six-metal layer

glass panel (3/0/3 stack up). The interior layers (M2-M5) in

the six-metal layer panel included a copper mesh pattern with

approximately 55% copper coverage. The fabrication process

details are described in another publication [11], but a brief

summary is shown in Table 2.

Table 2. Process for two-metal layer (double-sided) panel

fabrication. Six-metal layer panel, Test Vehicle Structure C,

fabrication sequence repeats steps 1-7 three times. Two-metal

layer panel, Test Vehicle Structures A and B, fabrication

sequence follows steps 1-6.

# Process

1 17.5 m dry film polymer lamination

2 Electroless copper plating

3 Photolithography1,2 (dry film resist)

4 Electrolytic copper plating

5 Dry film resist removal

6 Seed layer etching3

7 Surface treatment (adhesion promoter) 1 Two-metal layer fabrication sequence uses Ushio UX-44101 projection

mask aligner [12] 2 Six-metal layer fabrication sequence uses contact photolithography 3 Differential spray etching used for two-metal layer fabrication sequence

Two-metal Layer Panel Fabrication

The fabricated structures with 3 m lines and spaces in the

escape region, and 5 m lines and spaces in the die-to-die

space are shown in Figure 9. Optical and scanning electron

microscope (SEM) inspections confirmed good yield of the

ultra-fine lines and spaces on glass for all 879 die-to-die

interconnections without delamination or bridging. The

measured line widths were slightly smaller than the designed

dimensions mainly due to over etch during copper seed layer

removal. Future designs will include an etch compensation

factor to account for this deviation.

(a.) (b.)

Figure 9. Demonstration of (a) 3/3 m escape routing and (b)

5/5 m fan-out on 1/0/1 glass interposer at 50 m bump pitch.

Six-metal Layer Panel Fabrication and Assembly

Results for six-metal layer panel fabrication using the

process flow described above are shown in Figure 10. Topside

metal layers are shown in the detailed cross-section of Figure

10c. Similar results were observed for bottom side

metallization.

The 2.5D assembly was performed using a semi-automatic

Finetech Matrix Flip-Chip Bonder [13] with a placement

accuracy of 3 m. Pre-applied underfill (B-Stageable No-

Flow Underfill by Namics Corporation [14]) was used to

confine the solder, prevent bridging at 50 m pitch, and to

control the shape of the solder joint during assembly by

viscosity control. The silicon dies were sequentially picked

and placed onto the interposer, using a 10mm x 10mm

vacuum-locked spring gimbal tool. The interposer was

maintained at 70°C to reduce the viscosity of the underfill

material for adequate bump-to-pad contact. Underfill volume

was optimized to prevent any movement of the first die during

the placement of the second die due to flow of the material in

the die gap. After sequential placement, both dies were

simultaneously bonded by low-pressure thermo-compression

at 260°C peak temperature, using a 20mm x 20mm pre-

leveled gimbal tool. The placement pressure was reduced

upon reaching the low viscosity point of the underfill material

to allow excess material to flow.

(a).

(b).

2.2 um Line3.8 um Space 4.2 um Line

5.8 um Space

745

Figure 10a shows the top view of the six-metal layer

interposer after 2.5D assembly. X-ray characterization of the

glass assembled structure was performed after placement of

the first and second die, respectively, and after thermo-

compression bonding, confirming that there was no

displacement of either the first or second die during the

assembly sequence. After the side-by-side chip assembly,

sample cross-sections indicated acceptable joint quality and

interconnection yield, despite a slight misalignment, as seen in

Figure 10b and 10c.

Figure 10. Demonstration of 2.5D FLI assembly at 100 m

die-to-die spacing (a.) top view of 25 mm x 30 mm six-metal

layer glass interposer (b) cross-section (c) FLI detailed cross-

section.

Electrical Characterization

Ultra-fine lines, while required for high-density die-to-die

interconnects, pose electrical design challenges for signal

integrity especially at increased signal length. As a first step

in the high frequency characterization of 3 μm signal lines on

glass, the insertion loss of CPW transmission lines was

measured up to 20 GHz after performing a SOLT calibration.

Measurement results shown in Figure 11 indicate good

correlation between 3D-EM simulations and VNA

measurements at signal lengths of 660 m and 5 mm, and,

more importantly, low insertion loss of approximately 0.12

dB/mm at 2 GHz.

Figure 11. Simulated and measured insertion loss of a 3 μm

signal CPW transmission line up to 20 GHz.

Conclusions

Results shown in the above analysis indicate the

advantages of glass interposers compared to silicon and

organic technology. This paper, for the first time, shows the

design, fabrication, and assembly of a panel-based, low-cost,

six-metal layer, 2.5D, 300 μm thick glass interposer at 50 μm

bump pitch. Side-by-side chip assembly with sequential pick-

and-place, and simultaneous TCB was demonstrated at 100

μm die spacing. Ultra-fine escape routing structures down to 3

μm line lithography were fabricated at high yield, verified by

optical and SEM inspections. Modeling, simulation, design,

and characterization of 3 μm, single-layer transmission line

structures confirmed low signal insertion loss up to 20 GHz.

Furthermore, double-sided signal routing on glass was

analyzed, and these simulated results show good signal

integrity for frequencies up to 6 GHz. Low loss TPVs resulted

in lower insertion loss in glass, compared to wafer silicon.

In summary, this paper describes the first panel-based,

2.5D glass interposer fabrication, demonstrating 3 μm RDL

wiring technology at 50 μm bump pitch. Such a technology,

when implemented in large panel manufacturing is expected

to result in about 5X cost reduction compared to silicon from

wafer fabs [15]. The electrical simulation and characterization

results demonstrate the superiority of glass for low-data rate

double-sided signal routing as well as low insertion loss for 3

μm lines fabricated using the aforementioned low-cost

processes.

Acknowledgements

Research results described above are part of the Low-cost

3D Glass Interposers and Packages (LGIP) program at

Georgia Tech PRC (GT-PRC). The authors acknowledge

those LGIP member companies and supply chain partners in

supporting this research effort. Additionally, the authors

would like to thank Jialing Tong from GT-PRC, and Ryuta

Furuya, a visiting engineer to GT-PRC from USHIO, for his

help in operating the Ushio UX-44101 photolithography tool

with panel stepper lens (model "Square 70") used in

fabrication.

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