Page 1EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Introduction to IC Test Tsung-Chu Huang ( 黃宗柱 ) Department of Electronic Eng. Chong Chou Institute of Tech

Page 1EL/CCUT T.-C. Huang Apr. 2004

TCH

CCUT

Introduction to IC TestIntroduction to IC Test

Tsung-Chu Huang(黃宗柱 )

Department of Electronic Eng.Chong Chou Institute of Tech.

Email: [email protected]

2004/04/19


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Syllabus & Chapter PrecedenceIntroduction

Modeling

Logic Simulation Fault Modeling

Fault Simulation

Testing for Single Stuck Faults

Test Compression

Built-In Self-Test

Design for Testability

(II)


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t

Critical Path Tracing

1. A line l has a critical value v in the test (vector) t iff t detects the fault l s-a-!v. A line with a critical value in t is said to be critical in t.

2. POs are critical and the others are found by backtracing.3. Paths composed of critical lines are critical paths.4. A gate input is sensitive (in a test t) if complementing its valu

e changes the value of the gate output.5. If a gate output is critical, then its sensitive inputs, if any, are

also critical.

lD=1/0


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Example

E

J

B

A

CD

Hi

Hj

F

H

I

G K

Gi

Gj

Ci Cj

1

0

1

10

11

1

0


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Self-Masking

A

B

C

Bi

Bj E

F

G

Z

1

1

1

A

B

C

Bi

Bj E

F

G

Z

1

1

0

Stem B is self-masking.

Stem B is critial.


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Capture Line

1. Let t be a test that activates fault f in a single-output combinational circuit. Let y be a line with level ly, sensitized to f by t. If every path sensitized to f either goes through y or does not reach any line with level greater than ly, then y is said to be a capture line of f in test t.

2. A capture is a bottleneck for the propagation of fault effects.

3. A test t detects the fault f iff all the capture lines of f in t are critical in t.


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Cones & Fanout-Free Region

1. A Cone contains all the logic feeding one primary output.2. To take advantage of the simplicity of critical path tracing in f

anout-free circuits, within each cone we identify fanout-free regions (FFRs).

3. The inputs of a FFR are checkpoints of the circuit, namely fanout branches and primary inputs. The output of a FFR is either a stem or a primary output.

J

B

A

CD

Hi

Hj

F I

G

HGi

Gj

Ci Cj


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Testability

A Typical Combinational Circuit

Controllability Observability


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STAFAN: Statistical Fault AnalysisAgrawal, 1985

1. Vector-based probability2. C1(l): The probability causing the output of line l a value v3. O(l): The probability propagating response from l to any out

put.4. Example:

x

y

zw

5.010 cc

5.010 cc

5.010 cc

5.010 cc

75.0

25.0

1

0

c

c

75.0

25.0

1

0

c

c

01

0

1

75.075.0

cc

c


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Syllabus & Chapter PrecedenceIntroduction

Modeling

Logic Simulation Fault Modeling

Fault Simulation


Test Compression

Built-In Self-Test

Design for Testability

(I)


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1. Test Generation: Random vs. Diterministic2. ATPG for SSFs in Combinational Circuits3. ATPG for SSFs in Sequential Circuits


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Test Generation: Random vs. Deterministic

Test Selection

Fault Simulation

Fault Dropping

TE enough?

Done

No

Fault Selection

Test Generation

Fault Simulation

Fault Dropping

TE enough?

Done

No


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Test Generation: Random vs. Deterministic

#patterns

Test Efficiency

0 Test set generation time

Expected time per pattern

0


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5-Value Operations

v/vf

0/0 0 0

1/1 1 0

1/0 D ↓

0/1 D ↑

Notations AND

0

1

D

D

X

0

0

0

0

0

0

0

1

D

D

X

1 D D X

0 0 00 0

D

D

X X X

0 D X

X

XD

0

OR

0

1

D

D

X

0

D

X

1

1

D

1

1 D D X

D

X X X

D X

X1

1 11 11

0 1 D D X

1 1


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Test Generation for Fanout-Free Tree1. Set all values to X

X

X

X

X

X

X

X

X

X

X

X

X

2. Justify(l, ~v)

X

X

3. Propagate(l, v/vf )

Justify for Enabling


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State 2

Decision Process in Justification

State 1

1

1 1 1


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Decision Process in Justification

0

000 001 010 011 100 101 110

State 1

Branches of Decision Tree


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Sub-Process

Backtracking in Decision Tree

A

B CB C

Conflictor

Contradiction

In typical circuits, test generation for some faults usually have more than thousands of backtracking


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Test Generation for Fanout-Free Tree1. Set all values to X

X

X

X

X

X

X

X

X

X

X

X

X

2. Justify(l, ~v)

X

X

3. Propagate(l, v/vf )

Justify for Enabling

Possible Backtracking with Fanout

If Conflict?

Backtracking


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Concept of Frontiers

J-Frontier D-Frontier

D-frontier: all gates with any D or \D on their inputs – a queue waiting for propagation.

J-frontier: all gates keeping track of unsolved


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Bonus Project 1

1. Write a set of C (or C++) programs to read the ISCAS85 benchmark.

2. Construct an internal model (data structure).3. Do functional logic simulation in the internal model.4. Add a bit for fault insertion in each gate and do serial fault

simulation.


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Bonus Project 2

1. Be familiar with a test tool in this laboratory environment, say, SynTest, Mentor or Synopsys, e.t.c.

2. Try at least 3 instances in ISCAS89 benchmark, do the full-scan test syntheses and obtain the test patterns and report the associated parameters (i.e., fault coverage, test efficiency and approximated area overhead.)

Documents

Page 1EL/CCUT T.-C. Huang Apr. 2004 TCH CCUT Introduction to IC Test Tsung-Chu Huang ( 黃宗柱 ) Department of Electronic Eng. Chong Chou Institute of Tech