Performed by:Alexander Pavlov David DombInstructor: Mony Orbach

High speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

הטכניון - מכון טכנולוגי לישראל

הפקולטה להנדסת חשמל

Technion - Israel institute of technologydepartment of Electrical Engineering

דו”ח סיכום פרויקט )סופי(Subject:

GPS/INS Computing System

2009סמסטר אביב 1

AbstractHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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Developed in the “Technion” and Implements the tightly coupled INS/GPS navigation unit, with the particle filter.

The algorithm stages:

Solution – top designHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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Basic ArchitectureHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

•24Bit words data bus.• FIFO-Like streaming interfaces ( Request + Empty / Full )• Controlled By Start/Finished activation mechanism

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BasicStreaming

Block

Start Finished

Data outRead Request Empty

Control

Input Path

Output Path

Particle Propagation UnitHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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clockresetstart

finish

ParticlePropagation

Unit

X[0..439]

INS[0..287]X_OUT[0..439]

Particle Propagation UnitHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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Propagation Unit 1

Propagation Unit 2

Propagation Unit 6

MUX(6 to 1)

Propagationtimingcontrol

Single Particle Propagation Data FlowHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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Propagationflow

control

Estimation UnitHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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clockreset

New_Data_In

Estimation_Ready

EstimationUnit

X[0..439]

W[0..23]ESTIMATED_DATA

[0..439]

Estimation UnitHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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W

X Σ Estimated Data×

Physical ImplementationHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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Physical implementation of entire design was unsuccessful due to lack of FPGA resources.

Therefore, only 1 of the 6 parallel “propagation unit” blocks was implemented.

A design with 6 prop units will need approximately: • 130K combinational ALUTs )85K available(.• 162K logic registers )85.2K available(.• 20M block memory bits )8.25M available(.• 4074 DSP blocks )896 available(.

Timing AnalysisHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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The implemented design of 1 prop unit produced:• Particle LATENCY – 97 clock cycles )from “start” to “finish”(

@100MHz = 1uSec• Throughput of 38 clock cycles )from “finish” to “finish”(

@100MHz = 380nSec The total time with the implemented design of 1 prop

unit produced was 30,000 particles in 1,140,059 100MHz clocks = 11.4mSec.

Accuracy AnalysisHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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We have encountered many problems while trying to test our results:• The “Generic program” for 1 FPGA did not work correctly – we were unable to

control the inputs to the design.• The “Generic program” for 4 FPGAs did not work as anticipated with the SW data

files:o The SW data input files were arranged not according to the “bits order” agreed

upon.o The program’s data output files did not reflect the output values from our

design correctly. We have made a manual accuracy check for one particle, by comparing the

result as viewed with the “signal tap” tool to the SW result. For the tested particle, we got a location result which was different from the SW

result by 0.0002%

Project SummaryHigh speed digital systems laboratoryהמעבדה למערכות ספרתיות מהירות

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Implementation of our design - PARTIAL - due to lack of FPGA resources.

Design testing and integration - PARTIAL - due to problems with the testing environments and no cooperation from other design teams )which finished their project(.

In terms of possibility – it seems that it is possible to implement the “Propagation” and “Estimation” stages of the project, within the necessary timing requirements, on a better, more powerful FPGA )without changing the design(