Principles of sequential logical circuits

Michal Lucki

Author: Michal Lucki Title: Principles of sequential logical circuits

Compiled by: esk vysok uen technick v Praze Faculty of Electrical Engineering

Contact address: Technicka 2, Prague 6, Czech Republic Inovace pedmt a studijnch materil pro

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EXPLANATORY NOTES

Definition

Interesting

Note

Example

Summary

Advantage

Disadvantage

ANNOTATION

The goal of this module is to introduce the principles of sequential logics. Selected aspects of more advanced logic circuits, such as Mealy or Moore machine, particular design steps, minimization algorithms are discussed in details.

OBJECTIVES

After studying this module, a student should know the principles of operation of common sequential circuits, such as Mealy or Moore machines, devices with clocks, flip-flops etc. A student should be familiar with design steps and algorithms of minimization of states of a sequential device. The basic knowledge on combinational logics and Boolean algebra is assumed. Students should be able to solve tasks, to specify type of a machine and its states, to determine state diagrams, tables of transitions, to minimize number of states and encode output them. Those steps are necessary to practical implementations.

LITERATURE

[1] GREGG, J.: Ones and Zeros: Understanding Boolean Algebra, Digital Circuits, and the Logic of Sets, IEEE Press Understanding Science & Technology Series, Mar 16, 1998

[2] STANKOVIC, R., ASTOLA, J.: From Boolean Logic to Switching Circuits and Automata: Towards Modern Information Technology (Studies in Computational Intelligence), Springer, Mar 7, 2011, ISBN-10: 3642116817

[3] HASSOUN, S., SASAO, T.: Logic Synthesis and Verification (The Springer International Series in Engineering and Computer Science), Kluver Academic Publisher, Nov. 1, 2001, ISBN-10: 0792376064

[4] HACHTEL, G., SOMENZI, F.: Logic Synthesis and Verification Algorithms, Springer, Feb 10, 2006, ISBN-10: 0387310045

[5] KOHAVI, Z., JHA, N.: Switching and Finite Automata Theory, Cambridge University Press, 2009, ISBN-10: 0521857481

[6] HOLDSWORTH, B., WOODS, C.: Digital Logic Design, Fourth Edition, Dec. 17, 2002, Integra Software Services, UK Printed, ISBN-10: 0750645822

[7] PEDRONI, V.: Circuit Design and Simulation with VHDL, MIT Press, Sep. 17, 2010, ISBN-10: 0262014335

[8] Nelson, V., Nagle, H., Carroll, B., Irwin, D.: Digital Logic Circuit Analysis and Design, Mar 18, 1995, ISBN-10: 0134638948

Index 1 Introduction .......................................................................................................................... 6

1.1 Assumed knowledge (1/2) .......................................................................................... 6 1.2 Assumed knowledge (2/2) .......................................................................................... 8 1.3 Task: sequential logic device solved as a combinational circuit (1/2) ..................... 11 1.4 Task: sequential logic device solved as a combinational circuit (2/2) ..................... 13

2 Sequential logics ................................................................................................................. 14 2.1 General design stages of sequential logics ............................................................... 14 2.2 Sequential logic devices ........................................................................................... 15 2.3 Transformation of a Mealy machine into a Moore machine .................................... 17 2.4 Task: binary adder specification of a state diagram and a table of transitions ...... 18 2.5 Task: specification of states and transitions of a binary comparator ....................... 20 2.6 Case study sequential logics in a factory ............................................................... 21 2.7 Case study sequential controller for pumps .......................................................... 23

3 Optimization of finite state sequential machines ............................................................. 25 3.1 Transformation of a transition table into a triangle table ......................................... 25 3.2 Verification of non-contradicting states in a triangle table ...................................... 27 3.3 Re-grouping of non-contradicting states .................................................................. 28 3.4 Minimization of transition table ............................................................................... 29 3.5 New alphabet ............................................................................................................ 30 3.6 Task: optimization of a synchronic counter (1/3) .................................................... 31 3.7 Task: optimization of a synchronic counter (2/3) .................................................... 33 3.8 Task: optimization of a synchronic counter (3/3) .................................................... 35 3.9 Encoding of a sample transition table of a Moore machine ..................................... 36

4 More advanced sequential devices .................................................................................... 38 4.1 D-type flip-flop ......................................................................................................... 38 4.2 D-type flip-flop with asynchronous/synchronous clear ........................................... 39 4.3 JK and T flip-flops ................................................................................................... 40 4.4 Modulo-16 binary counter ........................................................................................ 41 4.5 Shift registers (SIPO) ............................................................................................... 43 4.6 Shift registers (SISO) ............................................................................................... 45

5 Final test .............................................................................................................................. 46

1 Introduction

1.1 Assumed knowledge (1/2)

A student should be familiar with the fundamentals presented in the previous module entitled Fundamentals of combinational logics. Basic knowledge on Boolean algebra, binary codes, operation of logical gates, interpretation of truth tables, minimization of Karnaugh maps, and principles of operation of a simple latch or a multiplexor is assumed.

For better comprehension, let us remind you some of the most necessary background information on combinational logics, which applies to sequential logics and more advanced digital devices.

Boolean algebra y = a & 0 y = 0, y = a & 1 y = a, y = a | 0 y = a, y = a | 1 y = 1

4-position BCD particular bits of code words are originated by the conversion of decimal values, starting with the most significant bit at the left hand (23, 22, 21, 20 = 8, 4, 2, 1).

0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111

4-position Gray code is a binary system, in which two successive code words differ in one bit.

0000, 0001, 0011, 0010, 0110, 0111, 0101, 0100, 1100, 1101, 1111, 1110, 1010, 1011, 1001, 1000.

3- or 2-position code words can be derived from the right-hand bits of a 4-position Gray code.

Truth table is a mathematical expression used to compute the functional values of logical functions. It contains a column for each input variable (for example a, b), and one or more final columns for all of the possible results of the logical operations. Each row contains one combination of input variables (0s and 1s), and the result of the operation true (1) or false (0).

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Sample truth table.

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1.2 Assumed knowledge (2/2)

Primitive gates AND the output is true (1) if all the inputs are true. It operates as a logical multiplication.

OR the output is true (1) if at least one of the inputs (or more) is true. It operates as a logical sum.

XOR known as an exclusive OR. It results with 1 if one of the inputs is 1 and the other is 0. True output excludes the case when both inputs are true.

NAND the negation of an AND (AND in series with NOT).

NOR the negated OR.

XNOR The negation of XOR. Known as NXOR.

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Primitive gates.

Karnaugh map is a form of representation of logical functions used for reduction of mathematical description of logical function and the minimization of number of logical gates in practical implementations. Karnaugh maps offer an overview on the logical states that could be dropped, because they are covered by some other expressions.

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Sample 4-variable Karnaugh map.

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1.3 Task: sequential logic device solved as a combinational circuit (1/2)

Some tasks dealing with sequential logics can be solved as combinational logics.

Let us consider a heater with two sensors of temperature. The first sensor indicates that temperature is above/below 15C, the other one indicates temperature above/below 25C. The heater is switched automatically on, if temperature falls below 15C and it is switched off if temperature reaches 25C. There is no manual switch and no flame indicator. Two variables are introduced, in the contrary to the previous task, variables are low-active, they activate actions at the value of logic 0:

Solution:

Input variables:

1 0, 15COR 1, temp 15CT temp= < > 2 0, 25COR 1, temp 25CT temp= < >

Output variable is:

0, , 2 1, , 1Y not heating disabledby signal fromT OR heating activated by signal fromT= First sensor is OFF until the temperature of 15C is reached. If temperature T is from the range (15, 25), first sensor is ON, if temperature is >25, both sensors are ON. Activation is by T1, deactivation is by T2.

Table describing operation of a heater:

Truth table.

There are two possible outputs for the input combination 10. The problem occurs because of a hysteresis. For temperature 15

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This approach can be demanding, especially when specifying tables of operation, because different outputs can be assigned for given combination of operands (i.e. input values). Then, such relations are not functions in terms of mathematics. This is unusual in common combinational systems. Then additional variables to specify which particular output is to be assigned (usually basing on past values) must be introduced. Since a sequence of actual and past states is monitored, we deal with sequential or synchronous logical device.

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1.4 Task: sequential logic device solved as a combinational circuit (2/2)

An additional internal variable informing about temperature in previous state (n-1) is introduced. We consider the sequence of states. Logical gates implement functions assigning unique output for given operands.

Notice that the n-1 value is directly copied from the previous row (state n). By adding an internal variable being the feedback from output y, we solved the problem of multi-vocal input 10 (Now, it is split into 101 and 100). Moreover, new rows in the table are originated. For example, 11 are split into 111 and 110, because we cannot avoid the sequence of 111 passing from 101 to 110. We fill out the Karnaugh map; we treat yn-1 as an internal variable:

Block scheme of sequential circuit and updated truth table with an internal variable.

Karnaugh map.

Designed circuit.

Conclusion: in combinational logics, the output values are directly related to the current combination of operands. In sequential logics, the output values depend not on its current input values and on previous output input values, depending thus on past inputs. That is, the output values depend on a sequence of input values.

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2 Sequential logics

2.1 General design stages of sequential logics

Schematic illustration of particular design steps of sequential devices and circuits is presented below.

Schematic illustration of particular design steps of sequential devices and circuits.

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2.2 Sequential logic devices

In combinational logics, an actual state of outputs depends only on actual values of inputs (a unique output is assigned to a specific input; the output function can be directly minimized by Karnaugh maps, Boolean algebra or de Morgan transformations):

Yt = f (Xt)

In sequential logics, one combination of operands can be assigned different outputs. This is because an actual state of outputs depends not only on actual inputs, but also on the past value or on the sequence of past input values, creating internal states required for deriving the actual outputs. The values of internal states are kept in an internal memory and are not available to a user.

Yt = f (Xt, Xt-1, Xt-2)

The memory exhibits an actual internal state of a machine. An actual internal state and an actual output value are, as follows:

At+1 = (At, Xt) Yt = (At, Xt) Where Xt is actual input value, Yt is actual output value, At is actual internal state, At+1 is future internal state, is function of transition, is function of outputs.

A machine, in which finite number of states is determined by current internal state and values at inputs, is known as a Mealy machine. Output values of a Mealy machine can be changed immediately by new input value (the small delay is due to the propagation time). Then, the outputs are changed asynchronously with respect to clock (timing), meaning that the outputs change at unpredictable times, making timing analysis harder.

However, outputs can be determined by internal state only. The machine can be described, as follows:

At+1 = (At, Xt) Yt = (At)

Such a machine is known as a finite-state Moore machine, in which an output is determined only when the internal state is updated. Since internal state is updated in specific time instants with respect to the clock, the machine acts as a synchronous device.

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Mealy and Moore machine schematic diagram.

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2.3 Transformation of a Mealy machine into a Moore machine

Every Mealy machine can be transformed into a Moore machine. Internal states, presented in a transition table of a Moore machine must be redefined. New states are assigned basing not only on Mealys internal states, but also on its outputs (directly influenced by inputs).

Sample Mealys machine transition table.

Table summarizing the conversion process.

Moore machine transition table originated from a Mealy machine.

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2.4 Task: binary adder specification of a state diagram and a table of transitions

Task: consider a binary adder, which adds two n-digit binary strings. The addition is performed bit by bit, starting from the least significant bit.

Notice that a carry in from the addition of previous bits should be taken into account.

There are two bits at the input (one bit from each string); possible combinations are 00, 01, 10, 11.

0 + 0 + no carry in from previous operation results in 0 without new carry in

0 + 0 + carry in from previous operation results in 1 without new carry in

0 + 1 (or 1 + 0) + no carry in from previous operation results in 1 without new carry in

0 + 1 (or 1 + 0) + carry in from previous operation results in 0 with new carry in

1 + 1 + no carry in from previous operation results in 0 with new carry in to the more significant bit

1 + 1 + carry in from previous operation results in 1 with new carry in to the more significant bit

Solution:

There are two internal states:

A1 an addition without carry in (p = 0)

A2 an addition with carry in (p = 1)

The states can be represented in graphical form, known as a state diagram.

State diagram of a binary adder.

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Tables of transitions of a binary adder.

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2.5 Task: specification of states and transitions of a binary comparator

The circuit should compare two binary strings Ci and Di bit by bit from the least significant bit.

Solution:

Table of states of a binary comparator.

State diagram of a binary comparator.

Table of transitions of a binary comparator.

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2.6 Case study sequential logics in a factory

Three containers C1, C2, and C3, as displayed in the below figure, are supplemented by some material. The containers are equipped with sensors x1, x2, x3, indicating the level of material in particular containers. Logical 1 signalizes the low amount of material and thus the demand for service. Design a circuit controlling the operation of a trolley developing material to the boxes.

Block scheme of a sample sequential logics in a factory.

Solution:

1) If every container indicates low amount of material, service should be provided in the order: C1, C2, C3, C1, C2, C3, C1

2) If two of three boxes are empty, service is provided alternately: Ca, Cb, Ca, Cb, Ca

2) If one of three boxes is empty, provide a service to it

3) If no sensor is active, there is no action

4) C1 has higher priority than C3

There are four internal states:

Table of states.

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State diagram.

Table of transitions.

Notice that the clock period should be long enough to complete the service of a container. Although S1 is much closer than S3 to the initial position of a trolley, time given for a service is identical, which might be found as not effective.

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2.7 Case study sequential controller for pumps

Design a controller for two pumps P1 and P2 pumping water from a mine. The water level is indicated by two sensors x1 and x2. If a sensor detects water, it indicates the value of 1. The pumps work alternately. If a water level is above x1, we switch on one pump, the one which was not used in the previous action. A pump is switched off if the water level is below x2.

Solution:

Block scheme of a controller of pumps.

Table of states.

Notice that for water level between two sensors, x1 x2 = 01, there is a hysteresis. For this input combination, a pump can be working, if water previous input combination was 11, or both pumps can be switched off, if previous combination of inputs was 00. We must consider historical input values stored in an internal variable.

Input combination 10 is impossible because the water level above x1 and below x2 has no physical interpretation and would mean that x2 sensor is broken. Because of this fact, states for this input combination are presented as -.

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State diagram.

Table of transitions.

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3 Optimization of finite state sequential machines

3.1 Transformation of a transition table into a triangle table

A minimized machine executes the same function as an original machine, but has lower number of states. The minimization process is based on series of schematics algorithms. However, some steps are very intuitive.

Let us consider a transition table of a sample Mealy machine.

Sample table of transitions of a Mealy machine (two equivalent expressions).

We construct a triangle table, in which the states of a machine are compared. Concerning seven states, the table contains six rows (2-7) and six columns (1-6). The first row and the seventh column is missing, because the comparison of first state with itself (and seventh state with itself) can be dropped and has no contribution to the minimization process.

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Sample triangle table.

We put X to those fields, for which both compared states are assigned different outputs. For example, state 1 has 00 as its outputs and state 2 determines -1 at the output, which means that they cannot be unified. Then we write X at the cross of column 1 and row 2. This operation is repeated for every combination of rows and columns.

In the following step, we put V to those fields, for which the outputs and the internal states are non-contradicting.

What are non-contradicting states in terms of logics? The following cases can be considered. Outputs and internal states can be identical or outputs / internal states do not exclude each other. One of the compared states is not specified or the next internal states are the same as actual states.

Triangle table obtained for considered circuit.

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3.2 Verification of non-contradicting states in a triangle table

The outputs of all the remaining empty fields are non-contradicting, but the next internal states are different. We write down those pairs of the next states into empty fields. If those states are non-contradicting, we can conclude that the actual states depending on them are non-contradicting, too.

Specification of next states in triangle table.

Now, we verify if the pairs placed in the table are contradicting or not. For example, if states (2,4) are non-contradicting, we conclude that states (2,3) are non-contradicting, too. Finally, we put the final decision: V or X. In some cases we can get into long sequences of the verification process. For example, because states (6.7) are non-contradicting (there is X on the cross of row 7 and column 6), we conclude that pair (4,5) are non-contradicting, and pair (4,3) is non-contradicting, too.

Verification of non-contradicting states in triangle table.

The set of non-contradicting states is, as follows:

{Q} = {1,6}, {2,3}, {2,4}, {2,5}, {3,5}, {5,7}

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3.3 Re-grouping of non-contradicting states

For the set of non-contradicting states:

{Q} = {1,6}, {2,3}, {2,4}, {2,5}, {3,5}, {5,7}

a diagram of non-contradicting states is drawn. We draw a line between two states, if they are non-contradicting. A group of non-contradicting states is created by the states, which are connected with all other states within this group.

Re-grouping of non-contradicting states.

Non-contradicting states are re-grouped:

{Q} = {1,6}, {2,3,5}, {2,4}, {5,7}

Those groups could potentially form minimized states.

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3.4 Minimization of transition table

Simplified transition table based on the minimized states is presented in the below figure:

Partially minimized transition table.

To complete the table, a new alphabet covering all the states must be introduced, for example:

{1, 6} B {2, 3, 5} C {2, 4} D {5, 7} E The following step of minimization is very intuitive. The following goal is to verify, if the next states in a transition table can be expressed by using a new alphabet only. (In this particular situation we can use only new states B, C, Detc). This step of minimization is very intuitive.

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3.5 New alphabet

The next states are: {3,-}, {2, -}, {-,-,6}, {2,4,-}, {-,7}, {2,5}, {6,6}, {-,6}

We can express them by using new alphabet, as follows:

{3,-} C {2, -} C or D {-,-,6} B {2,4,-} D {-,7} E {2,5} C {6,6} B {-,6} B In some cases, next states cannot be expressed by using new alphabet. In such a case, some groups must be intuitively simplified.

The minimal transition table in our example is, as follows:

Completed minimized transition table using new alphabet.

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3.6 Task: optimization of a synchronic counter (1/3)

Consider a circuit, which has one serial input, receiving 3-bit strings bit by bit. The possible input strings are 010 - 410 (in decimal), however transmitted as binary information. The output is set to 1, if and only there is an odd number of log1 bits in a string. The amount equal to zero is considered as even number. The possible input strings (X) and the corresponding outputs are, as follows:

Notice that decision is made during the last bit of a string (not after it). The decision is based on internal states and an actual value of the input, which directly influences the output. We deal with a Mealy machine.

Solution:

State diagram.

Transition table.

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Triangle table.

Non-contradicting states.

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3.7 Task: optimization of a synchronic counter (2/3)

Minimized transition table.

Encoded minimal transition table.

The table from the previous slide can be split into three Karnaugh tables for Q1, Q2, Q3.

Last but not least, the encoded transition table of outputs is presented as a Karnaugh map.

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Karnaugh map.

The function of outputs is: Y = Q1 | X Q2 Q3

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3.8 Task: optimization of a synchronic counter (3/3)

The same task can be solved as a Moore machine, for which a decision is made only basing on the internal states, so it must be done after the last (third) bit duration, when it is already taken into account in the internal memory. The decision is then available at the next clock edge, when the first bit of a new string is coming. The whole circuit is synchronous.

Corresponding state diagram.

Corresponding transition table.

Try to minimize this table.

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3.9 Encoding of a sample transition table of a Moore machine

Consider a sample transition table of a Moore machine:

Sample transition table of a Moore machine.

To encode three states, we need two bits. This is the minimum number of bits for binary representation of decimal values: 1, 2, and 3. Notice that two bits are also used to express output states. The easiest way is to assign the same combinations to the internal states. In practice, we give the same expression to both: In practice we copy output combinations to the corresponding internal states. 1 will then be expressed as 00, 2 as 01, and 3 as 10. The encoded table is, as follows:

Encoded table.

However, this is not a Karnaugh table. To obtain Karnaugh table, one row must be added: (there must be five rows with the following arguments: 00, 01, 11, 10). The added row is filled with because the input combination 11 is not possible in this particular example (it does not occur):

Karnaugh map.

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Encoded tables of outputs.

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4 More advanced sequential devices

4.1 D-type flip-flop

Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems. A flip-flop can be referred to as a register. Data appears to be loaded when a transition, or edge, occurs on the clock input, which is therefore said to be edge-sensitive (it is loaded when an edge occurs). A transition from 0 to 1 is known as a rising-edge or a positive- edge, while a transition from 1 to 0 is known as a falling-edge or a negative-edge. A D-type flip-flops clock input can be positive-edge or negative-edge triggered. The chevrons (arrows) associated with the clock inputs on the symbols indicate that these are edge-sensitive inputs. A chevron without an associated bobble indicates a positive-edge clock, and a chevron with a bobble indicates a negative edge clock. The last rows in the truth tables show that an inactive edge on the clock leaves the contents of the flip-flops unchanged.

Block scheme of a positive-edge triggered flip-flop and corresponding table of states.

Block scheme of a negative-edge triggered flip-flop and corresponding table of states.

Consider a sample implementation of a D-type flip-flop by using two D-latches in series. The first one is a Master D-latch, the next one is a Slave D-latch. The first latch can have an active-low enable (no action and keeping the previous value, if the clock is 1, passing data if 0) and the second one an active-high enable. Both of these enables are connected to a clock. When the clock value is 0, the master latch is enabled and passes any data. The slave latch is disabled and continues to store existing outputs. When clock is driven to 1, the master latch is disabled and stores an existing content; the slave latch passes the data from the output of the master latch to the output of the whole circuit. From the outside world it appears as that the flip was loaded by a rising edge at the clock input. Task: try to explain the operation of such a device.

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4.2 D-type flip-flop with asynchronous/synchronous clear

Some flip-flops have an additional ~clear input, which forces q to 0, no matter the value on the data input. Similarly, some flip-flops have a preset input, which forces q to 1, and some have both. These inputs may be either asynchronous or synchronous. In the more common asynchronous case, the effect of ~clear going active is immediate and overrides both the clock and data inputs (the effect of this input is not synchronized to the clock). By comparison, in case of a synchronous flip-flop, the effect of ~clear is synchronized to the active edge of the clock.

D-type flip-flop with synchronous/asynchronous clear.

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4.3 JK and T flip-flops

JK: When both the j and k inputs are 1, an active edge on the clock causes the outputs to toggle to the inverse of their previous values. T: there are no data inputs, the inputs are inversed at each active edge of the clock input.

JK and T flip-flops.

Summarizing, the word latch is mainly used for storage elements, while clocked devices are described as flip-flops. Flip-flops can be either simple (transparent or opaque) or clocked (synchronous or edge-triggered).

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4.4 Modulo-16 binary counter

Counting functions are commonly used in digital systems.

The number of states that the counter goes sequentially through before returning to its original value is called the modulus of a counter.

For example, a function that counts from 00002, to 11112, in binary (or 0 to 15 in decimal) has a modulus of sixteen and would be called a modulo-16, or mod-16, counter. Consider a modulo-16 counter implemented using D-type flip-flops.

Block scheme of a modulo-16 binary counter.

Table of states of a modulo-16 binary counter.

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Karnaugh maps of a modulo-16 binary counter.

d[3]=(q[3] & q[1] ) | (q[3] & q[2]) | (q[3] & q[0] )| (q[3] & q[2]& q[1]& q[0])

d[2]=(q[2] & q[1]) | (q[3] & q[0]) |(q[2] & q[1]& q[0])

d[1]=(q[1] &q[0] ) | (q[1] & q[0])

d [0]=q [0]

This example is based on positive-edge triggered D-type flip-flops with active-low ~clear inputs. Four flip-flops are used to store the current count value which is displayed on the q [3:0] outputs. When ~clear is set to 1 (its inactive state), a positive edge on the clock input causes the counter to load the next value in the count sequence. A block of logic is used to generate the next value, d [3:0], which is based on the current value q [3:0].

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4.5 Shift registers (SIPO)

Functions known as shift registers, which facilitate the shifting of binary data one bit at a time-are commonly used in digital systems. Consider a simple 4-bit shift register constructed using D-type flip-flops. This example is based on positive-edge triggered D-type flip-flops with active-low ~clear inputs (in this case were only using each registers q output). Also, this example is classed as a serial-in-parallel-out (SIPO) shift register, because data is loaded in serially (one after the other) and read out in parallel (side by side). When the ~clear input is set to 1 (its inactive state), a positive-edge on the clock input loads the value on the serial-in input into the first flip-flop, dff [0]. At the same time, the value that used to be in dff [0] is loaded into dff [1], the value that used to be in dff [1] is loaded into dff [2], and the value that used to be in dff [2] is loaded into dff [3]. Each flip-flop exhibits a delay between seeing an active edge on its clock input and the ensuing response on its q output. These delays provide sufficient time for the next flip-flop in the chain to load the value from the previous stage before that value changes.

Block scheme of a SIPO shift register.

Consider the below waveform, where a single logic 1 value is migrated through the shift register. Initially all of the flip-flops contain dont know X values. When the ~clear input goes to its active state (logic 0), all of the flip-flops are cleared to 0. When the first active edge occurs on the clock input, the serial-in input is 1, so this is the value thats loaded into the first flip-flop. At the same time, the original 0 value from the first flip-flop is loaded into the second, the original 0 value from the second flip-flop is loaded into the third, and the original 0 value from the third flip-flop is loaded into the fourth. When the next active edge occurs on the clock input, the serial-in input is 0, so this is the value thats loaded into the first flip-flop. At the same time, the original 1 value from the first flip-flop is loaded into the second flip-flop, the 0 value from the second flip-flop is loaded into the third flip-flop, and the 0 value from the third flip-flop is loaded into the fourth one.

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Waveforms for SIPO shift register, X is the initial dont know state; (it has no practical impact

on the following value).

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4.6 Shift registers (SISO)

Another common shift register variants are the parallel-in-serial-out (PISO), and the serial-in-serial-out (SISO).

Similarly, when the next active edge occurs on the clock input, the serial-in input is still 0, so this is the value that is loaded into the first flip-flop. At the same time, 0 value from the first flip-flop is loaded into the second flip-flop, the 1 value from the second flip-flop is loaded into the third one, and the 0 value from the third flip-flop is loaded into the fourth flip-flop.

Block scheme of a SISO shift register.

Summarizing, the design of sequential logical circuits is a schematic procedure, demanding the knowledge on specifying logical functions, minimizing the amount of states of a machine, optimal encoding and selection of logical components, such as latches or multiplexors, integrated circuits or RAM memories, controllers, ect.

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5 Final test

Please, verify your knowledge by solving the following final test.

1. In combinational logics

a) actual state of outputs depends on actual values of inputs

b) actual state of outputs depends on past values of inputs

c) actual state of outputs depends on past values of outputs Solution: a

2. Design stages of sequential logics, listed chronologically, are, as follows:

a) state diagram, transition table, triangle table, minimization process

b) transition table, Karnaugh map, specification of non-contradicting states, state diagram

c) selection of logical components, minimization of Karnaugh table, state diagram

d) transition table, state diagram, triangle table, Karnaugh maps Solution: a

3. So-called triangle table

a) contains n+1 rows and n+1 columns, where n is number of states

b) is representation of transitions between particular states of a machine

c) is used to find non-contradicting states that can be potentially minimized Solution: c

4. New alphabet used in a transition table

a) should cover all the actual and next states

b) should cover all the actual states, while next states can be covered by existing alphabet

c) should cover all the next states, while actual states can be covered by existing alphabet

d) should cover all the actual states, next states and outputs Solution: a

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5. D-type flip-flop

a) can be referred to as a modulo-16 counter

b) loads data when a transition, or edge, occurs on the clock input

c) is positive-edge triggered if negative edge of clock appears

d) is latched (keeps the value) if arising edge is detected since it is positive-edge triggered

Solution: b

6. Clear input of a D-type flip-flop

a) forces outputs to be cleared with no respect to data

b) in synchronous mode, it immediatelly overrides both the clock and data inputs

c) in asynchronous mode, clear going active overrides data inputs and it is synchronized with clock

d) operates as a clock Solution: a

7. Which sentences about flip-flops are true

a) JK flip-flop does not have a clock

b) JK flip-flop does have a clear input

c) T flip-flop does have a data input Solution: No answer

8. Modulo-16 binary counter

a) cannot be implemented by using D-type flip-flops

b) goes through the sequence of 16 states

c) goes through the sequence of 4 states

d) operates as a RAM memory Solution: b

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9. Devices known as SIPO are

a) shift registers

b) memories

c) curcuits consisting of flip-flops with parallel inputs

d) curcuits consisting of flip-flops with serial outputs Solution: a

10. Karnaugh map

a) is used to minimize logical functions

b) is named after Thomas Carnaugh

c) cannot contain dont know states

d) cannot cover more than 3 variables Solution: a

11. In sequential logics

a) one combination of operands can be assigned different outputs

b) actual state of outputs depends on actual inputs

c) actual state of outputs depends on past states

d) internal states are introduced to keep the information required to determine outputs

Solution: a, b, c, d

12. Mealy machine

a) has infinite number of states

b) can determine its states by current iternal state and values at inputs

c) can determine new outputs immediatelly by new input values

d) can set output only synchronously with respect to clock Solution: b, c

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13. Moore machine

a) has infinite number of states

b) determines new outputs only when the internal state is updated

c) can determine new outputs immediatelly by new input values

d) set output synchronously with respect to clock Solution: b, d

14. Transition table

a) is a form of representation of transition between particular states of a machine

b) is a canonic form of a logical function

c) is a table with minimal logical functions

d) specifies true or false for given operands and/or internal variables Solution: a, d

15. State diagram

a) is a form of representation of transition between particular states of a machine

b) is a canonic form of a logical function

c) is a diagram with minimal logical functions

d) provides an overview on outputs, operands and/or internal variables Solution: a, d

16. States can be considered as non-contradicting

a) since outputs and internal states are identical

b) since outputs / internal states do not exclude each other

c) since one of the compared states is not specified or the next internal states are the same as actual states

d) since outputs are identical to inputs Solution: a, b, c

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17. Minimization of transition table

a) has as its aim to minimize the number of rows

b) has as its aim to minimize the number of columns

c) has as its aim to find and remove non-contradicting states

d) has as its aim to replace a group non-contradicting states by one state Solution: a, d

18. Steps of design of a logical circuit contain

a) specification of all the input variables

b) specification of a truth table

c) specification of a Karnaugh map

d) deriving the minimized function and the coresponding circuit Solution: a, b, c, d

19. Gray code

a) assumes that successive code words differ in one bit

b) is used to label columns in Karnaugh maps

c) can be used to faciliate error correction

d) is a 4-position BCD Solution: a, b, c

20. Which sentences are true:

a) Mealy machine can be transformed into a Moore machine

b) triangle tables are usually specified from Karnaugh maps

c) triangle tables are specified basing on transition table

d) new alphabet specified directly from the minimized transition table will always cover all the states and no verification is required

Solution: a, c