Product Design Methodology - SOI Consortiumsoiconsortium.eu/wp-content/uploads/2017/02/2017-06-… · · 2017-06-14Functional/Logic design Circuit design Physical design Physical

1 SOI Industry Consortium – June, 2017

Product Design Methodology

June 2017 - Tokyo

Christophe Tretz, Giorgio Cesana, Carlos Mazure


Agenda

FD SOI performance advantages

SoC design approach

Ecosystem updates

Conclusions


FD SOI technology performance gains


Body Bias Advantages

Boost performances

Improve power efficiency

Enable leakage reduction

Enable area reduction

Reduce process dispersion

Allow compensation

techniques

4

Courtesy: ST - SOI Consortium 2016


The Advantage Illustration for IoT

RF Analytics

CPU & Memories

Power Management

SoC Architecture

X3 to X6 Power Consumption Improvement with .

* Measured on Silicon / Product Simulation

** Projection

Power Supply

Loss

RF

Analytics

CPU &

Memories

Other

SoC Power Consumption34 mW*

<10 mW*

<5 mW**

Previous

Generation (40LP)

FD-SOI

28nm

FD-SOI 28nm

Power optimized

5

Courtesy: ST - SOI Consortium 2016


Design flowD

esig

n F

low

Architectural design

Functional/Logic design

Circuit design

Physical design

Physical verification and

signoff

System Specification

Fabrication

Packaging and testing

Chip

• Starting a new design will go

through all the steps from

system specification to

manufacturing and testing.


Design flowD

esig

n F

low



Circuit design

Physical design


signoff


Fabrication


Chip

•

•Using FD-SOI, the following

steps could take advantage of

the technology, either through

performance estimation (blue)

or bias connections (orange)


Design flowD

esig

n F

low



Circuit design

Physical design


signoff


Fabrication


Chip

•

•

• It is not necessary to optimize

an SoC design at every stage,

but improvements can be

obtained progressively


Our proposed SoC roadmap strategy


NXP SoC slide

Courtesy: Synopsys - SOI Consortium Silicon Valley – April 2017


Motivation

• Being a smaller design house, new technologies such as

FD-SOI are very appealing but also frightening– Great potential performance improvements

– Can it be used without having special expertise or huge time to product

• The answer is simple:

– No you do not need to know anything about this technology to be able to use it and benefit from it (of course over time it is better to learn about all its intricacies to fully benefit from it)

– Yes a product can be easily and rapidly done using existing designs with minor modifications and potentially huge power improvements

– Yes the ecosystem to use FD-SOI is growing and allows smaller design house to use that technology!!!


Case 1: Simple digital SoC

• All digital SoC, using basic library

blocks, with some specialized

proprietary logic– Most standards blocks are already available in foundry libraries

– Recompile the proprietary logic with or without back bias optimization

– Benefit savings from the existing optimized blocks

• Using this approach, significant

power savings can be achieved by

reusing existing blocks and doing

minor recompile

De

sig

n F

low



Circuit design

Physical design


signoff


Fabrication


Chip


Case 2: RF – Mixed signal chip

• While this type of design likely

need to do a full circuit design and

physical design, they are usually

“small” and easier to control

• Turnaround time can be relatively

small with significant savings in

power

• Example: AnalogBits SERDES

De

sig

n F

low



Circuit design

Physical design


signoff


Fabrication


Chip


Remap example: AnalogBits

Courtesy: AnalogBits - SOI Consortium – April 2016


Remap example: AnalogBits

ANALOG BITS achieved this work in about 3 months!!!

Courtesy: AnalogBits - SOI Consortium – April 2016


Case 3: “complex” SoC with RF blocks

• Combination of the first 2 cases

• The RF blocks will take circuit

work, and require more design work

and testing while the digital portion

of the SoC can either be straight

library blocks that have already been

optimized, or sometimes might need

to be recompiled for some more

unique functions

• Significant power savings from

reusing those library elements

without a lot of design effort

De

sig

n F

low



Circuit design

Physical design


signoff


Fabrication


Chip


Case 4: “complex” SoC with RF blocks

• If the SoC uses too many non

library elements, there is more need

for recompiling the RTL

• These designs will require more

design time to complete, but it could

be a second step to case 3, where in

a first design pass, library elements

are used, and in a second (third, etc)

pass, more blocks are customized

and optimized

De

sig

n F

low



Circuit design

Physical design


signoff


Fabrication


Chip


Case X: fully optimized SoC

• Sometimes a full optimization is

desired, and some design can benefit

from all the advantages of FD-SOI

• Architecture and logic can be further

optimized and changed to take into

account back bias

• This approach will take the most

design time, but can be done in

parallel with a faster turnaround

design

• Most dramatic power improvements!!

De

sig

n F

low



Circuit design

Physical design


signoff


Fabrication


Chip


Status of the ecosystem, libraries and foundries


Courtesy: Synopsys - SOI Consortium – 2017


Courtesy: Synopsys - SOI Consortium – 2017


Courtesy: Cadence - SOI Consortium – 2016

Silvaco Confidential

Silvaco’s Comprehensive FD-SOI Design Flow

Layout

Spice

Parasitic extraction

Spice modeling

Process

Device

Measured Data

Schematic

Spice

LVS

DRC

TCAD

Parasitic reduction

Modeling Design & Verification

Reliability Analysis

Variation Analysis

Simulation

Courtesy: Silvaco - SOI Consortium Tokyo – May 2017


Existing 28nm libraries (non exhaustive list)

• Standard cell libraries in 8 and 12 tracks, multiple Vths

• Memory cells: 3SRAM, dual port, ROM

• Complex blocks:

– ARM A cores, working on M cores (with back bias),

– PVT sensors, bias generators

– interface such as USB2, USB3, HDMI, SATA, etc

–Memory interface such as DDR, LPDDR (2,3,4)

• Mixed signals blocks:

– PLL up to 1+ GHz frequencies

– Synthesizers, digital clocks

– DAC, ADC, video and audio

– SERDES

22FDX Design IP Portfolio

GLOBALFOUNDRIES Confidential 25

Foundation IP

Library

High Speed & High Density

Low Leakage & Low Power

Memories

Single Port High Density SRAM

Single Port High Speed SRAM

Time multiplexed 2-port SRAM

1-Port High Speed Register File

2-Port Register File

ROM

Low Power (ULP) Low Leakage (ULL) SRAM

eFuse Macro and OTP

General Purpose I/O Library

1.8V + OSC and 3.3v GPIO

Production: Q2 2017

Available

In Development

Analog IP and RF IP

Analog IP

Process Monitor & Temp Sensor

Video DAC

Audio DAC & Audio ADC

General Purpose PLL

Fractional PLL

RF IP

Bluetooth

WiFi

NB IOT

Specialty IoT

LDO Library

DC-DC

Real-Time Clock (RTC)

Interface IP

LPDDR4/3

LPDDR4/3 DDR4/3 Combo

USB2 OTG

USB3.0/3.1

PCIe Gen2(5G) and Gen3(8G)

SATA2

10G-KR

MIPI DPHY (CSI/DSI)

MIPI M-PHY

HDMI Tx

HDMI Rx

Display Port Tx/Rx

12.5G SerDes

16G/25G SerDes

Ready for Customer Design Starts Now; Production-ready IP validation in Q2 2017


Existing 22nm libraries (non exhaustive list)

• Standard cell libraries in 12, 8 and 7.5 tracks, multiple Vths

• Memory cells: SRAM, dual port, ROM

• Complex blocks:

– multiple ARM cores

– PVT sensors, bias generators

– interface such as USB2, USB3, HDMI, SATA, PCIe, etc

–Memory interface such as DDR, LPDDR (2,3,4)

• Mixed signals blocks:

– PLL and fractional, from 300MHz to 2GHz+

– Synthesizers, digital clocks

– DAC, ADC, video and audio

– MIPI designs

– SERDES


Conclusions

• Incremental design approach will enable every design

house to have access to FD SOI and benefit greatly from

its advantages

• The ecosystem is ready to be used, from foundries, to

IP/libraries, to EDA solutions;

• In a first pass, products can be obtained very rapidly with

minimum design efforts, with first silicon starts;

•Over time, more improvements can be obtained by taking

advantages of every aspect of the technology!

Documents

Product Design Methodology - SOI Consortiumsoiconsortium.eu/wp-content/uploads/2017/02/2017-06-… · · 2017-06-14Functional/Logic design Circuit design Physical design Physical