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Prof. Dr. Thomas Baier / DG8SAQ Juli 2006
Prof. Dr. Thomas BaierDG8SAQ
Prof. Dr. Thomas Baier / DG8SAQ Juli 2006
• Minimum frequency range 100 KHz … 30 MHz
• Sufficient accuracy to useS-parameters for simulations
• Utilize standard PC as much as possible • Cut down on hardware as much as
possible• Easily obtainable standard components,
solderable by amateur with soldering iron
Prof. Dr. Thomas Baier / DG8SAQ Juli 2006
Prof. Dr. Thomas Baier / DG8SAQ Juli 2006
Prof. Dr. Thomas Baier / DG8SAQ Juli 2006
from datasheet AD9851, Analog Devices
Prof. Dr. Thomas Baier / DG8SAQ Juli 2006
Computational Example: clock frequency RF-DDS: 180 MHzclock frequency LO-DDS: 170 MHz IF: 10 MHz
DDS Alias Frequencies
0
50
100
150
200
250
300
350
400
0 30 60 90 120 150 180 210 240 270 300 330 360 390
RF-Frequeny
Spec
ta o
f RF
and
LO D
DS
Prof. Dr. Thomas Baier / DG8SAQ Juli 2006
≈ 30 kHz
Prof. Dr. Thomas Baier / DG8SAQ Juli 2006
≈ 30 kHz
Usable frequency range: 200 Hz … about 500 MHzExceptions:Zero signal amplitude in vicinitiy of integer multiples of DDS clock frequency (180MHz, 360 MHz, 540 MHz …) → measurements not possible
Prof. Dr. Thomas Baier / DG8SAQ Juli 2006
Problem: make wideband BALUNSolution: use balanced Gilbert Cell Mixer
BALUN
RF
1 : 1
50
50
50
DUT
Bridge Voltage
50
50
ZS = 50
Prof. Dr. Thomas Baier / DG8SAQ Juli 2006
RF+ RF-
IF+ IF -
LO
Prof. Dr. Thomas Baier / DG8SAQ Juli 2006
Problem: Frequenzgang des DC-Blocks im Hz - Bereich
RF DDSZS = ∞
8,2
27
15
DUT
BridgeVoltage
10
ZS = 50,2
LO DDS
Reference Signal= Bridge Current
LO DDS
+
-
+
-
NE612
NE612
10 F Tantal
Prof. Dr. Thomas Baier / DG8SAQ Juli 2006
TX RX
to Parallel Interface to Line In +12V/250mA DC
100mm
Prof. Dr. Thomas Baier / DG8SAQ Juli 2006
Prof. Dr. Thomas Baier / DG8SAQ Juli 2006
Prof. Dr. Thomas Baier / DG8SAQ Juli 2006
LOAD "F64A.s1p"
LOAD "F64B.s1p"
Circuit Diagram [...] (E)Sweep Init (E)
Sweep "Initial analysis"LOOP 400 FREQ LIN 10.685Meg 10.714925MegW 0 Y "Gain" "dB" -30 0W 1 SMITH
Show + W 0 Y MagdB(S(2,1)) + W 0 Y MagdB(S(1,1)) + W 0 Y MagdB(S(2,2)) + W 1 DB S(1,1) + DB S(2,2)
EndSweep
port_2 270ohmport_1 270ohm
… e.g. with APLAC:
Prof. Dr. Thomas Baier / DG8SAQ Juli 2006
10.685M 10.692M 10.700M 10.707M 10.715M
-30.00
-22.50
-15.00
-7.50
0.00
Initial analysisAPLAC 8.00 Student version FOR NON-COMMERCIAL USE ONLY
Gain
dB
f/HzMagdB(S(2,1)) MagdB(S(1,1))MagdB(S(2,2))
Prof. Dr. Thomas Baier / DG8SAQ Juli 2006
VNWAZS = ZL = 50 Ω
VNWAsoftwarematched
HP8753Csoftwarematched
Prof. Dr. Thomas Baier / DG8SAQ Juli 2006
simulated matchingresistive matching
ZS = ZL = 50 Ω
ZS = ZL = 610 Ω
e.g. 11 kHz LC Filter
Prof. Dr. Thomas Baier / DG8SAQ Juli 2006
VNWA
HP8753C
Verbesserung durch 10 dB Dämpfungsglied vor RX-Eingang
e.g. 400 MHz SAW Filter
Prof. Dr. Thomas Baier / DG8SAQ Juli 2006
Achieved:• 200 Hz – 500 MHz covered with exceptions,
especially VLF-2m, 70cm covered!• Accuracy sufficient for network synthesis.• Minimum hardware, no tuning points.• Universal software• Principally achievable accuracy with PC sound
device: 0,01dB and 0,1°,currently limited by Mixer nonlinearities
Possible Improvements:• Higher level mixers• DDS devices with higher clock rates (up to 1 GHz)
