Readout Architecture for MuCh Introduction of MuCh Layout of Much ( proposed several schemes) Read ASIC’s Key features Basic Readout chain ROC Block Diagram

Readout Architecture for MuChReadout Architecture for MuCh

•Introduction of MuCh•Layout of Much ( proposed several schemes)•Read ASIC’s Key features•Basic Readout chain•ROC Block Diagram•Requirements to desig the FEB•Conceptual sketch of Tripple GEM Chamber with FEB•Indian contribution to CBM MuCh Electronics

• muon system consists of 16 detector layers with 100 μm position resolution • 5 absorber layers made of tungsten, iron and carbon of variable thickness.

The structure : •one sensitive layer is in front of the first absorber, three sensitive layers are between each two absorbers and three behind last absorber.

25th CBM-India Collaboraton Meeting, BHU, S. K. Pal29/12/2009

Introduction

Several schemes for MuCh are proposed :Modular Square ChamberSlat typeSector type ( 8Sectors)

2m

300

mm

300 mm

Chambers layout for MuChChambers layout for MuCh

Modular Square Chamber

One module is 30cm x 30cm36 Nos. of Modules in one plane

Profile is more to reduce dead space


Slat Type

2m

20 ChambersWidth of each chamber 10 cm.

X-section of chamber

Profile is less as compared to modular designWastage of chamber space

Chambers layout for MuChChambers layout for MuCh


Sector Type

8 Nos. of SectorsNo wastage of chamber SpaceSimilar type of chamberLess profile


Read-out ASIC to be used for MuCh is n-XYTER / CBM-XYTER

mixed signal chip process: AMS 0.35 μm CMOS 128 channels 1 test channel with analogue diagnostic output architecture for AC-coupling, employable for positive and negative signals self triggered, data driven de-randomizing, sparcifying readout at 32 MHz digital time stamp output analogue peak hight output maximum data loss at 32 MHz average input rate over 16 μs: 4%

Key Features


•analogue pile-up registry •programmable dead time •local threshold adjustment •Dynamic Range: 120000 e •Shaping time and noise performance:

•30 ns fast shaper at 30 pF input, 850 enc for positive signals, 1000 enc for negative signals •130 ns slow shaper at 30 pF input, 600 enc

•Timing resolution ~ 2-3 ns, time stamp resolution 1 ns

Key Features contd..

Basic n-XYTER Readout ChainBasic n-XYTER Readout ChainDetector

FEB ROCXY

TER

XYTE

RXY

TER

ADC

XYTE

R

Tag data

Tag data

Tag data

Tag data

ADC data

clockFP

GA

control

SFPMGT

DCB

FPGA

SFP MGT

MGT

Front-EndBoard

Read-OutController

Data CombinerBoard

to otherROC's

to ABB

SFP

SFP MGT

MGT


From Walter F.J. Mueller’s lecture

PC

Some ConfigurationsSome Configurations

Detector FEB ROC ABB

PCDCB ABB

Detector FEB ROC

Detector FEB ROC

Detector FEB ROC

Detector FEB ROC

Minimal Configuration

Expandable Configuration


Block Diagram of ROC BoardBlock Diagram of ROC Board

Two nos. of such Boards are already fabricated in India

Functional testing is in progress

Details in M.S.Dey’s lecture

Diagram taken from CBM-Wiki page105th CBM-India Collaboraton Meeting, BHU,

S. K. Pal29/12/2009

29/12/2009 5th CBM-India Collaboraton Meeting, BHU, S. K. Pal 11

Input needed to design the FEBType of package of XYTER chip

No. of Channels in one XYTER chip ( 64 or 128 or 32 ?)

Pad Size of the Detector

Gap between chamber and absorber i.e maximum available profile for FEB

Radiation dose on the Detector end.

Things to be considered at the Detector end:Cooling of the FEBPower ( LV ) connection to FEBsConnectivity between FEB and ROC … and many more …

Gas out

Gas in

HV (9 segments)

300 mm

300

mm

Conceptual sketch of Triple GEM chamber module

256ch. FEB

36 FEBs=9216chs


3-GEM chamber

Heat sinkXYTER

256 ch- FEB

chamber frame

X-section of chamber


Profile of Chamber

3GEM Chamber

50m

m

Heat Sink

XYTER chip

FEB PCB

Chamber PCB

Connector

10m

m


Tracking station plane

2m

ROC stack ROC stack


Indian Contribution to CBM MUCH Electronics

• India could supply complete detector system with electronics!

• XYTER integration for 0.5x106 detector channels:

2-chips or 4-chips (256 channels) to one hybrid FEE pcb (estimated 2000 boards)

• FPGA-based readout controller (ROC)

• adaptation and assembly ( ~500 boards needed)

• For a test case 2 ROC boards of current version have already been fabricated in India

The cost factor is the integration of chips !!


Documents

Readout Architecture for MuCh Introduction of MuCh Layout of Much ( proposed several schemes) Read ASIC’s Key features Basic Readout chain ROC Block Diagram