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8-1
Samsung
Confidential
SR
P S
heet Num
ber: 1 of 73
Intel PENR
YN
EXCEPT AS AUTHORIZED BY SAMSUNG.
3
A
SAM
SUN
G PR
OPR
IET
AR
Y
EXCEPT AS AUTHORIZED BY SAMSUNG.
4
SAMSUNG ELECTRONICS COS PROPERTY.
PCB Code :
Model Name :
Owner :
00
D
1
C
CPU :
SEC Mobile R &
D
T.R. Date :
13
MAIN
TPT : BA41-00919A
DRAW
D
Montevina Platform
(NB
9M)
ISTA
NB
UL
SAMSUNG ELECTRONICS COS PROPERTY.
ISTANBUL
4
APPROVAL
4
A
Remarks :
THIS DOCUMENT CONTAINS CONFIDENTIAL
Revision :
THIS DOCUMENT CONTAINS CONFIDENTIAL
4
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
2
1
Intel CA
NTIG
A PM
+ ICH
9M
PV
ELE
CTR
ON
ICS
NAN : BA41-00921A
Chip Set :
C
Dev. Step :
1
X
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
SA
MS
UN
G
4
PROPRIETARY INFORMATION THAT IS
GCE : BA41-00920A
2
2008.07.18
2
CHECK
2
BB
PBA Name :
3 3
PROPRIETARY INFORMATION THAT IS
Signature :
SAM
SUN
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OPR
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AR
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8. Block Diagram and Schematic
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8. Block Diagram and Schematic
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heet Num
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2
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8. Block Diagram and Schematic
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heet Num
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8-3
-
8-4
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8. Block Diagram and Schematic
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ICH
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-
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8. Block Diagram and Schematic
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Battery
3.3V
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THIS DOCUMENT CONTAINS CONFIDENTIAL
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-
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8. Block Diagram and Schematic
Samsung
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Confidential
SR
P S
heet Num
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PROPRIETARY INFORMATION THAT IS
4
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
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4* = S4_S
TA
TE
*) > SL
PM
* > SL
PS
3*
CL_P
WR
OK
6) P1.8V
_AU
X
15)VR
M3_C
PU
_PW
RG
D
PW
RO
K
PC
Ie
P3.3V
_MIC
OM
2) VD
C
P3.3V
_AU
X &
P5V
_AU
X
10) P1.5V
3
15) VR
M3_C
PU
_PW
RG
D
20) CP
U1_C
PU
RS
T*B
SA
MS
UN
G
9
1
6) P3.3V_AUX
CL_P
WR
OK
18
19) PC
I3_RS
T*
19) PC
I3_RS
T*
17) KB
C3_P
WR
GD
TP
S51124 Sheet 22-25
8
M-1) K
BC
3_DD
R_P
WR
ON
(TB
D) = 8) K
BC
3_SU
SP
WR
CP
U
5) KB
C3_S
US
PW
R
9-1
17) KB
C3_P
WR
GD
17
7) P1.05V
_AU
X
10) P5.0V
Adapter
10) P1.25
19
Ho
st Bo
ot / M
E O
ff
13
10) P1.05V
(IGF
X_C
OR
E)
POW
ER
SEQ
UE
NC
ESA
MSU
NG
PRO
PRIE
TA
RY
3
FD
C653N
SC
486
20
Sheet 40
2
10-1) P1.8V
1112)G
CO
RE
_PW
RG
D
9) KB
C3_P
WR
ON
13) KB
C3_V
RO
N (B
ack-up
)
2-1) P12.0V
_AL
W
2) VD
C
DC
/DC
Bd
16) CL
K3_P
WR
GD
1
18) CP
U1_P
WR
GD
CP
U
10-1) P3.3V
6) P1.8V
_AU
X
15)VR
M3_C
PU
_PW
RG
D
10-1) P1.5V
10-1) P1.25
10-2) P0.9V
1
Sheet 46-47
17) KB
C3_P
WR
GD
10-1) P1.8V
A
Sheet 46
16-1) Clo
ck Ru
nn
ing
B
12)GC
OR
E3_P
WR
GD
(PM
-mo
del)
Sheet 8
10) P1.5V
FD
S6680A
8) CH
P3_S
LP
S5#/4#/3#
110ms D
elay
10) P1.05V
(IGF
X_C
OR
E)
BC
P69
CK
-505
4
16
Sheet 10-12
15
6
INTVRMEN
ISL
6227
10-1) P1.8V
12) P1.5
6) ME
M1_V
RE
F
Ho
st / ME
Bo
ot
A
GM
CH
PW
RO
K
(SL
PS
4* = S4_S
TA
TE
*) > (SL
PM
* = SL
PS
3*)
2
VR
M
5) KB
C3_S
US
PW
R
6) P3.3V
_AU
X
CH
P3_R
TC
RS
T#
VR
MP
WR
GD
6) P1.8V
_AU
X
2) VDC
10) P5.0V
Marvell
14
11-1) GF
X_C
OR
E
10-1) P1.2V
6) P5.0V
_AU
X
7) KB
C3_R
SM
RS
T#
4) POWER_SW*
19) PL
T3_R
ST
*
5
2) VD
C
DD
R2 P
OW
ER
Mem
ory
10-1) ICH
_CO
RE
(P1.05V
)
PR
TC
_BA
T
Sheet 50
6-1) P1.2V
_LA
N
2) VD
C
EXCEPT AS AUTHORIZED BY SAMSUNG.
PO
WE
R
Sheet 40
10-1) P3.3V
S/W
9-1) KB
C3_P
WR
ON
_INV
#
DD
R3
6) P3.3V_AUX
19) PL
T3_R
ST
*
10) P1.5V
8) KBC3_SUSPWR
10-2) 0.9V
P3.3V
_MIC
OM
MA
X 8734
Battery
Devices
PC
I
RT
C12) P1.05V
_M
Sheet 40
11) KB
C3_P
WR
ON
Battery
AC
_DC
/ Battery
3
PM
-mo
del o
nly
-
8-7
- -
- This Document can not be used without Samsung's authorization
-
8. Block Diagram and Schematic
Samsung
Confidential
Samsung
Confidential
Samsung
Confidential
SR
P S
heet Num
ber: 7 of 73
CLK
0_HO
ST_G
MC
H/G
MC
H*
100 MH
z (SR
C4)
HD
24 MH
z
CP
U
Main P
LL
48MH
z PLL
SS
C
Need to be updated!!
A
SA
MS
UN
G
D
4
CLK
1_PE
G/P
EG
*
CLK
1_MIN
I2PC
IE/P
CIE
*
1
SP
I3_CLK
HP
LL
DP
LLA
DP
LLB
CLK
1_MC
LK3/3#
CLK
1_MC
LK4/4#
CLK
1_MC
LK0/0#
1
CLK
1_MC
LK1/1#
US
BP
LL
32.768 KH
z
Cantiga
3
2
EX
P3_C
LKR
EQ
*
EXCEPT AS AUTHORIZED BY SAMSUNG.
B
PC
IE LA
N(M
arvell)C
LK3_U
SB
48
CLK
1_SA
TA/S
ATA
*
CLK
3_ICH
14
CH
P3_S
ATA
CLK
RE
Q*
33 MH
z
200 MH
z
33 MH
z
CLK
0_HO
ST_C
PU
/CP
U*
CLK
3_PC
LKP
OR
T80
200 MH
z
33 MH
z
MC
H
CLK
3_PC
LKM
ICO
MK
BC
BS
EL
14.318 MH
z
14 MH
z
CK-505M (w/ CLKREQ* & SSDC)
D
xSLG8SP513r05)
100 MH
z
CLK
1_DR
EFC
LK/C
LK*
Buffer
MUX
FS
B
DM
I
CP
U_S
TP*
SS
(96/100) SE
L
P3.3V
10 MH
z
CLK
3_PW
RG
D*
Page 8
100 MH
z (SR
C 6,8,9)
MC
H3_C
LKR
EQ
*
MIN
I PC
IE
CL
OC
K D
ISTR
IBU
TIO
N
CA
RD
1 Rev. 0.1
CLK
1_MIN
IPC
IE/P
CIE
*
1067/800 MH
z
MIN
3_CLK
RE
Q*
17.86 MH
z
PC
IE P
LL
MP
LL
ICH
9-M
SA
TAP
LL
PC
IEP
LL
PC
I Express G
fx100 M
Hz (S
RC
0)
OS
C
C
HD
Audio
B
MD
C
A
MIN
I PC
IE
SAMSUNG ELECTRONICS COS PROPERTY.
CA
RD
2
3
533/400 MH
z
ELE
CTR
ON
ICS
533/400 MH
z
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
533/400 MH
z
4
100 MH
z (SR
C 2)
14.318 MH
z
CLK
3_PC
LKIC
H
CLK
1_DR
EFS
SC
/SS
C*
CLK
1_MC
H3G
PLL/3G
PLL*
AU
D3_B
CLK
SO
DIM
M #0
SO
DIM
M #1
533/400 MH
z
CLK
1_EX
PC
AR
D#
EX
PR
ES
SC
AR
D
OS
C
SS
C
PLL333 M
Hz
MUXMUX
PE
G
2
32.768 KH
z
SAM
SUN
G PR
OPR
IET
AR
Y
RTC
Clock
25 MH
z
1
FS(2:0)
ITP_E
N
PC
I_STP
*
100 MH
z (SR
C 6)
100 MH
z (SR
C 8)
SP
I
96 MH
z
CLK
1_PC
IEIC
H/IC
H*
100 MH
z (SR
C 10)
CLK
1_PC
IELO
M/LO
M*
100 MH
z (SR
C 9)
MD
C3_B
CLK
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
C
LOM
3_CLK
RE
Q*
PO
RT 80
48 MH
z
-
8-8
- -
- This Document can not be used without Samsung's authorization
-
8. Block Diagram and Schematic
Samsung
Confidential
Samsung
Confidential
Samsung
Confidential
SR
P S
heet Num
ber: 8 of 73 A
THIS DOCUMENT CONTAINS CONFIDENTIAL
1
C
3
EXCEPT AS AUTHORIZED BY SAMSUNG.
B
2
A
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
SAM
SUN
G PR
OPR
IET
AR
Y
SA
MS
UN
G
4
B
1
D
2
ELE
CTR
ON
ICS
SAMSUNG ELECTRONICS COS PROPERTY.
PROPRIETARY INFORMATION THAT IS
D
C
34
ME
M1_C
KE
3M
EM
1_CS
0#M
EM
1_CS
1#M
EM
1_CS
2#M
EM
1_CS
3#M
EM
1_OD
T0M
EM
1_OD
T1M
EM
1_OD
T2M
EM
1_OD
T3M
EM
1_VR
EF
SM
B3_C
LK
SMB3_DATA
ME
M1_A
RA
S#
ME
M1_A
WE
#M
EM
1_BB
S(0)
ME
M1_B
BS
(1)M
EM
1_BB
S(2)
ME
M1_B
CA
S#
ME
M1_B
DM
(7:0)
MEM1_BDQ(63:0)MEM1_BDQS#(7:0)MEM1_BDQS(7:0)
ME
M1_B
MA
(14:0)M
EM
1_BR
AS
#M
EM
1_BW
E#
ME
M1_C
KE
0M
EM
1_CK
E1
ME
M1_C
KE
2
CLK
1_MC
LK1#
CLK
1_MC
LK2
CLK
1_MC
LK2#
CLK
1_MC
LK3
CLK
1_MC
LK3#
MC
H3_E
XTTS
0#M
CH
3_EX
TTS1#
ME
M1_A
BS
(0)M
EM
1_AB
S(1)
ME
M1_A
BS
(2)M
EM
1_AC
AS
#M
EM
1_AD
M(7:0)
MEM1_ADQ(63:0)MEM1_ADQS#(7:0)MEM1_ADQS(7:0)
ME
M1_A
MA
(14:0)M
EM
1_OD
T0M
EM
1_OD
T1M
EM
1_OD
T2M
EM
1_OD
T3
ME
M1_V
RE
FP
EG
1_RX
N(15:0)
PE
G1_R
XP
(15:0)
PE
G1_TX
N(15:0)
PE
G1_TX
P(15:0)
PLT3_R
ST#
SO
DIM
M_D
DR
2
CLK
1_MC
LK0
CLK
1_MC
LK0#
CLK
1_MC
LK1
ME
M1_B
CA
S#
ME
M1_B
DM
(7:0)
MEM1_BDQ(63:0)MEM1_BDQS#(7:0)MEM1_BDQS(7:0)
ME
M1_B
MA
(14:0)M
EM
1_BR
AS
#M
EM
1_BW
E#
ME
M1_C
KE
0M
EM
1_CK
E1
ME
M1_C
KE
2M
EM
1_CK
E3
ME
M1_C
S0#
ME
M1_C
S1#
ME
M1_C
S2#
ME
M1_C
S3#
MCH1_HVREFMCH1_HXSWING
MC
H3_C
LKR
EQ
#
MC
H3_E
XTTS
0#M
CH
3_EX
TTS1#
MC
H3_IC
HS
YN
C#
ME
M1_A
BS
(2:0)M
EM
1_AC
AS
#M
EM
1_AD
M(7:0)
MEM1_ADQ(63:0)MEM1_ADQS#(7:0)MEM1_ADQS(7:0)
ME
M1_A
MA
(14:0)M
EM
1_AR
AS
#M
EM
1_AW
E#
ME
M1_B
BS
(2:0)
DM
I1_RX
N_1
DM
I1_RX
N_2
DM
I1_RX
N_3
DM
I1_RX
P_0
DM
I1_RX
P_1
DM
I1_RX
P_2
DM
I1_RX
P_3
DM
I1_TXN
_0D
MI1_TX
N_1
DM
I1_TXN
_2D
MI1_TX
N_3
DM
I1_TXP
_0D
MI1_TX
P_1
DM
I1_TXP
_2D
MI1_TX
P_3
KB
C3_P
WR
GD
CPU1_DSTBN3#CPU1_DSTBP0#CPU1_DSTBP1#CPU1_DSTBP2#CPU1_DSTBP3#
CPU1_HIT#CPU1_HITM#
CP
U1_LO
CK
#
CPU1_REQ#(4:0)
CP
U1_R
S0#
CP
U1_R
S1#
CP
U1_R
S2#
CP
U1_S
LP#
CP
U1_TH
RM
TRIP
#C
PU
1_TRD
Y#
DM
I1_RX
N_0
CPU1_BSEL1CPU1_BSEL2
CP
U1_C
PU
RS
T#
CPU1_D#(63:0)CPU1_DBI0#CPU1_DBI1#CPU1_DBI2#CPU1_DBI3#
CPU1_DBSY#
CP
U1_D
EFE
R#
CP
U1_D
PR
STP
#
CP
U1_D
PW
R#
CPU1_DRDY#CPU1_DSTBN0#CPU1_DSTBN1#CPU1_DSTBN2#
CLK
1_MC
LK0
CLK
1_MC
LK0#
CLK
1_MC
LK1
CLK
1_MC
LK1#
CLK
1_MC
LK2
CLK
1_MC
LK2#
CLK
1_MC
LK3
CLK
1_MC
LK3#
CPU1_A#(35:3)CPU1_ADS#
CPU1_ADSTB0#CPU1_ADSTB1#
CPU1_BNR#
CP
U1_B
PR
I#
CPU1_BREQ#CPU1_BSEL0
LOM
3_CLK
RE
Q#
MC
H3_C
LKR
EQ
#M
IN3_C
LKR
EQ
#S
MB
3_CLK
SMB3_DATA
MC
H_C
AN
TIGA
_GM
_DD
R2
CHP3_CL_CLK_0CHP3_CL_DATA_0
CH
P3_C
L_RS
T_0#C
HP
3_DP
RS
LPV
RC
HP
3_PM
_SY
NC
#C
LK0_H
CLK
1C
LK0_H
CLK
1#C
LK1_M
CH
3GP
LLC
LK1_M
CH
3GP
LL#
CLK
1_PE
G#
CLK
1_SA
TAC
LK1_S
ATA
#C
LK3_D
BG
LPC
CLK
3_FM48
CLK
3_GFX
_27MC
LK3_G
FX_27M
_SS
CLK
3_ICH
14C
LK3_P
CLK
ICH
CLK
3_PC
LKM
ICO
M
CLK
3_PW
RG
D
CLK3_USB48
CP
U1_B
SE
L0C
PU
1_BS
EL1
CP
U1_B
SE
L2E
XP
3_CLK
RE
Q#
CH
P3_S
ATA
CLK
RE
Q#
CLK
0_HC
LK0
CLK
0_HC
LK0#
CLK
0_HC
LK1
CLK
0_HC
LK1#
CLK
1_EX
PC
AR
DC
LK1_E
XP
CA
RD
#C
LK1_M
CH
3GP
LLC
LK1_M
CH
3GP
LL#C
LK1_M
INIP
CIE
CLK
1_MIN
IPC
IE#
CLK
1_PC
IEIC
HC
LK1_P
CIE
ICH
#C
LK1_P
CIE
LOM
CLK
1_PC
IELO
M#
CLK
1_PE
G
CPU3_THRMTRIP#FAN3_FDBACK#
FAN5_VDD
GFX
3_THE
RM
#
GFX3_THERMDNGFX3_THERMDP
KB
C3_P
WR
GD
KBC3_THERM_SMCLKKBC3_THERM_SMDATA
THM
3_ALE
RT#
THM
3_STP
#
CK
_Clock_505M
CH
P3_C
PU
STP
#C
HP
3_PC
ISTP
#
CPU1_TDI
CP
U1_TH
RM
TRIP
#
CPU1_TMS
CP
U1_TR
DY
#
CPU1_TRST#
CP
U1_V
CC
SE
NS
EC
PU
1_VID
(6:0)C
PU
1_VS
SS
EN
SE
CP
U2_TH
ER
MD
AC
PU
2_THE
RM
DC
ITP3_D
BR
RE
SE
T#
Thermal_S
ensor_SM
SC
_Em
c2102
CP
U1_TH
RM
TRIP
#
CPU2_THERMDACPU2_THERMDC
CPU1_HITM#
CP
U1_IG
NN
E#
CP
U1_IN
IT#C
PU
1_INTR
CPU1_LOCK#
CP
U1_N
MI
CP
U1_P
SI#
CP
U1_P
WR
GD
CP
U
CPU1_REQ#(4:0)
CP
U1_R
S0#
CP
U1_R
S1#
CP
U1_R
S2#
CP
U1_S
LP#
CP
U1_S
MI#
CP
U1_S
TPC
LK#
CPU1_TCK
CPU1_DBSY#
CP
U1_D
EFE
R#
CP
U1_D
PR
STP
#C
PU
1_DP
SLP
#C
PU
1_DP
WR
#
CPU1_DRDY#CPU1_DSTBN0#CPU1_DSTBN1#CPU1_DSTBN2#CPU1_DSTBN3#CPU1_DSTBP0#CPU1_DSTBP1#CPU1_DSTBP2#CPU1_DSTBP3#
CP
U1_FE
RR
#
CPU1_HIT#
CPU1_ADSTB1#CPU1_BNR#
CP
U1_B
PR
I#
CPU1_BREQ#
CP
U1_B
SE
L0C
PU
1_BS
EL1
CP
U1_B
SE
L2
CP
U1_C
PU
RS
T#
CPU1_D#(15:0)CPU1_D#(31:16)CPU1_D#(47:32)CPU1_D#(63:48)
CPU1_DBI0#CPU1_DBI1#CPU1_DBI2#CPU1_DBI3#
CLK
3_GFX
_27MC
LK3_G
FX_27M
_SS
PE
G1_R
XN
(15:0)P
EG
1_RX
P(15:0)
PE
G1_TX
N(15:0)
PE
G1_TX
P(15:0)
GFX3_THERMDNGFX3_THERMDP
GFX
3_THE
RM
#
CP
U_P
enryn_MV
_SV
CLK
0_HC
LK0
CLK
0_HC
LK0#
CPU1_A#(16:3)CPU1_A#(35:17)
CP
U1_A
20M#
CPU1_ADS#CPU1_ADSTB0#
ME
M1_C
KE
0M
EM
1_CK
E1
ME
M1_C
KE
2M
EM
1_CK
E3
ME
M1_C
S0#
ME
M1_C
S1#
ME
M1_C
S2#
ME
M1_C
S3#
ME
M1_O
DT0
ME
M1_O
DT1
ME
M1_O
DT2
ME
M1_O
DT3
ME
M1_V
RE
FS
MB
3_CLK
SMB3_DATA
CLK
1_PE
GC
LK1_P
EG
#
ME
M1_A
BS
(1)M
EM
1_AB
S(2)
ME
M1_A
CA
S#
ME
M1_A
DM
(7:0)
MEM1_ADQ(63:0)MEM1_ADQS#(7:0)MEM1_ADQS(7:0)
ME
M1_A
MA
(14:0)M
EM
1_AR
AS
#M
EM
1_AW
E#
ME
M1_B
BS
(0)M
EM
1_BB
S(1)
ME
M1_B
BS
(2)M
EM
1_BC
AS
#M
EM
1_BD
M(7:0)
MEM1_BDQ(63:0)MEM1_BDQS#(7:0)MEM1_BDQS(7:0)
ME
M1_B
MA
(14:0)M
EM
1_BR
AS
#M
EM
1_BW
E#
CPU3_THRMTRIP#FAN3_FDBACK#FAN5_VDD
KB
C3_P
WR
GD
KBC3_THERM_SMCLKKBC3_THERM_SMDATA
THM
3_ALE
RT#
THM
3_STP
#
CLK
1_MC
LK0
CLK
1_MC
LK0#
CLK
1_MC
LK1
CLK
1_MC
LK1#
CLK
1_MC
LK2
CLK
1_MC
LK2#
CLK
1_MC
LK3
CLK
1_MC
LK3#
MC
H3_E
XTTS
0#M
CH
3_EX
TTS1#
ME
M1_A
BS
(0)
CP
U1_IG
NN
E#
CP
U1_IN
IT#C
PU
1_INTR
CPU1_LOCK#
CP
U1_N
MI
CP
U1_P
SI#
CP
U1_P
WR
GD
CP
U
CPU1_REQ#(4:0)
CP
U1_R
S0#
CP
U1_R
S1#
CP
U1_R
S2#
CP
U1_S
LP#
CP
U1_S
MI#
CP
U1_S
TPC
LK#
CPU1_TCKCPU1_TDI
CP
U1_TH
RM
TRIP
#
CPU1_TMS
CP
U1_TR
DY
#
CPU1_TRST#
CP
U1_V
CC
SE
NS
EC
PU
1_VID
(6:0)C
PU
1_VS
SS
EN
SE
CP
U2_TH
ER
MD
AC
PU
2_THE
RM
DC
ITP3_D
BR
RE
SE
T#
CP
U1_TH
RM
TRIP
#
CPU2_THERMDACPU2_THERMDC
CP
U1_D
EFE
R#
CP
U1_D
PR
STP
#C
PU
1_DP
SLP
#C
PU
1_DP
WR
#
CPU1_DRDY#CPU1_DSTBN0#CPU1_DSTBN1#CPU1_DSTBN2#CPU1_DSTBN3#CPU1_DSTBP0#CPU1_DSTBP1#CPU1_DSTBP2#CPU1_DSTBP3#
CP
U1_FE
RR
#
CPU1_HIT#CPU1_HITM#
CLK
0_HC
LK0#
CPU1_A#(16:3)CPU1_A#(35:17)
CP
U1_A
20M#
CPU1_ADS#CPU1_ADSTB0#CPU1_ADSTB1#CPU1_BNR#
CP
U1_B
PR
I#
CPU1_BREQ#
CP
U1_B
SE
L0C
PU
1_BS
EL1
CP
U1_B
SE
L2
CP
U1_C
PU
RS
T#
CPU1_D#(15:0)CPU1_D#(31:16)CPU1_D#(47:32)CPU1_D#(63:48)CPU1_DBI0#CPU1_DBI1#CPU1_DBI2#CPU1_DBI3#CPU1_DBSY#
CLK
1_SA
TA#
CLK
3_DB
GLP
CC
LK3_FM
48
CLK
3_ICH
14C
LK3_P
CLK
ICH
CLK
3_PC
LKM
ICO
M
CLK
3_PW
RG
D
CLK3_USB48
CP
U1_B
SE
L0C
PU
1_BS
EL1
CP
U1_B
SE
L2E
XP
3_CLK
RE
Q#
LOM
3_CLK
RE
Q#
MC
H3_C
LKR
EQ
#M
IN3_C
LKR
EQ
#S
MB
3_CLK
SMB3_DATA
CLK
0_HC
LK0
CLK
1_EX
PC
AR
DC
LK1_E
XP
CA
RD
#C
LK1_M
CH
3GP
LLC
LK1_M
CH
3GP
LL#C
LK1_M
INIP
CIE
CLK
1_MIN
IPC
IE#
CLK
1_PC
IEIC
HC
LK1_P
CIE
ICH
#C
LK1_P
CIE
LOM
CLK
1_PC
IELO
M#
CLK
1_SA
TA
ME
M1_B
DM
(7:0)
MEM1_BDQ(63:0)MEM1_BDQS#(7:0)MEM1_BDQS(7:0)
ME
M1_B
MA
(14:0)M
EM
1_BR
AS
#M
EM
1_BW
E#
ME
M1_C
KE
0M
EM
1_CK
E1
ME
M1_C
KE
2M
EM
1_CK
E3
ME
M1_C
S0#
ME
M1_C
S1#
ME
M1_C
S2#
ME
M1_C
S3#
ME
M1_O
DT0
ME
M1_O
DT1
ME
M1_O
DT2
ME
M1_O
DT3
ME
M1_V
RE
F
PLT3_R
ST#
CH
P3_C
PU
STP
#C
HP
3_PC
ISTP
#C
HP
3_SA
TAC
LKR
EQ
#
CLK
0_HC
LK0
CLK
0_HC
LK0#
CLK
0_HC
LK1
CLK
0_HC
LK1#
DM
I1_TXP
_0D
MI1_TX
P_1
DM
I1_TXP
_2D
MI1_TX
P_3
KB
C3_P
WR
GD
MCH1_HVREFMCH1_HXSWING
MC
H3_C
LKR
EQ
#
MC
H3_E
XTTS
0#M
CH
3_EX
TTS1#
MC
H3_IC
HS
YN
C#
ME
M1_A
BS
(2:0)M
EM
1_AC
AS
#M
EM
1_AD
M(7:0)
MEM1_ADQ(63:0)MEM1_ADQS#(7:0)MEM1_ADQS(7:0)
ME
M1_A
MA
(14:0)M
EM
1_AR
AS
#M
EM
1_AW
E#
ME
M1_B
BS
(2:0)M
EM
1_BC
AS
#
DM
I1_RX
N_1
DM
I1_RX
N_2
DM
I1_RX
N_3
DM
I1_RX
P_0
DM
I1_RX
P_1
DM
I1_RX
P_2
DM
I1_RX
P_3
DM
I1_TXN
_0D
MI1_TX
N_1
DM
I1_TXN
_2D
MI1_TX
N_3
CPU1_BSEL2
CP
U1_C
PU
RS
T#CPU1_D#(63:0)CPU1_DBI0#CPU1_DBI1#CPU1_DBI2#CPU1_DBI3#CPU1_DBSY#
CP
U1_D
EFE
R#
CP
U1_D
PR
STP
#
CP
U1_D
PW
R#
CPU1_DRDY#CPU1_DSTBN0#CPU1_DSTBN1#CPU1_DSTBN2#CPU1_DSTBN3#CPU1_DSTBP0#CPU1_DSTBP1#CPU1_DSTBP2#CPU1_DSTBP3#CPU1_HIT#CPU1_HITM#
CP
U1_LO
CK
#
CPU1_REQ#(4:0)
CP
U1_R
S0#
CP
U1_R
S1#
CP
U1_R
S2#
CP
U1_S
LP#
CP
U1_TH
RM
TRIP
#C
PU
1_TRD
Y#
DM
I1_RX
N_0
CHP3_CL_CLK_0CHP3_CL_DATA_0
CH
P3_C
L_RS
T_0#C
HP
3_DP
RS
LPV
RC
HP
3_PM
_SY
NC
#C
LK0_H
CLK
1C
LK0_H
CLK
1#C
LK1_M
CH
3GP
LLC
LK1_M
CH
3GP
LL#
CLK
1_MC
LK0
CLK
1_MC
LK0#
CLK
1_MC
LK1
CLK
1_MC
LK1#
CLK
1_MC
LK2
CLK
1_MC
LK2#
CLK
1_MC
LK3
CLK
1_MC
LK3#
CPU1_A#(35:3)CPU1_ADS#CPU1_ADSTB0#CPU1_ADSTB1#CPU1_BNR#
CP
U1_B
PR
I#
CPU1_BREQ#CPU1_BSEL0CPU1_BSEL1
-
8-9
- -
- This Document can not be used without Samsung's authorization
-
8. Block Diagram and Schematic
Samsung
Confidential
Samsung
Confidential
Samsung
Confidential
SR
P S
heet Num
ber: 9 of 73
SA
MS
UN
GE
LEC
TRO
NIC
S
A
BB
CC
DD
44
33
22
11
SAM
SUN
G PR
OPR
IET
AR
YPROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS COS PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
THIS DOCUMENT CONTAINS CONFIDENTIAL
EXCEPT AS AUTHORIZED BY SAMSUNG.
A
USB3_P6+USB3_P6-USB3_P8+USB3_P8-
VR
M3_C
PU
_PW
RG
D
Bluetooth_IF_C
onn
US
B3_P
5+U
SB
3_P5-
SP
I3_CS
0#
SPI3_MISOSPI3_MOSI
THM
3_ALE
RT#
USB3_P0+USB3_P0-
USB3_P10+USB3_P10-USB3_P2+USB3_P2-USB3_P3+USB3_P3-USB3_P4+USB3_P4-USB3_P5+USB3_P5-
PE
X1_M
INITX
P1
PEX3_WAKE#
PLT3_R
ST#
PLT3_RST_ORG#
SA
T1_RX
N0
SA
T1_RX
N1
SA
T1_RX
P0
SA
T1_RX
P1
SA
T1_TXN
0S
AT1_TX
N1
SA
T1_TXP
0S
AT1_TX
P1
SMB3_ALERT#SMB3_CLK
SMB3_DATA
SP
I3_CLK
KB
C3_W
AK
ES
CI#
LPC3_LAD(3:0)
LPC
3_LFRA
ME
#
MC
H3_IC
HS
YN
C#
PCI3_CLKRUN#
PE
X1_E
XP
CA
RD
RX
N3
PE
X1_E
XP
CA
RD
RX
P3
PE
X1_E
XP
CA
RD
TXN
3P
EX
1_EX
PC
AR
DTX
P3
PE
X1_G
LAN
_RX
N4
PE
X1_G
LAN
_RX
P4
PE
X1_G
LAN
_TXN
4P
EX
1_GLA
N_TX
P4
PE
X1_M
INIR
XN
1P
EX
1_MIN
IRX
P1
PE
X1_M
INITX
N1
HD
A3_H
DM
I_SD
I2
HD
A3_H
DM
I_SD
OH
DA
3_HD
MI_S
YN
CH
DA
3_MD
C_B
CLK
HD
A3_M
DC
_RS
T#
HD
A3_M
DC
_SD
I1
HD
A3_M
DC
_SD
OH
DA
3_MD
C_S
YN
C
ITP3_D
BR
RE
SE
T#
KBC3_A20GKBC3_CPURST#
KB
C3_E
XTS
MI#
KB
C3_P
WR
BTN
#K
BC
3_PW
RG
DK
BC
3_RS
MR
ST#
KB
C3_R
UN
SC
I#
DM
I1_RX
P_3
DM
I1_TXN
_0D
MI1_TX
N_1
DM
I1_TXN
_2D
MI1_TX
N_3
DM
I1_TXP
_0D
MI1_TX
P_1
DM
I1_TXP
_2D
MI1_TX
P_3
HD
A3_A
UD
_BC
LKH
DA
3_AU
D_R
ST#
HD
A3_A
UD
_SD
I0
HD
A3_A
UD
_SD
OH
DA
3_AU
D_S
YN
CH
DA
3_HD
MI_B
CLK
HD
A3_H
DM
I_RS
T#
CP
U1_FE
RR
#
CP
U1_IG
NN
E#
CP
U1_IN
IT#C
PU
1_INTR
CP
U1_N
MI
CP
U1_P
WR
GD
CP
UC
PU
1_SM
I#C
PU
1_STP
CLK
#
CP
U1_TH
RM
TRIP
#D
MI1_R
XN
_0D
MI1_R
XN
_1D
MI1_R
XN
_2D
MI1_R
XN
_3D
MI1_R
XP
_0D
MI1_R
XP
_1D
MI1_R
XP
_2
CHP3_SERIRQ
CH
P3_S
LPS
3#C
HP
3_SLP
S4#
CH
P3_S
LPS
5#C
HP
3_SU
SS
TAT#
CLK
1_PC
IEIC
HC
LK1_P
CIE
ICH
#C
LK1_S
ATA
CLK
1_SA
TA#
CLK
3_ICH
14C
LK3_P
CLK
ICH
CLK
3_PW
RG
D
CLK
3_US
B48
CP
U1_A
20M#
CP
U1_D
PR
STP
#C
PU
1_DP
SLP
#
CHP3_BIOSWP#CHP3_BIOS_CRI#CHP3_CL_CLK_0
CHP3_CL_DATA_0CHP3_CL_RST_0#
CH
P3_C
PU
STP
#C
HP
3_DP
RS
LPV
R
CHP3_GPIO18CHP3_GPIO20
CHP3_INTRUDER#CHP3_ME_RTCRST#
CH
P3_P
CIS
TP#
CH
P3_P
M_S
YN
C#
CHP3_RTCRST#
CH
P3_S
ATA
CLK
RE
Q#
CH
P3_S
ATA
LED
#
HD
D_IF_C
onn
SA
T1_RX
N0
SA
T1_RX
P0
SA
T1_TXN
0S
AT1_TX
P0
OD
D_IF_C
onn
SA
T1_RX
N1
SA
T1_RX
P1
SA
T1_TXN
1S
AT1_TX
P1
ICH
_9M_B
AU
D3_S
PK
R
US
B3_P
8-
LED
_Sw
itch
CH
P3_S
ATA
LED
#K
BC
3_CA
PS
LED
#K
BC
3_LED
_AC
IN#
KB
C3_LE
D_C
HA
RG
E#
KB
C3_LE
D_P
OW
ER
#K
BC
3_NU
MLE
D#
KB
C3_S
CLE
D#
WLO
N_LE
D#
LID_S
witch
LID3_S
WITC
H#
US
B3_P
2+U
SB
3_P2-
US
B_2P
ort
KB
C3_U
SB
PW
RO
N#
US
B3_P
0+U
SB
3_P0-
US
B3_P
6+U
SB
3_P6-
MIO
_Sw
itch
KB
C3_P
WR
SW
#
Cam
era_IF_Conn
US
B3_P
8+
KB
D_IF_C
onn
KB
C5_K
SI(0:7)
KB
C5_K
SO
(0:15)
Other_D
ebug_80
CLK
3_DB
GLP
C
LPC3_LAD(0)LPC3_LAD(1)LPC3_LAD(2)LPC3_LAD(3)
LPC3_LFRAME#
PLT3_R
ST#
US
B_1P
ort
KB
C3_U
SB
PW
RO
N#
LPC3_LAD(0:3)
LPC
3_LFRA
ME
#
PCI3_CLKRUN#
PE
X3_W
AK
E#
PLT3_R
ST#
THM
3_ALE
RT#
THM
3_STP
#V
RM
3_CP
U_P
WR
GD
Touchpad_IF_Conn
KB
C5_TC
LKK
BC
5_TDA
TAT_L_B
UTTO
N#
T_R_B
UTTO
N#
KB
C3_S
CLE
D#
KBC3_SMCLK#KBC3_SMDATA#
KB
C3_S
PK
MU
TEK
BC
3_SU
SP
WR
KB
C3_TH
ER
M_S
MC
LK
KBC3_THERM_SMDATAKB
C3_U
SB
PW
RO
N#
KB
C3_V
RO
NK
BC
3_WA
KE
SC
I#
KB
C5_K
SI(0:7)
KB
C5_K
SO
(0:7)K
BC
5_KS
O(8:15)
KBC5_TCLKKBC5_TDATALID
3_SW
ITCH
#
KBC3_CHKPWRSW#
KB
C3_C
PU
RS
T#K
BC
3_EX
TSM
I#K
BC
3_LED
_AC
IN#
KB
C3_LE
D_C
HA
RG
E#
KB
C3_LE
D_P
OW
ER
#K
BC
3_NU
MLE
D#
KB
C3_P
RE
CH
GK
BC
3_PW
RB
TN#
KB
C3_P
WR
GD
KB
C3_P
WR
ON
KB
C3_P
WR
SW
#
KB
C3_R
FOFF#
KB
C3_R
SM
RS
T#
KBC3_RST#
KB
C3_R
UN
SC
I#
MIC
OM
_Renesas2110_100p
AD
T3_SE
L#B
AT3_D
ETE
CT#
CH
P3_S
ER
IRQ
CH
P3_S
LPS
3#C
HP
3_SLP
S4#
CH
P3_S
LPS
5#C
HP
3_SU
SS
TAT#
CLK
3_PC
LKM
ICO
M
KB
C3_A
20GK
BC
3_BK
LTON
KBC3_BLCKPWRSW#
KB
C3_C
AP
SLE
D#
KB
C3_C
HG
4.2VK
BC
3_CH
GE
N
PLT3_R
ST#
US
B3_P
5+U
SB
3_P5-
AD
T3_SE
L#
KB
C3_P
RE
CH
G
KBC3_SMCLK#KBC3_SMDATA#
KB
C3_U
SB
PW
RO
N#
KB
C3_U
SB
PW
RO
N#
KB
C3_U
SB
PW
RO
N#
KB
C3_C
HG
4.2V
SP
I_BIO
S_R
OM
CH
P3_B
IOS
WP
#S
PI3_C
LKS
PI3_C
S0#
SP
I3_MIS
O
SP
I3_MO
SI
SA
T1_RX
N1
SA
T1_RX
P1
SA
T1_TXN
1S
AT1_TX
P1
US
B3_P
8+U
SB
3_P8-
T_R_B
UTTO
N#
T_L_BU
TTON
#K
BC
5_TDA
TAK
BC
5_TCLK
CH
P3_B
IOS
WP
#S
PI3_C
LKS
PI3_C
S0#
SP
I3_MIS
O
SP
I3_MO
SI
CLK
3_DB
GLP
C
LPC3_LAD(0)LPC3_LAD(1)LPC3_LAD(2)LPC3_LAD(3)LPC3_LFRAME#
KB
C3_S
US
PW
RK
BC
3_THE
RM
_SM
CLK
KBC3_THERM_SMDATA
KB
C3_V
RO
NK
BC
3_WA
KE
SC
I#
KB
C5_K
SI(0:7)
KB
C5_K
SO
(0:7)K
BC
5_KS
O(8:15)
KBC5_TCLKKBC5_TDATA
LID3_S
WITC
H#
LPC3_LAD(0:3)
LPC
3_LFRA
ME
#
PCI3_CLKRUN#
PE
X3_W
AK
E#
PLT3_R
ST#
THM
3_ALE
RT#
THM
3_STP
#V
RM
3_CP
U_P
WR
GD
CH
P3_S
ATA
LED
#K
BC
3_CA
PS
LED
#K
BC
3_LED
_AC
IN#
KB
C3_LE
D_C
HA
RG
E#
KB
C3_LE
D_P
OW
ER
#K
BC
3_NU
MLE
D#
KB
C3_S
CLE
D#
WLO
N_LE
D#
KB
C5_K
SI(0:7)
KB
C5_K
SO
(0:15)
LID3_S
WITC
H#
KB
C3_P
WR
SW
#
SA
T1_TXP
0
BA
T3_DE
TEC
T#C
HP
3_SE
RIR
Q
CH
P3_S
LPS
3#C
HP
3_SLP
S4#
CH
P3_S
LPS
5#C
HP
3_SU
SS
TAT#
CLK
3_PC
LKM
ICO
M
KB
C3_A
20GK
BC
3_BK
LTON
KBC3_BLCKPWRSW#
KB
C3_C
AP
SLE
D#
KB
C3_C
HG
EN
KBC3_CHKPWRSW#
KB
C3_C
PU
RS
T#K
BC
3_EX
TSM
I#K
BC
3_LED
_AC
IN#
KB
C3_LE
D_C
HA
RG
E#
KB
C3_LE
D_P
OW
ER
#K
BC
3_NU
MLE
D#
KB
C3_P
WR
BTN
#K
BC
3_PW
RG
DK
BC
3_PW
RO
N
KB
C3_P
WR
SW
#
KB
C3_R
FOFF#
KB
C3_R
SM
RS
T#
KBC3_RST#
KB
C3_R
UN
SC
I#K
BC
3_SC
LED
#K
BC
3_SP
KM
UTE
USB3_P3+USB3_P3-USB3_P4+USB3_P4-USB3_P5+USB3_P5-USB3_P6+USB3_P6-USB3_P8+USB3_P8-
VR
M3_C
PU
_PW
RG
D
US
B3_P
2+U
SB
3_P2-
US
B3_P
6-
SA
T1_RX
N0
SA
T1_RX
P0
SA
T1_TXN
0
PE
X1_M
INITX
P1
PEX3_WAKE#
PLT3_R
ST#
PLT3_RST_ORG#
SA
T1_RX
N0
SA
T1_RX
N1
SA
T1_RX
P0
SA
T1_RX
P1
SA
T1_TXN
0S
AT1_TX
N1
SA
T1_TXP
0S
AT1_TX
P1
SMB3_ALERT#SMB3_CLKSMB3_DATA
SP
I3_CLK
SP
I3_CS
0#
SPI3_MISOSPI3_MOSI
THM
3_ALE
RT#
USB3_P0+USB3_P0-USB3_P10+USB3_P10-USB3_P2+USB3_P2-
KB
C3_P
WR
BTN
#K
BC
3_PW
RG
DK
BC
3_RS
MR
ST#
KB
C3_R
UN
SC
I#
KB
C3_W
AK
ES
CI#
LPC3_LAD(3:0)
LPC
3_LFRA
ME
#
MC
H3_IC
HS
YN
C#
PCI3_CLKRUN#
PE
X1_E
XP
CA
RD
RX
N3
PE
X1_E
XP
CA
RD
RX
P3
PE
X1_E
XP
CA
RD
TXN
3P
EX
1_EX
PC
AR
DTX
P3
PE
X1_G
LAN
_RX
N4
PE
X1_G
LAN
_RX
P4
PE
X1_G
LAN
_TXN
4P
EX
1_GLA
N_TX
P4
PE
X1_M
INIR
XN
1P
EX
1_MIN
IRX
P1
PE
X1_M
INITX
N1
DM
I1_TXN
_2D
MI1_TX
N_3
DM
I1_TXP
_0D
MI1_TX
P_1
DM
I1_TXP
_2D
MI1_TX
P_3
HD
A3_A
UD
_BC
LKH
DA
3_AU
D_R
ST#
HD
A3_A
UD
_SD
I0
HD
A3_A
UD
_SD
OH
DA
3_AU
D_S
YN
CH
DA
3_HD
MI_B
CLK
HD
A3_H
DM
I_RS
T#
HD
A3_H
DM
I_SD
I2
HD
A3_H
DM
I_SD
OH
DA
3_HD
MI_S
YN
CH
DA
3_MD
C_B
CLK
HD
A3_M
DC
_RS
T#
HD
A3_M
DC
_SD
I1
HD
A3_M
DC
_SD
OH
DA
3_MD
C_S
YN
C
ITP3_D
BR
RE
SE
T#
KBC3_A20GKBC3_CPURST#
KB
C3_E
XTS
MI#
CLK
3_US
B48
CP
U1_A
20M#
CP
U1_D
PR
STP
#C
PU
1_DP
SLP
#
CP
U1_FE
RR
#
CP
U1_IG
NN
E#
CP
U1_IN
IT#C
PU
1_INTR
CP
U1_N
MI
CP
U1_P
WR
GD
CP
UC
PU
1_SM
I#C
PU
1_STP
CLK
#
CP
U1_TH
RM
TRIP
#D
MI1_R
XN
_0D
MI1_R
XN
_1D
MI1_R
XN
_2D
MI1_R
XN
_3D
MI1_R
XP
_0D
MI1_R
XP
_1D
MI1_R
XP
_2D
MI1_R
XP
_3
DM
I1_TXN
_0D
MI1_TX
N_1
US
B3_P
0+U
SB
3_P0-
US
B3_P
6+
AU
D3_S
PK
R
CHP3_BIOSWP#CHP3_BIOS_CRI#CHP3_CL_CLK_0CHP3_CL_DATA_0CHP3_CL_RST_0#
CH
P3_C
PU
STP
#C
HP
3_DP
RS
LPV
R
CHP3_GPIO18CHP3_GPIO20CHP3_INTRUDER#CHP3_ME_RTCRST#
CH
P3_P
CIS
TP#
CH
P3_P
M_S
YN
C#
CHP3_RTCRST#
CH
P3_S
ATA
CLK
RE
Q#
CH
P3_S
ATA
LED
#
CHP3_SERIRQ
CH
P3_S
LPS
3#C
HP
3_SLP
S4#
CH
P3_S
LPS
5#C
HP
3_SU
SS
TAT#
CLK
1_PC
IEIC
HC
LK1_P
CIE
ICH
#C
LK1_S
ATA
CLK
1_SA
TA#
CLK
3_ICH
14C
LK3_P
CLK
ICH
CLK
3_PW
RG
D
-
8-10
- -
- This Document can not be used without Samsung's authorization
-
8. Block Diagram and Schematic
Samsung
Confidential
Samsung
Confidential
Samsung
Confidential
SR
P S
heet Num
ber: 10 of 73
SA
MS
UN
GE
LEC
TRO
NIC
S
A
BB
A CC
DD
44
311
3
22
SAM
SUN
G PR
OPR
IET
AR
YTHIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS COS PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
WD
QS
A(4)
WD
QS
A(5)
WD
QS
A(6)
WD
QS
A(7)
WE
A#
MC
LKA
1M
CLK
A1#
OD
TR
AS
A#
RD
QS
A(0)
RD
QS
A(1)
RD
QS
A(2)
RD
QS
A(3)
RD
QS
A(4)
RD
QS
A(5)
RD
QS
A(6)
RD
QS
A(7)
WD
QS
A(0)
WD
QS
A(1)
WD
QS
A(2)
WD
QS
A(3)
DQ
MA
(0)D
QM
A(1)
DQ
MA
(2)D
QM
A(3)
DQ
MA
(4)D
QM
A(5)
DQ
MA
(6)D
QM
A(7)
MA
A(12:0)
MA
B(2)
MA
B(3)
MA
B(4)
MA
B(5)
MC
KE
AM
CLK
A0
MC
LKA
0#
PE
X1_M
INITX
N1
PE
X1_M
INITX
P1
PE
X3_W
AK
E#
PLT3_R
ST#
WLO
N_LE
D#
Graphics_M
emory_N
vidia
BA
A0
BA
A1
BA
A2
CA
SA
#C
SA
0#D
QA
(15:0)D
QA
(31:16)D
QA
(47:32)D
QA
(63:48)
HD
A3_A
UD
_SD
OH
DA
3_AU
D_S
YN
CK
BC
3_SP
KM
UTE
SPK5_L+SPK5_L-
SPK5_R+SPK5_R-
PC
IE_M
inicard_Slot
CLK
1_MIN
IPC
IEC
LK1_M
INIP
CIE
#K
BC
3_RFO
FF#
MIN
3_CLK
RE
Q#
PE
X1_M
INIR
XN
1P
EX
1_MIN
IRX
P1
AUD5_HP_O_RIGHTAUD5_LINE_O_LEFT
AUD5_LINE_O_RIGHTAUD5_MIC1_LEFT
AUD5_MIC1_RIGHTAUD5_MIC1_VREF_LEFT
AUD5_MIC1_VREF_RIGHTAUD5_MIC2_LEFT
AUD5_MIC2_RIGHTAUD5_MIC2_VREF
AUD5_SENS_AAUD5_SENS_HP#
AUD5_SENS_MIC#
HD
A3_A
UD
_BC
LKH
DA
3_AU
D_R
ST#
HD
A3_A
UD
_SD
I0
PE
G3_TX
1P_H
DM
IP
EG
3_TX2N
_HD
MI
PE
G3_TX
2P_H
DM
IP
EG
3_TXC
N_H
DM
IP
EG
3_TXC
P_H
DM
I
PEG5_HDMI_CLK
PE
G5_H
DM
I_DA
TA
HD
A_C
odec_Alc262
AUD3_BEEPAUD3_GPIO0#AUD3_GPIO1#AUD3_SHDN#
AU
D3_S
PK
R
AUD5_HP_O_LEFT
LCD
1_BC
LK#
LCD1_BDATA0LCD1_BDATA0#
LCD1_BDATA1LCD1_BDATA1#
LCD1_BDATA2LCD1_BDATA2#LCD3_BKLTON
LCD
3_BR
ITLC
D3_E
DID
_CLK
LCD3_EDID_DATA
PE
G3_B
KLTE
N
PE
G3_H
PD
_HD
MI
PE
G3_LC
DV
DD
ON
PE
G3_TX
0N_H
DM
IP
EG
3_TX0P
_HD
MI
PE
G3_TX
1N_H
DM
I
CR
T3_VS
YN
C CRT5_DDCCLKCRT5_DDCDATA
CRT5_HSYNCCRT5_VSYNC
KB
C3_B
KLTO
NLC
D1_A
CLK
LCD
1_AC
LK#
LCD1_ADATA0LCD1_ADATA0#
LCD1_ADATA1LCD1_ADATA1#
LCD1_ADATA2LCD1_ADATA2#
LCD
1_BC
LK
WE
A#
HD
A_M
odem
HD
A3_M
DC
_BC
LKH
DA
3_MD
C_R
ST#
HD
A3_M
DC
_SD
I1
HD
A3_M
DC
_SD
OH
DA
3_MD
C_S
YN
C
Graphics_IF_C
RT
CR
T3_BLU
EC
RT3_D
DC
CLK
CRT3_DDCDATA
CR
T3_GR
EE
NC
RT3_H
SY
NC
CR
T3_RE
D
PE
G3_H
PD
_HD
MI
PE
G3_LC
DV
DD
ON
PE
G3_TX
0N_H
DM
IP
EG
3_TX0P
_HD
MI
PE
G3_TX
1N_H
DM
IP
EG
3_TX1P
_HD
MI
PE
G3_TX
2N_H
DM
IP
EG
3_TX2P
_HD
MI
PE
G3_TX
CN
_HD
MI
PE
G3_TX
CP
_HD
MI
PE
G5_H
DM
I_CLK
PEG5_HDMI_DATA
PLT3_R
ST#
RA
SA
#R
DQ
SA
(0:7)W
DQ
SA
(0:7)
MA
B(2)
MA
B(3)
MA
B(4)
MA
B(5)
MC
KE
AM
CLK
A0
MC
LKA
0#M
CLK
A1
MC
LKA
1#O
DT
PE
G1_R
XN
(15:0)P
EG
1_RX
P(15:0)
PE
G1_TX
N(15:0)
PE
G1_TX
P(15:0)
PE
G3_B
KLTE
N
LCD1_BDATA2#
LCD
3_BR
ITLC
D3_E
DID
_CLK
LCD3_EDID_DATA
MA
A(0)
MA
A(1)
MA
A(10)
MA
A(11)
MA
A(12)
MA
A(2)
MA
A(3)
MA
A(4)
MA
A(5)
MA
A(6)
MA
A(7)
MA
A(8)
MA
A(9)
HD
A3_H
DM
I_SY
NC
LCD
1_AC
LKLC
D1_A
CLK
#
LCD1_ADATA0LCD1_ADATA0#
LCD1_ADATA1LCD1_ADATA1#
LCD1_ADATA2LCD1_ADATA2#
LCD
1_BC
LKLC
D1_B
CLK
#LCD1_BDATA0
LCD1_BDATA0#LCD1_BDATA1
LCD1_BDATA1#LCD1_BDATA2
GFX3_I2CSDATAGFX3_ROMSCLK
GFX3_ROMSIGFX3_ROMSOGFX3_STRAP0GFX3_STRAP1GFX3_STRAP2
GFX
3_THE
RM
#G
FX3_TH
ER
MD
NG
FX3_TH
ER
MD
PG
FX3_V
OLTID
_0G
FX3_V
OLTID
_1
HD
A3_H
DM
I_BC
LKH
DA
3_HD
MI_R
ST#
HD
A3_H
DM
I_SD
I2
HD
A3_H
DM
I_SD
OC
RT3_D
DC
CLK
CRT3_DDCDATA
CR
T3_GR
EE
NC
RT3_H
SY
NC
CR
T3_RE
DC
RT3_V
SY
NC
CS
A0#
DQA(63:0)
DQ
MA
(7:0)
GFX3_HCLKGFX3_HDATA
GFX3_I2CBCLKGFX3_I2CBDATA
GFX3_I2CECLKGFX3_I2CEDATA
GFX3_I2CSCLK
LCD1_BDATA1LCD1_BDATA1#LCD1_BDATA2LCD1_BDATA2#
Gfx_E
xternal_Nvidia_N
b9x_64bit
BA
A0
BA
A1
BA
A2
CA
SA
#
CLK
1_PE
GC
LK1_P
EG
#C
LK3_G
FX_27M
CLK
3_GFX
_27M_S
SC
RT3_B
LUE
CR
T3_HS
YN
CC
RT3_G
RE
EN
CRT3_DDCDATA
CR
T3_DD
CC
LKC
RT3_B
LUE
CLK
3_GFX
_27M_S
SC
LK3_G
FX_27M
CLK
1_PE
G#
CLK
1_PE
G
CA
SA
#B
AA
2B
AA
1B
AA
0
LCD
1_BC
LKLC
D1_B
CLK
#LCD1_BDATA0LCD1_BDATA0#LCD1_BDATA1LCD1_BDATA1#LCD1_BDATA2LCD1_BDATA2#
LCD
1_BC
LKLC
D1_B
CLK
#
LCD1_BDATA0LCD1_BDATA0#
HD
A3_H
DM
I_SY
NC
HD
A3_H
DM
I_SD
O
HD
A3_H
DM
I_SD
I2
HD
A3_H
DM
I_RS
T#H
DA
3_HD
MI_B
CLK
GFX
3_VO
LTID_1
GFX
3_VO
LTID_0
GFX
3_THE
RM
DP
GFX
3_THE
RM
DN
GFX
3_THE
RM
#
GFX3_STRAP2GFX3_STRAP1GFX3_STRAP0GFX3_ROMSOGFX3_ROMSIGFX3_ROMSCLKGFX3_I2CSDATAGFX3_I2CSCLKGFX3_I2CEDATAGFX3_I2CECLKGFX3_I2CBDATAGFX3_I2CBCLKGFX3_HDATAGFX3_HCLK
DQ
MA
(7:0)
DQA(63:0)
CS
A0#
CR
T3_VS
YN
CC
RT3_R
ED
MA
A(11)
MA
A(10)
MA
A(1)
MA
A(0)
LCD3_EDID_DATA
LCD
3_ED
ID_C
LKLC
D3_B
RIT
LCD
1_AD
ATA
2#LC
D1_A
DA
TA2
LCD
1_AD
ATA
1#LC
D1_A
DA
TA1
LCD
1_AD
ATA
0#LC
D1_A
DA
TA0
LCD
1_AC
LK#
LCD
1_AC
LK
PE
G3_B
KLTE
N
PE
G1_TX
P(15:0)
PE
G1_TX
N(15:0)
PE
G1_R
XP
(15:0)P
EG
1_RX
N(15:0)
OD
TM
CLK
A1#
MC
LKA
1M
CLK
A0#
MC
LKA
0M
CK
EA
MA
B(5)
MA
B(4)
MA
B(3)
MA
B(2)
MA
A(9)
MA
A(8)
MA
A(7)
MA
A(6)
MA
A(5)
MA
A(4)
MA
A(3)
MA
A(2)
MA
A(12)
WD
QS
A(1)
WD
QS
A(2)
WD
QS
A(3)
WD
QS
A(4)
WD
QS
A(5)
WD
QS
A(6)
WD
QS
A(7)
WE
A#
WE
A#
WD
QS
A(0:7)
RD
QS
A(0:7)
RA
SA
#
PLT3_R
ST#
PEG5_HDMI_DATA
PE
G5_H
DM
I_CLK
PE
G3_TX
CP
_HD
MI
PE
G3_TX
CN
_HD
MI
PE
G3_TX
2P_H
DM
IP
EG
3_TX2N
_HD
MI
PE
G3_TX
1P_H
DM
IP
EG
3_TX1N
_HD
MI
PE
G3_TX
0P_H
DM
IP
EG
3_TX0N
_HD
MI
PE
G3_LC
DV
DD
ON
PE
G3_H
PD
_HD
MI
MC
KE
AM
CLK
A0
MC
LKA
0#M
CLK
A1
MC
LKA
1#O
DT
RA
SA
#R
DQ
SA
(0)R
DQ
SA
(1)R
DQ
SA
(2)R
DQ
SA
(3)R
DQ
SA
(4)R
DQ
SA
(5)R
DQ
SA
(6)R
DQ
SA
(7)W
DQ
SA
(0)
CS
A0#
DQ
A(15:0)
DQ
A(31:16)
DQ
A(47:32)
DQ
A(63:48)
DQ
MA
(0)D
QM
A(1)
DQ
MA
(2)D
QM
A(3)
DQ
MA
(4)D
QM
A(5)
DQ
MA
(6)D
QM
A(7)
MA
A(12:0)
MA
B(2)
MA
B(3)
MA
B(4)
MA
B(5)
SPK5_L-SPK5_R+SPK5_R-
CLK
1_MIN
IPC
IEC
LK1_M
INIP
CIE
#K
BC
3_RFO
FF#
MIN
3_CLK
RE
Q#
PE
X1_M
INIR
XN
1P
EX
1_MIN
IRX
P1
PE
X1_M
INITX
N1
PE
X1_M
INITX
P1
PE
X3_W
AK
E#
PLT3_R
ST#
WLO
N_LE
D#
PE
G3_B
KLTE
N
PE
G3_H
PD
_HD
MI
PE
G3_LC
DV
DD
ON
BA
A0
BA
A1
BA
A2
CA
SA
#
AU
D3_S
PK
R
AUD5_HP_O_LEFTAUD5_HP_O_RIGHTAUD5_LINE_O_LEFTAUD5_LINE_O_RIGHTAUD5_MIC1_LEFTAUD5_MIC1_RIGHTAUD5_MIC1_VREF_LEFTAUD5_MIC1_VREF_RIGHTAUD5_MIC2_LEFTAUD5_MIC2_RIGHTAUD5_MIC2_VREFAUD5_SENS_AAUD5_SENS_HP#AUD5_SENS_MIC#
HD
A3_A
UD
_BC
LKH
DA
3_AU
D_R
ST#
HD
A3_A
UD
_SD
I0
HD
A3_A
UD
_SD
OH
DA
3_AU
D_S
YN
CK
BC
3_SP
KM
UTE
SPK5_L+
PE
G3_TX
0P_H
DM
IP
EG
3_TX1N
_HD
MI
PE
G3_TX
1P_H
DM
IP
EG
3_TX2N
_HD
MI
PE
G3_TX
2P_H
DM
IP
EG
3_TXC
N_H
DM
IP
EG
3_TXC
P_H
DM
I
PEG5_HDMI_CLK
PE
G5_H
DM
I_DA
TA
HD
A3_M
DC
_BC
LKH
DA
3_MD
C_R
ST#
HD
A3_M
DC
_SD
I1
HD
A3_M
DC
_SD
OH
DA
3_MD
C_S
YN
C
AUD3_BEEPAUD3_GPIO0#AUD3_GPIO1#AUD3_SHDN#
CR
T3_BLU
EC
RT3_D
DC
CLK
CRT3_DDCDATA
CR
T3_GR
EE
NC
RT3_H
SY
NC
CR
T3_RE
DC
RT3_V
SY
NC
CRT5_DDCCLKCRT5_DDCDATACRT5_HSYNCCRT5_VSYNC
KB
C3_B
KLTO
N
LCD1_ACLKLCD1_ACLK#
LCD1_ADATA0LCD1_ADATA0#LCD1_ADATA1LCD1_ADATA1#LCD1_ADATA2LCD1_ADATA2#
LCD3_BKLTON
LCD
3_BR
ITLC
D3_E
DID
_CLK
LCD3_EDID_DATA
PE
G3_TX
0N_H
DM
I
-
8-11
- -
- This Document can not be used without Samsung's authorization
-
8. Block Diagram and Schematic
Samsung
Confidential
Samsung
Confidential
Samsung
Confidential
SR
P S
heet Num
ber: 11 of 73 C
DDB
44
33
22
11
SAM
SUN
G PR
OPR
IET
AR
YTHIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS COS PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
SA
MS
UN
GE
LEC
TRO
NIC
S
AA
B C
GC
OR
E3_P
WR
GD
GFX
3_VO
LTID_0
GFX
3_VO
LTID_1
KB
C3_P
WR
ON
P1.1V
_PW
RG
D
VC
CP
3_PW
RG
D
CP
U1_V
ID(3)
CP
U1_V
ID(4)
CP
U1_V
ID(5)
CP
U1_V
ID(6)
CP
U1_V
SS
SE
NS
EG
CO
RE
3_PW
RG
DK
BC
3_VR
ON
P1.1V
_PW
RG
D
VR
M3_C
PU
_PW
RG
D
VRM_ISEN1VRM_ISEN2
VRM_PRMVRM_VSUM
PW
R_G
fx_MV
_Ext
BAT3_SMDATA#
KB
C3_C
HG
4.2VK
BC
3_CH
GE
NK
BC
3_PR
EC
HG KBC3_SMCLK#
KBC3_SMDATA#VDC_SGATE
PW
R_C
PU
_MV
_ISL6262
CH
P3_D
PR
SLP
VR
CP
U1_D
PR
STP
#C
PU
1_PS
I#C
PU
1_VC
CS
EN
SE
CP
U1_V
ID(0)
CP
U1_V
ID(1)
CP
U1_V
ID(2)
PW
R_M
V_3V
_5V
AU
X_P
GK
BC
3_SU
SP
WR
PW
R_M
V_M
eMory
AU
X_P
GK
BC
3_SU
SP
WR
ME
M1_V
RE
F
PW
R_M
V_C
harger_ISL6256
AD
T3_SE
L#B
AT3_D
ETE
CT#
BAT3_SMCLK#
KB
C3_P
RE
CH
G
KBC3_SMCLK#KBC3_SMDATA#
KB
C3_P
WR
ON
_INV
#K
BC
3_SU
SP
WR
GC
OR
E3_P
WR
GD
KB
C3_P
WR
ON
VC
CP
3_PW
RG
D
GFX
3_VO
LTID_0
GFX
3_VO
LTID_1
GC
OR
E3_P
WR
GD
VDC_SGATE
P1.1V
_PW
RG
D
KB
C3_C
HG
4.2V
P1.1V
_PW
RG
D
PW
R_M
V_D
isCharger
KB
C3_P
WR
ON
_INV
#K
BC
3_SU
SP
WR
PW
R_M
V_C
antiga
KB
C3_P
WR
ON
VC
CP
3_PW
RG
D
AU
X_P
GK
BC
3_SU
SP
WR
ME
M1_V
RE
F
CH
P3_D
PR
SLP
VR
CP
U1_D
PR
STP
#C
PU
1_PS
I#C
PU
1_VC
CS
EN
SE
CP
U1_V
ID(0)
CP
U1_V
ID(1)
CP
U1_V
ID(2)
CP
U1_V
ID(3)
CP
U1_V
ID(4)
CP
U1_V
ID(5)
CP
U1_V
ID(6)
CP
U1_V
SS
SE
NS
E
KB
C3_V
RO
N
VR
M3_C
PU
_PW
RG
D
VRM_ISEN1VRM_ISEN2VRM_PRMVRM_VSUM
KB
C3_P
WR
ON
VC
CP
3_PW
RG
D
AU
X_P
GK
BC
3_SU
SP
WR
AD
T3_SE
L#B
AT3_D
ETE
CT#
BAT3_SMCLK#BAT3_SMDATA#
KB
C3_C
HG
EN
-
8-12
- -
- This Document can not be used without Samsung's authorization
-
8. Block Diagram and Schematic
Samsung
Confidential
Samsung
Confidential
Samsung
Confidential
SR
P S
heet Num
ber: 12 of 73
X
EXCEPT AS AUTHORIZED BY SAMSUNG.
2
A
THIS SIDE UP
34.00 mm
W
INSERT
75.00 mm
L
SAMSUNG ELECTRONICS COS PROPERTY.
D
4
2
B
PROPRIETARY INFORMATION THAT IS
3
Type 2 module
EX
PR
ES
S C
AR
D
34.00 mm
54.00 mm
75.00 mm
SA
MS
UN
G
SAM
SUN
G PR
OPR
IET
AR
Y
1
Type 1 module
EXPRESS CARD
EXPRESS CARD
A
4
3
THIS DOCUMENT CONTAINS CONFIDENTIAL
D
X
C
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
5.00 mm
H
54.00 mm
WX
B
75.00 mm
INSERTTHIS SIDE UP
C
75.00 mm
LX
5.00 mm
H
1
ELE
CTR
ON
ICS
100nFC
729
10V10V
C773
100nF
P3.3V
_EX
PP
3.3V_A
UX
_EX
P
100nFC
774
10V100nFC
772
10V
OC
*
8P
ER
ST*
18R
CLK
EN
20S
HD
N*
STB
Y*
1S
YS
RS
T*6
THE
RM
AL
21
P1.5V
_EX
PP
3.3V
1.5VIN
_11214
1.5VIN
_211
1.5VO
UT_1
1.5VO
UT_2
13
23.3V
IN_1
3.3VIN
_24
3.3VO
UT_1
353.3V
OU
T_2
17A
UX
INA
UX
OU
T15
CP
PE
*109
CP
US
B*
7G
ND
16N
C_5
19
R710
0
U519
R5538D
001-TR-F
1205-002807
nostuff
10V
C770
100nF
nostuff0
R669
100nFC
769
10V
1M
NT1
2M
NT2
EX
PR
ES
S-26P
-FRA
ME
J10
3709-001491
R670
0nostuff
SH
OR
T5030
P3.3V
_AU
XP
1.5V_E
XP
10V
C771
100nF
P1.5V
22
PE
RS
T#13
PE
TN0
24P
ETP
025
RE
FCLK
+19
RE
FCLK
-18
RE
SE
RV
ED
_15
RE
SE
RV
ED
_26
SM
B_C
LK7
SM
B_D
ATA
8
US
B_D
+3
US
B_D
-2
WA
KE
#11
+1.5V_1
10+1.5v_2
9
+3.3V_1
14+3.3V
_215
+3.3V_A
UX
12
CLK
RE
Q#
16C
PP
E#
17
CP
US
B#
4
GN
D_1
1G
ND
_220
GN
D_3
23G
ND
_426
MN
T12728
MN
T2
PE
RN
021
PE
RP
0
P3.3V
_EX
PP
3.3V_A
UX
_EX
P
3711-006496
J9EDG
E-X
PR
ES
S-26P
PE
X1_E
XP
CA
RD
TXP
3
SM
B3_C
LK
P3.3VR
70910K
PE
X1_E
XP
CA
RD
RX
N3
PE
X1_E
XP
CA
RD
RX
P3
PE
X1_E
XP
CA
RD
TXN
3
EX
P3_C
PP
E#
EX
P3_C
PU
SB
#
EX
P3_P
ER
ST#
CH
P3_S
LPS
3#P
LT3_RS
T#
EX
P3_C
LKR
EQ
#E
XP
3_CP
PE
#
EX
P3_C
PU
SB
#
EX
P3_P
ER
ST#
CLK
1_EX
PC
AR
DC
LK1_E
XP
CA
RD
#
SM
B3_D
ATA
US
B3_P
4+U
SB
3_P4-
PE
X3_W
AK
E#
-
8-13
- -
- This Document can not be used without Samsung's authorization
-
8. Block Diagram and Schematic
Samsung
Confidential
Samsung
Confidential
Samsung
Confidential
SR
P S
heet Num
ber: 13 of 73 A
PROPRIETARY INFORMATION THAT IS
Add for A
U6372
(2008.02.29)
40mil trace
EM
C S
olution(07.10.18)
ELE
CTR
ON
ICS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D
Place the resistor as close as possible
to prevent 48MH
z stub
2-in-1 Socket
SAMSUNG ELECTRONICS COS PROPERTY.
44
THIS DOCUMENT CONTAINS CONFIDENTIAL
3
SA
MS
UN
G
SAM
SUN
G PR
OPR
IET
AR
Y
3
BA C
2 IN 1 C
AR
D
1
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
100nFC
476
10V
0R
296
nostuff
0.022nFC
467
50Vnostuff
P3.3V
_MC
D100nFC
482
10V
R290
10K1%
R295
330
10V
C481
100nF100nFC
480
10V
50Vnostuff
nostuff
1000nFC
876
6.3V
C468
0.022nF
0R
298
100nFC
474
10V
C485
0.018nF50V
nostuff
33R
279
0.018nFC
483
50V
nostuff
6.3V
C831
10000nF
P3.3V
_MC
D
MN
T11213
MN
T2
VD
D4
VS
S1
36V
SS
2
11W
RITE
_PR
OTE
CT
3709-001492
J515E
DG
E-S
D-9P
CA
RD
_DE
TEC
T10 1
CD
_DA
T3
CLK
5
CM
D27
DA
T08
DA
T1D
AT2
9
P3.3V
100nFC
475
10V1000nFC
484
6.3V
1V
DD
H14
VD
D_U
10
XD
CD
#22
XI
7X
O8
MS
_INS
18
NC
_111
NC
_212
RE
AD
ER
_EN
16
RE
SE
T#47
RE
XT
2
SD
CD
#21
SM
CD
#19
V18
13
VC
C3
VD
D
CFR
D#_X
DC
E#
25C
FRE
SE
T_XD
WR
#23
CFW
R#_X
DR
D#
24
CFW
T#46
DM
5D
P4
GN
D6
GN
DH
17
GN
D_U
9
GN
D_V
DD
48
GP
ON
629
44C
FD15_X
DD
745
CFD
1_MS
D1_X
DW
P#
31
CFD
2_MS
D2_S
DW
P32
CFD
3_MS
D3_X
DR
B#
33C
FD4_S
DD
034
CFD
5_SD
D1
35C
FD6_S
DD
236
CFD
7_SD
D3
37C
FD8_S
DD
4_XD
D0
38
CFD
9_SD
D5_X
DD
139
CA
RD
_PO
WE
R15
CFA
D0_S
DC
LK_M
SB
S28
CFA
D1_M
S
