SDL Seminar Presentation

8/4/2019 SDL Seminar Presentation

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118/04/2012CDTA/Microelectronics

CHENOUF. A

Advanced Technologies Development CenterMicroelectronics & Nanotechology laboratory

Presented by : Chenouf. A CAD/VLSI TEAM

Design Kit Development Project Team


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CHENOUF. A

1_Introduction

2_STD Cell developmentflow

3_Observations


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CHENOUF. A


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CHENOUF. A

1_Introduction

System design

Logic design

Circuit design

Layout design

IC Design process

A typical IC design process is composed of the 4 following steps:

The process of defining the circuitfunctionality & input/output behavior

Process of transforming high level Description into a

netlist of technology-independent logic elements

System Design

Logic Design

Circuit Design

Layout Design

Technologymapping

Process of transforming the basic logic components

into a network of transistors & interconnects

The process of creating geometrical shapes on # masklayers which corresponds to a silicon implementation ofthe IC

The transition from atechnology-independent processto a technology -dependentprocess i.efrom logic synthesis to the circuitand layout design phases iscalled Technology mapping

This procedure is carried out

using a specified layout stylesuch as PLA, Gate array, sea ofgates, standard cells or full-custom design implementations


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CHENOUF. A

A standard cell is a small circuit layout designed with anumber of constraints.It is used as a building block in larger layouts.

What s a standard cell ?

The cells with different functions and layouts have to fit together.


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CHENOUF. A


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Standard Cell Library Development

a) Defining cells schematic;

b) logical simulation of the cell (if needed);

c) Electrical simulation for transistor sizing;

d) Laying out the cell;

e) Design checking (verification) DRC, ERC, LVS;

f) Parasitic parameters extraction;

g) Post-layout simulation ;

h) Delay equation derivation for the cell;

i) Tape out & eventual test assistance and SCL( if needed)

j) Contribution in the Integration in the synthesis tool (if needed)

k) Documentation of the Library


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818/04/2012 CDTA/MicroelectronicsCHENOUF. A

Cells Design Flow

Simulation

Schematic

Layout

Extraction

Netlist

Verification

Extracted

Netlist

techfiles

Devicemodels


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1st Step: Cells schematic

A CMOS gate is composed of two networks : an nMOS pull-downnetwork to connect the output to 0 (GND) and a pMOS pull-up networkto connect the output to 1 (VDD). The networks are arranged such thatone is ON & the other is OFF for any input pattern.

Pmos

Pull_upnetwork

NmosPull_downnetwork

Inputs output

Schematic of NAND2

A

B

Y

VDD

GND


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2nd Step: logic simulation

At the logic level, a gate is presented by its truth table witch

The logic simulation checks if the output corresponds faithfully to theexpected answer for a given input pattern

NAND2_ Truth Table

AB Y

0 0 1

0 1 1

1 0 1

1 1 0

A

B

Y

A

BY

A

B

Y

11 0


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3rdStep: Electrical Simulationit entails the representation of the CMOS cell as a netlist oftransistors. Then, to run the electrical simulator on this netlist to getthe results corresponding to the applied inputs.

From the gotten waveforms, the designer extracts many parametersthat characterize his cell.

A

B

Y

m1

m2

m3m4D G S B L W

m1 3 1 0 0 ? ?

m2 4 2 3 0 ? ?

m3 4 2 5 5 ? ?

m4 4 1 5 5 ? ?0

1 3

2

4

5 Corresponding Netlist


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4th Step: laying out the cell

Design rules Standard rules

The constraints imposedon the geometry

of an integrated circuitLayout in order to

guarantee that the circuitcan be fabricated

with an acceptable yield.

Some rules that must befollowed to ensure theconformity of the cells

made. Therefore to bepractical to use in big

arrays

1_ Size rules

2_ Separation

rules

3_ Overlap rules

Rules for Stdcells

1_Naming Conventions.

2_Cover Layers

3_Enclosure of abutmentbox.

4_Cell Height.


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Device

Geometries

5th Step: Physical Verification

Layout

Database

DRC

LVS

ERC

PEX

Extracted

Netlist

SchematicNetlist

Parasitics


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6th Step: Delay equation derivation

Rise time,tr= time for a waveform to rise from 10% to 90% of its steady-state value

Fall time,tf = time for a waveform to fall from 90% to 10% of its steady-state value

Edge rate,trf= (tr+ tf)/2

Propagation delay time = maximum time from input crossing 50% to the output crossing 50% (worst case)

Contamination delay time = minimum time from input crossing 50% to the output crossing 50% (best case)

The gate thatcharges or dischargesa node is called thedriver and the gates and wires being driven are

called the load

Dabs = d *

The term timing model is used to describe delays outside logic cells while the term delay

model is used to describe delays inside logic cells.

These terms are not standard and often people use them interchangeably.

h ff i D l


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parameters that affect propagation Delay

The delay is usually quoted assuming typical process parameters

and worst-case environment (low power supply voltage and high temperature)

Supplyvoltage

Temper-ature

Fan-outloading

Inter-connectloading

Input-transition

Time

Timingconstraint

Process

variation


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Combinational Gate Delay Model

The delay of a logic gate is composed of the delay due to parasitic delayp(no load delay)

and the delay due to the loadf( effort delay). It can be written as:

pis theparasitic delayinherent to the gate whenno loadis attached;

f is theeffort delaythat depends on thecomplexityandfan-outof the gate.

The logical effort and parasitic delay can be estimated either by using RC models or extracted bycurve-fitting simulated data.

Le logical effort is the ratio of the input capacitance of the gate to the input capacitance of aninverter that can deliver the same output current

A gate drivingh identical copies of itself is said to have an electrical effort of h

If the load isnot identicalcopies of the gate, the electrical effort can be computed as h = Cout/ Cin

d = f + p

f = g * h

Gate delay = no-load delay + K * Cload

In general, a gate delay is given as follows :


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Final Step:Tapeout Flow

Layout

Database

Schematic

Netlist

Bonding

Diagram

Verification

GDSII File

CDTAs Clean Room

Stream Out

C ll d t ti


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Cells documentation

It consists in generating a final datasheet for the specified design(cells) by reporting the characteristics according to a user-defined

method and attaching graphs (symbols) and plots together in populardocument formats


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Observations


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Observations

Confused by the chosen cells ( many cells are

useless in the nearest future & others are out ofdate),

no information is available about synthesizer &

PNR constraints on Cells,missed tool for cell characterization &documentation utility


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Documents

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