Sembt5 Arch Io

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    fCPU

    statusreg

    datareg m

    e c h a n i s m

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

    time

    bit 0 bit 1 bit n-1

    no char(marking)

    start

    stop

    ... par

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    8251

    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

    CPU

    status

    (8 bit)

    data(8 bit)

    serialport

    xmit/rcv

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

    CPU

    statusreg

    data

    reg m e c h a n i s m

    P C

    intr request

    intr ack

    data/address

    I R

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    fhead tailhead tail

    a

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

    : : : :

    empty

    a

    empty

    b

    bc

    c

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

    : : : : :

    B

    A,B

    C

    A

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

    : :

    receiverequest

    receiveack

    receivevector

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    RMR2012

    Maths is not everything

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    RMR2012

    Maths is not everything

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    RMR2012

    Maths is not everything

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

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    RMR2012

    Maths is not everything

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

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    RMR2012

    Maths is not everything

    39

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    RMR2012

    Maths is not everything

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    Interrupts

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    INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT ADDRESS SECTION PRIORIT

    Power-upExternal resetWatchdog

    PORIFGRSTIFGWDTIFG

    Reset 0xFFFE .reset 15, highest

    NMIOscillator faultFlash memory violation

    NMIIFGOFIFGACCDVIFG

    Non-maskable 0xFFFC .int14 14

    Timer_B3 TBCCR0 CCIFG Maskable 0xFFFA .int13 13

    Timer_B3 TBCCR1 CCIFGTBCCR2 CCIFG, TBIFG Maskable 0xFFF8 .int12 12

    0xFFF6 .int11 11Watchdog Timer WDTIFG Maskable 0xFFF4 .int10 10

    Timer_A3 TACCR0 CCIFG Maskable 0xFFF2 .int09 9

    Timer_A3 TACCR1 CCIFG,TACCR2 CCIFG, TAIFG Maskable 0xFFF0 .int08 8

    USCI_A0/USCI_B0 Rx UCA0RXIFG, USB0RXIFG Maskable 0xFFEE .int07 7

    USCI_Z0/USCI_B0 Tx UCA0TXIFG, UCB0TXIFG Maskable 0xFFEC .int06 6

    ADC10 ADC10IFG Maskable 0xFFEA .int05 50xFFE8 .int04 4

    I/O Port P2 P2IFG.0 P2IFG.7 Maskable 0xFFE6 .int03 3

    I/O Port P1 P1IFG.0 P1IFG.7 Maskable 0xFFE4 .int02 2

    0xFFE2 .int01 10xFFE0 .int00 0

    RMR2012

    Maths is not everything

    Interrupts

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    RMR2012

    Maths is not everything

    Byte8-bit Special Function Registers0x000F0x000016

    Byte8-bit Peripherals Modules0x00FF0x0010240

    Word16-bit Peripherals Modules0x01FF0x0100256

    Word/ByteStack0x05FF

    0x02001KBSRAM

    Word/ByteProgram Code0xFFBF

    0x8000

    WordInterrupt Vector Table0xFFFF0xFFC032KBFlash

    AccessDescriptionAddressSizeMemory

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    RMR2012

    Maths is not everything

    44

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    RMR2012

    Maths is not everything

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    RMR2012

    Maths is not everything

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    RMR2012

    Maths is not everything

    Mnemonic Operation DescriptionPUSH( .B or .W ) src SP-2 SP, src @SP Push byte/word source on stack

    CALL dst SP-2 SP, PC+2 @SPdst PC

    Subroutine call to destination

    RETI TOS SR, SP+2 SPTOS PC, SP+2 SP

    Return from interrupt

    Mnemonic Operation Emulation DescriptionRET @SP PC

    SP+2 SPMOV @SP+,PC Return from subroutine

    POP( .B or .W ) dst @SP tempSP+2 SPtemp dst

    MOV(.B or .W) @SP+,dst

    Pop byte/word from stack todestination

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    RMR2012

    Maths is not everything

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

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    RMR2012

    Maths is not everything

    2 0 0 8 W a y n e

    W o l

    f

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    RMR2012

    Maths is not everything

    0 8 W a y n e

    W o l

    f