8/13/2019 Sembt5 Arch Io
1/52
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2/52
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RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
fCPU
statusreg
datareg m
e c h a n i s m
8/13/2019 Sembt5 Arch Io
4/52
8/13/2019 Sembt5 Arch Io
5/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
time
bit 0 bit 1 bit n-1
no char(marking)
start
stop
... par
8/13/2019 Sembt5 Arch Io
6/52
8251
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
CPU
status
(8 bit)
data(8 bit)
serialport
xmit/rcv
8/13/2019 Sembt5 Arch Io
7/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
8/13/2019 Sembt5 Arch Io
8/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
8/13/2019 Sembt5 Arch Io
9/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
8/13/2019 Sembt5 Arch Io
10/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
8/13/2019 Sembt5 Arch Io
11/52
8/13/2019 Sembt5 Arch Io
12/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
8/13/2019 Sembt5 Arch Io
13/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
8/13/2019 Sembt5 Arch Io
14/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
CPU
statusreg
data
reg m e c h a n i s m
P C
intr request
intr ack
data/address
I R
8/13/2019 Sembt5 Arch Io
15/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
8/13/2019 Sembt5 Arch Io
16/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
8/13/2019 Sembt5 Arch Io
17/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
8/13/2019 Sembt5 Arch Io
18/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
fhead tailhead tail
a
8/13/2019 Sembt5 Arch Io
19/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
8/13/2019 Sembt5 Arch Io
20/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
: : : :
empty
a
empty
b
bc
c
8/13/2019 Sembt5 Arch Io
21/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
8/13/2019 Sembt5 Arch Io
22/52
8/13/2019 Sembt5 Arch Io
23/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
8/13/2019 Sembt5 Arch Io
24/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
: : : : :
B
A,B
C
A
8/13/2019 Sembt5 Arch Io
25/52
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RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
: :
receiverequest
receiveack
receivevector
8/13/2019 Sembt5 Arch Io
27/52
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8/13/2019 Sembt5 Arch Io
29/52
RMR2012
Maths is not everything
8/13/2019 Sembt5 Arch Io
30/52
RMR2012
Maths is not everything
8/13/2019 Sembt5 Arch Io
31/52
RMR2012
Maths is not everything
8/13/2019 Sembt5 Arch Io
32/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
8/13/2019 Sembt5 Arch Io
33/52
RMR2012
Maths is not everything
8/13/2019 Sembt5 Arch Io
34/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
8/13/2019 Sembt5 Arch Io
35/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
8/13/2019 Sembt5 Arch Io
36/52
8/13/2019 Sembt5 Arch Io
37/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
8/13/2019 Sembt5 Arch Io
38/52
8/13/2019 Sembt5 Arch Io
39/52
RMR2012
Maths is not everything
39
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RMR2012
Maths is not everything
40
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Interrupts
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INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT ADDRESS SECTION PRIORIT
Power-upExternal resetWatchdog
PORIFGRSTIFGWDTIFG
Reset 0xFFFE .reset 15, highest
NMIOscillator faultFlash memory violation
NMIIFGOFIFGACCDVIFG
Non-maskable 0xFFFC .int14 14
Timer_B3 TBCCR0 CCIFG Maskable 0xFFFA .int13 13
Timer_B3 TBCCR1 CCIFGTBCCR2 CCIFG, TBIFG Maskable 0xFFF8 .int12 12
0xFFF6 .int11 11Watchdog Timer WDTIFG Maskable 0xFFF4 .int10 10
Timer_A3 TACCR0 CCIFG Maskable 0xFFF2 .int09 9
Timer_A3 TACCR1 CCIFG,TACCR2 CCIFG, TAIFG Maskable 0xFFF0 .int08 8
USCI_A0/USCI_B0 Rx UCA0RXIFG, USB0RXIFG Maskable 0xFFEE .int07 7
USCI_Z0/USCI_B0 Tx UCA0TXIFG, UCB0TXIFG Maskable 0xFFEC .int06 6
ADC10 ADC10IFG Maskable 0xFFEA .int05 50xFFE8 .int04 4
I/O Port P2 P2IFG.0 P2IFG.7 Maskable 0xFFE6 .int03 3
I/O Port P1 P1IFG.0 P1IFG.7 Maskable 0xFFE4 .int02 2
0xFFE2 .int01 10xFFE0 .int00 0
RMR2012
Maths is not everything
Interrupts
8/13/2019 Sembt5 Arch Io
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RMR2012
Maths is not everything
Byte8-bit Special Function Registers0x000F0x000016
Byte8-bit Peripherals Modules0x00FF0x0010240
Word16-bit Peripherals Modules0x01FF0x0100256
Word/ByteStack0x05FF
0x02001KBSRAM
Word/ByteProgram Code0xFFBF
0x8000
WordInterrupt Vector Table0xFFFF0xFFC032KBFlash
AccessDescriptionAddressSizeMemory
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RMR2012
Maths is not everything
44
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RMR2012
Maths is not everything
8/13/2019 Sembt5 Arch Io
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RMR2012
Maths is not everything
8/13/2019 Sembt5 Arch Io
47/52
RMR2012
Maths is not everything
Mnemonic Operation DescriptionPUSH( .B or .W ) src SP-2 SP, src @SP Push byte/word source on stack
CALL dst SP-2 SP, PC+2 @SPdst PC
Subroutine call to destination
RETI TOS SR, SP+2 SPTOS PC, SP+2 SP
Return from interrupt
Mnemonic Operation Emulation DescriptionRET @SP PC
SP+2 SPMOV @SP+,PC Return from subroutine
POP( .B or .W ) dst @SP tempSP+2 SPtemp dst
MOV(.B or .W) @SP+,dst
Pop byte/word from stack todestination
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RMR2012
Maths is not everything
8/13/2019 Sembt5 Arch Io
49/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
8/13/2019 Sembt5 Arch Io
50/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
8/13/2019 Sembt5 Arch Io
51/52
RMR2012
Maths is not everything
2 0 0 8 W a y n e
W o l
f
8/13/2019 Sembt5 Arch Io
52/52
RMR2012
Maths is not everything
0 8 W a y n e
W o l
f