Single-Stage Amplifiers - 國立中興大學cc.ee.nchu.edu.tw/~aiclab/teaching/AIC/lect03.pdf · Single-Stage Amplifiers ... the characteristic of an amplifier is a nonlinear

1

Ching-Yuan Yang

National Chung-Hsing UniversityDepartment of Electrical Engineering

Single-Stage Amplifiers

類比電路設計(3349) - 2004

3-1 Ching-Yuan Yang / EE, NCHUAnalog-Circuit Design

Reading

– B. Razavi Chapter 3.

Introduction

In this lecture, we study the low-frequency behavior of single-stage CMOS amplifiers. Analyzing both the large-signal and the small-signal characteristics of each circuit, we develop intuitive techniques and models that prove useful in understanding more complex systems. An important part of a designer’s job is to use proper approximations so as to create a simple mental picture of a complicated circuit. The intuition thus gained makes it possible to formulate the behavior of most circuits by inspection rather than by lengthy calculations.

Overview

2


Basic concepts

Generally, the characteristic of an amplifier is a nonlinear function,

y(t) ≈ α0 + α1 x(t) + α2 x2(t) + + αn xn(t)

where x(t) and y(t) may be current or voltage.

For a sufficiently narrow range of x,

y(t) ≈ α0 + α1 x(t)

where α0 can be considered the operating (bias) point and α1 the small signal gain.

Systemx (t) y (t)


Analog design octagon

What aspects to the performance of an amplifier are important? In addition to gain and speed, such parameters as power dissipation, supply voltage, linearity, noise or maximum voltage swings may be important. Furthermore, the input and output impedances determine how the circuit interacts with preceding and subsequent stages. In practice, most of these parameters trade with each other, making the design a multi-dimensional optimization problem. Illustrated in the “analog design octagon”, such trade-offs present many challenges in the design of high-performance amplifiers, requiring intuition and experience to arrive at an acceptable compromise.

3


Common-source stage with resistive load

Schematic

Analysis(1):If the input voltage increases from zero, M1 is off and Vout = VDD.

As Vin approaches VTH, M1 begins to turn on, drawing current from RD and lowering Vout.

Input-output characteristic


Common-source stage with resistive load (cont’d)

(2):If VD > VG − VTH, M1 is in saturation,

where channel-length modulation is neglected, and at point A: Vout = Vin1 −VTH. Using above equation as the input-output characteristic and viewing its slop as the small-signal gain,

Small-signal model for the saturation region

DmTHinoxnDin

outv RgVV

LWCR

VVA −=−−=∂∂

= )(µ

2)(21

THinoxnDDDout VVL

WCRVV −−= µ

4



Considering the effect of channel-length modulation in M1, then

and

Using the approximation ID ≈ (1/2)µnCox(W/L)(Vin − VTH )2 and λID = 1/rO, then

Small-signal model of CS stage including the transistor output resistance

)//(1 DOm

DO

DOm

DD

Dmv Rrg

RrRrg

IRRgA −=

+−=

+−=

λ

)1()(21 2

outTHinoxnDDDout VVVL

WCRVV λµ +−−=

in

outTHinoxnDoutTHinoxnD

in

out

VVVV

LWCRVVV

LWCR

VV

∂∂

−−+−−=∂∂ λµλµ 2)(

21)1)((



(3):For Vin > Vin1, M1 is in the triode region,

If Vin is high enough to drive M1 into deep triode region, Vout << 2(Vin − VTH),

then

Equivalent circuit in deep triode region

])(2[21 2

outoutTHinoxnDDDout VVVVL

WCRVV −−−= µ

)(1 THinDoxn

DD

Don

onDDout

VVRL

WC

VRR

RVV−+

=+

=µ

5


CS stage with diode-connected load

Diode-connected NMOS/PMOS devices

Measure the equivalent resistance

mO

mX

XX g

rgI

VR 11≈==

OmbmX

XX r

ggIVR

+==

1

mbm gg +≈

1


CS stage with diode-connected load (cont’d)

Schematic

η

η

+⋅−=

+⋅−=

+−=

11

)/()/(

11

1

2

1

2

1

221

LWLW

gg

gggA

m

m

mbmmv

Neglecting channel-length modulation for simplicity, we have

and hence

If the variation of VTH2 with Vout is small, the circuit exhibits a linear input-output characteristic. The small-signal gain can also be computed by differentiating both sides with respect to Vin :

Since , then

Consider channel-length modulation:

( ) ( )222

21

1 21

21

THoutDDoxnTHinoxn VVVL

WCVVL

WC −−

=−

µµ

( ) ( )22

11

THoutDDTHin VVVL

WVVL

W−−

=−

∂∂

−∂∂

−

=

in

TH

in

out

VV

VV

LW

LW 2

21

∂∂

=

∂∂

∂∂

=∂∂

in

out

in

out

out

TH

in

TH

VV

VV

VV

VV η22

η+−=

∂∂

11

)/()/(2

1

LWLW

VV

in

out

−= 21

21 ////1

oom

mv rrg

gA

6



Diode-connected device with stepped bias current

Input/output characteristic

M1 triode

M1 saturated

Subthreshold condition



CS stage with diode-connected PMOS device

Where channel-length modulation is neglected.For example, to achieve a gain of 10, and

.

Specifically, ,

revealing that

21 DD II =

( ) ( )2222

211

1THGSpTHGSn VV

LWVV

LW

−

≈−

µµ

vTHGS

THGS AVVVV

−≈−−

11

22

100)/(/)/( 21 =LWLW pn µµ

2

1

)/()/(

LWLWA

p

nv µ

µ−=

7


CS stage with current-source loadSchematic

The output impedance of MOSFETs at a drain current can be scaled by changing the channel length, i.e., λ ∝ 1 / L and hence ro∝ L / ID. Thus, longer transistors yield a higher voltage gain.

Since , scaling up only L1 lowers gm1. The intrinsic gain of the

transistor can be written as , indicating that the gain

increases with L because λ depends more strongly on L than gm does.

Note that gm ro decreases as ID increases. Increasing L2 while keeping W2 constant increases ro2 and hence the voltage gain, but at the cost higher |VDS2| required to maintain M2 in saturation.

11 )/( LWgm ∝

DDoxnom I

ICLWrgλ

µ 1)/(2 111 ⋅=

M1 and M2 operate in saturation.Since Rout = rO1 || rO2, the gain is Av = −gm1 (rO1 || rO2).The output impedance and the minimum required |VDS| of M2are less strongly coupled than the value and voltage drop of a resistor.The voltage |VDS,min| = |VGS2 − VTH2| can be reduced to even a few hundred millivolts by simply increasing the width of M2.


CS stage with triode load

Schematic

M2 operates in deep triode region.The gate of M2 is biased at a sufficiently low level.Load value:

Note: Vout,max = VDD.

( )THPbDDoxpon VVVLWC

R−−

=2

2 )/(1

µ

8


CS stage with source degeneration

Schematic

Small-signal equivalent circuit of a degenerated CS stage

Sm

D

Sm

DmDmv

Sm

m

in

Dm

Rg

RRg

RgRGA

Rgg

VIG

+−=

+−=−=

+=

∂∂

=

1

1

1

Resistance seen in the source path

( ) ( )o

SoutSoutmbSoutinm

o

SoutXmbmout

rRIRIgRIVg

rRIVgVgI

−−+−=

−−= 1

[ ] oSmbmS

om

in

outm rRggR

rgVIG

⋅+++==⇒

)(1


CS stage with source degeneration (cont’d)

CS device without source degeneration, RS = 0.

CS device with source degeneration, RS ≠ 0.

9



Equivalent circuit for calculating the output resistance of a degenerated CS stage

V1: V1 = −IxRS

iro: Ix − (gm + gmb)V1 = Ix + (gm + gmb)RSIxVX: VX = ro[Ix + (gm + gmb)RSIx] + IxRS

Thus, Rout = VX/ Ix = [1 + (gm + gmb)RS] ro + RS = [1 + (gm + gmb)ro] RS + ro

Since typically (gm + gmb)ro >> 1, we have

Rout ≈ (gm + gmb)roRS + ro = [1 + (gm + gmb)RS] ro



Change in drain current in response to change in applied voltage to drain

The voltage change across RS is equal to

The change in current is

That is

oSmbm

Smbm

RSrR

gg

RggVV

++

+∆=∆//1

//1

( )[ ] SoSmbmS

RS

RrRggV

RVI

+++∆=

∆=∆

11

( )[ ] outSoSmbm RRrRggIV

=+++=∆∆ 1

10


Small-signal model of degenerated CS stage

It follows that

Let us rewrite as( )

( )[ ]( ) oSmbmoSD

oSmbmoSD

oSmbmoS

omv rRggrRR

rRggrRRrRggrR

rgA+++++++

⋅+++

−=

( )outDm RRG //−=

( ) outD

Dom

oSmbmoSD

Dom

in

out

RRRrg

rRggrRRRrg

VV

+−

=++++

−=

D

Souto

D

Soutmb

D

Soutinmo

D

outS

D

outoroout R

RVrRRVg

RRVVgr

RVR

RVrIV −

+

+−−=−=

( )

+

+−−=+−−=

D

Soutmb

D

Soutinm

D

outbsmbm

D

outro R

RVgRRVVg

RVVgVg

RVI 1

VS


Source follower (Common-drain stage)

Schematic


We can express the input-output characteristic as:

Differentiate both sides with respect to Vin :

Since , thus

Also, note that

Consequently,

( ) outSoutTHinoxn VRVVVL

WC =−− 2

21 µ

( )in

outS

in

out

in

THoutTHinoxn V

VRVV

VVVVV

LWC

∂∂

=

∂∂

−∂∂

−−− 1221 µ

inoutinTH VVVV ∂∂=∂∂ // η

( )

( ) ( )ηµ

µ

+−−+

−−=

∂∂

11 SoutTHinoxn

SoutTHinoxn

in

out

RVVVL

WC

RVVVL

WC

VV

( )outTHinoxnm VVVL

WCg −−= µ

( ) Smbm

Smv Rgg

RgA++

=1

11


Source follower (cont’d)

Small-signal equivalent circuit Voltage gain vs. input voltage

( ) Smbm

Sm

in

out

Soutoutmbm

outbsoutin

RggRg

VV

RVVgVgVVVVV

++=⇒

=−−==−

1

/

1

1

As the drain current and gm increase,

η+=

+≈

11

mbm

mv gg

gA



Source follower using a current source

Output impedance

V1 = VX

Ix − gmVx − gmbVx = 0

mbmmbmX

Xout ggggI

VR 111=

+==

12



Source follower including body effect

Thevenin equivalent

mbm

m

mbm

mbv

mbmmbmout

ggg

gg

gA

ggggR

+=

+=

+==

11

1

11//1



Source follower driving load resistance

mLOO

mb

LOOmb

v

gRrr

g

Rrrg�

A 11

1

21

21

+=

13



PMOS source follower with no body effect


Schematic

Comparison

SFvCSvin

out AAVV

×=

LmCSin

out

mL

LSF

in

out

RgVV

gR

RVV

1

1

1

≈

+≈

Cascade of source follower and CS stage

14


Schematic

Common-gate stage

(1) For Vin ≥ Vb − VTH, M1 is off and Vout = VDD.

(2) For lower value of Vin, if M1 is saturation

Obtaining a small-signal gain of

Since ∂VTH/∂Vin = ∂VTH/∂VSB = η, we have

(3) As Vin decreases, so does Vout , eventually driving M1 into the triode region if

( )221

THinboxnD VVVL

WCI −−= µ ( ) DTHinboxnDDout RVVVL

WCVV ⋅−−−= 2

21 µ

( )

∂∂

−−−−−=∂∂

in

THTHinboxn

in

out

VVVVV

LWC

VV 1µ

( )( ) ( ) DmTHinbDoxnin

out RgVVVRL

WCVV ηηµ +=+−−=∂∂ 11

( ) THbDTHinboxnDD VVRVVVL

WCV −=−−− 2

21 µ



CG stage (cont’d)

CG stage with finite output resistance

outinSD

outmbm

D

outo

mbmD

outroinS

D

out

VVRRVVgVg

RVr

VgVgRVIVR

RVV

=+−

−−

−

−−−

==+−

11

111 0

It follows that

DDSSOmbmO

Ombm

in

out RRRRrggr

rggVV

++++++

=)(

1)(

15


CG stage (cont’d)

Input resistanceV1 = −VX

Iro: Ix + gmV1 + gmbV1 = Ix − (gm + gmb)VX

So, RD Ix + ro[IX − (gm + gmb)VX ] = VX

Thus,

1. RD = 0,

2. Replace RD with an ideal current source,

Rin ≈ ∞

( )

( ) mbmombm

D

ombm

oD

X

X

ggrggR

rggrR

IV

++

+≈

+++

=

11

( )mbm

o

ombm

oin

ggr

rggrR

++=

++= 1

11

if (gm + gmb)ro >> 1.


CG stage (cont’d)

Output resistance

Example

DDSSOmbmO

Ombm

in

out RRRRrggr

rggVV

++++++

=)(

1)(

( ) 1++= ombm rgg

The gain does not depend on RS.

[ ]{ } DOSOmbmX

Xout RrRrgg

IVR +++== )(1

It is similar to that of CS.

16


Cascode stage

Schematic: CS + CG

M1: input deviceM2: cascode device

M1, M2 in saturation,Vb ≥ Vin + VGS2 – VTH1Vout ≥ Vin – VTH1 + VGS2 – VTH2

Addition of M2 to the circuit reduces the output voltage swing by at least the overdrive voltage of M2.For Vin ≤ VTH1, M1 and M2 are off, Vout = VDD, and VX ≈ Vb – VTH2.As Vin exceeds VTH1, M1 begins to draw current, and Vout drops. Depending on the device dimensions and the values of RD andVb, as Vin assumes sufficiently large values, two effects occur:(1) VX drops below Vin by VTH1, forcing M1

into the triode region.(2) Vout drops below Vb by VTH2, driving M2

into the triode region.


Cascode stage (cont’d)

Small-signal equivalent circuit (λ = 0)

Example

The voltage gain is equal to that of a

common-source stage because the drain

current produced by the input device (M1)

must flow through the cascode device (M2).

( )( )

( )( )

( )( ) Pmbm

DPmbmmDmv

Pmbm

Pmbmmm

Pmbm

Pmbminm

Pmbm

PinmD

RggRRgggRGA

RggRgggG

RggRggvg

Rgg

RvgI

+++

−=−=

+++

=

+++

=+

+

=

2

21

2

21

2

21

2

12

1

1

11

17



Output resistance

Triple cascode

The circuit can be viewed as a CS stage with a degeneration resistor equal to ro1.

Rout = [1+ (gm2 + gmb2)ro2]ro1 + ro2

Assuming gmbro >> 1, we have

Rout ≈ (gm2 + gmb2)ro2ro1.

That is, M2 boosts the output impedance of M1 by a factor of (gm2 + gmb2)ro2.

Cascoding can be extended to three or more stacked devices to achieve a higher output impedance, but the required additional voltage headroom makes such configurations less attractive.



Cascode stage with current-source load

Another approach

If both M1 and M2 operate in saturation, then Gm ≈ gm1 and Rout ≈ (gm2 + gmb2)ro2ro1, yielding

Av = −(gm2 + gmb2)ro2gm1ro1.

Thus, the maximum voltage gain is roughly equal to the square of the intrinsic gain of the transistors.

( )[ ]( )

( )[ ]1

1

//1

//1

22211

212221

22211

222

1

11

222

1

11

++−=−=

+++++

=

++

=

++

=

mbmoomoutmv

oombmoo

mbmoom

ombm

o

omm

ombm

o

oinmout

ggrrgRGA

rrggrrggrrg

rgg

r

rgG

rgg

r

rvgI

If we had assumed Gm = gm1,

then Av ≈ −gm1{[1+(gm2 + gmb2)ro2] ro1+ro2}

18



Increasing the output impedance by increasing the device length orcascoding

gmro 2gmro(gmro)2

Since , and , quadrupling L only doubles

the value of gmro while cascading results in an output impedance of roughly (gmro)2.Note that the transconductance of M1 in (b) is half that in (c), leading to higher noise.

DDoxnom I

IL

WCrgλ

µ 12 ⋅=L1

∝λ



NMOS cascode amplifier with PMOS cascode load

The high output impedance of the cascoding load yields a current

source closer to the ideal, but at the cost of voltage headroom.

The current source implemented with a PMOS cascode exhibits an impedance equal to [1 + (gm3 + gmb3)ro3] ro4 + ro3.

The maximum output swing is equal to .

Find the voltage gain: Gm ≈ gm1 and

Rout = {[1 + (gm2 + gmb2)ro2] ro1 + ro2} || {[1 + (gm3 + gmb3)ro3] ro4 + ro3},

we have |Av| ≈ gm1Rout. The voltage gain is approximated as

|Av| ≈ gm1[(gm2 ro2 ro1)|| (gm3 ro3 ro4)]

( ) ( ) 44332211 THGSTHGSTHGSTHGSDD VVVVVVVVV −−−−−−−−

19


Folded cascode

Schematic

The structures of (b) and (c) are called “folded cascode” stages because the small-signal current is “folded” up [in (b)] or down [in (c)].

Note that the total bias current in the folded cascode stage must be higher than that in the cascode stage to achieve comparable performance.


Folded cascode (cont’d)

AnalysisFor Vin > VDD − |VTH1|, M1 is off and M2 carries all of I1, yielding

Vout = VDD − I1RD.For Vin < VDD − |VTH1|, M1 turns on.

M1 is in saturation, giving

As Vin drops, ID2 decreases further, falling to zero if ID1 = I1.

For this to occur: VX = Vb − VTH2 and

Thus,

M1 (sat.):

M1 is in triode, , ID1 = I1, and VX ≈ VDD.

( )211

12 21

THinDDoxpD VVVL

WCII −−

−= µ

( ) 12

1112

1 IVVVLWC THinDDoxp =−−

µ

( ) 11

11 /

2TH

oxpDDin V

LWCIVV −−=

µ

( ) 1111

1

/2

THDDinTHoxp

DD VVVVLWC

IV −<<−−µ

( ) 11

11 /

2TH

oxpDDin V

LWCIVV −−<

µ

20


Folded cascode (cont’d)

• Folded cascode with cascode load – to achieve high voltage gain.

Documents

Single-Stage Amplifiers - 國立中興大學cc.ee.nchu.edu.tw/~aiclab/teaching/AIC/lect03.pdf · Single-Stage Amplifiers ... the characteristic of an amplifier is a nonlinear