SoC CAD 2016/1/24 1 Gem 5 Commit , Department of Electrical Engineering , National Cheng Kung University Tainan, Taiwan, R.O.C Xen ??? To be studied : NCKU SoC & ASIC Lab 2 Li-Sheng Chang, SoC CAD Commit Stage diagram commit stage ( commit.tick), thread squash Suash commit cycle ROB headInst retiring If squashing, inform the fetch stage of which instruction caused It'll try to re-fetch an instruction executing in microcode unless this is set K-K- ROB Rename Quene GetInst IEW Quene GetInst Send information Fetch Quene GetInst Send information NCKU SoC & ASIC Lab 3 Li-Sheng Chang, SoC CAD Commit Stage - ROB //Grab completed insts out of the IEW instruction queue if (!fromIEW->insts[inst_num]->isSquashed()) { DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready within ROB.\n" K-K- ROB headInst Rename Quene IEW quene //mark completed Fetch Quene NCKU SoC & ASIC Lab 4 Li-Sheng Chang, SoC CAD Commit stage mispredict template void DefaultCommit ::commit() DPRINTF(Commit, "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n", if (fromIEW->mispredictInst[tid]) { DPRINTF(Commit, "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n", } DPRINTF(Commit, "[tid:%i]: Squashing due to order violation [sn:%i]\n", tid, fromIEW->squashedSeqNum[tid Redirecting to PC %#x\n, else { DPRINTF(Commit, "[tid:%i]: Squashing due to order violation [sn:%i]\n", tid, fromIEW->squashedSeqNum[tid]); } DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n, tid, fromIEW- >pc[tid].nextInstAddr()); K-K- redirect NCKU SoC & ASIC Lab 5 Li-Sheng Chang, SoC CAD Commit stage commitInst //commit will be handled prior to putting new instructions in the ROB, also can't commit and squash things at the same time "Trying to commit instructions in the ROB.\n DPRINTF(Commit, "Trying to commit instructions in the ROB.\n") //Commit as many instructions as possible until the commit bandwidth limit is reached Trying to commit head instruction, [sn:%i] [tid:%i]\n DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n, head_inst->seqNum, tid) //Check for any interrupt that we've already squashed for and start processing it. if (interrupt != NoFault) handleInterrupt(); "Retiring squashed instruction from ROB.\n"); if (head_inst->isSquashed()) { DPRINTF(Commit, "Retiring squashed instruction from ROB.\n"); rob->retireHead(commit_thread); ++commitSquashedInsts; K-K- NCKU SoC & ASIC Lab 6 Li-Sheng Chang, SoC CAD Commit Stage - commitHead (1/3) template bool DefaultCommit ::commitHead(DynInstPtr &head_inst, unsigned inst_num) { ThreadID tid = head_inst->threadNumber; //If the instruction is not executed yet, then it will need extra handling. Encountered a barrier or non-speculative instruction [sn:%lli] at the head of the ROB, PC %s.\n, "Waiting for all stores to writeback.\n if (!head_inst->isExecuted()) { thread[tid]->funcExeInst--; // Make sure we are only trying to commit un-executed instructions we think are possible assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional() || head_inst->isMemBarrier() || head_inst->isWriteBarrier() || (head_inst->isLoad() && head_inst->uncacheable())); DPRINTF(Commit, Encountered a barrier or non-speculative instruction [sn:%lli] at the head of the ROB, PC %s.\n, head_inst->seqNum, head_inst->pcState()); if (inst_num > 0 || iewStage->hasStoresToWB(tid)) { DPRINTF(Commit, "Waiting for all stores to writeback.\n"); return false;} K-K- NCKU SoC & ASIC Lab 7 Li-Sheng Chang, SoC CAD Commit Stage - commitHead (2/3) // Change the instruction so it won't try to commit again until it is executed. head_inst->clearCanCommit(); Thread sync instructions are not handled yet . if (head_inst->isThreadSync()) { // Not handled for now. panic("Thread sync instructions are not handled yet.\n"); } // Check if the instruction caused a fault. If so, trap. Fault inst_fault = head_inst->getFault() .. Committing instruction with fault [sn:%lli]\n // If instruction has faulted, let the checker execute it and // check if it sees the same fault and control flow. if (cpu->checker) { cpu->checker->verify(head_inst); } . cpu->trap(inst_fault, tid, head_inst->staticInst); DPRINTF(Commit, Committing instruction with fault [sn:%lli]\n, head_inst->seqNum); .. generateTrapEvent(tid); // Generate trap squash event. return false ; } K-K- P.9 NCKU SoC & ASIC Lab 8 Li-Sheng Chang, SoC CAD Commit Stage - commitHead (3/3) Committing instruction with [sn:%lli] PC %s\n if (FullSystem) { if (thread[tid]->profile) { thread[tid]->profilePC = head_inst->instAddr(); ProfileNode *node = thread[tid]->profile->consume( thread[tid]->getTC(), head_inst->staticInst); DPRINTF(Commit, Committing instruction with [sn:%lli] PC %s\n, head_inst->seqNum, head_inst->pcState()); .,Return Instruction Committed [sn:%lli] PC %s \n if (head_inst->isReturn()) { DPRINTF(Commit,Return Instruction Committed [sn:%lli] PC %s \n, head_inst->seqNum, head_inst->pcState()); } K-K- NCKU SoC & ASIC Lab 9 Li-Sheng Chang, SoC CAD DefaultCommit ::TrapEvent class //used to schedule a squash due to a trap (fault or interrupt) to happen on a specific cycle class TrapEvent : public Event { private: DefaultCommit *commit; ThreadID tid; public: TrapEvent(DefaultCommit *_commit, ThreadID _tid); void process(); const char *description() const; }; template DefaultCommit ::TrapEvent::TrapEvent // , priority=50, flag=0x0004 (DefaultCommit *_commit, ThreadID _tid) : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid){ } template void DefaultCommit ::TrapEvent::process() { commit->trapSquash[tid] = true ; /* This will get reset by commit if it was switched out at the time of this event processing */ } template const char *DefaultCommit ::TrapEvent::description() const { return "Trap";} //member data // // class member function