TFT LCD AIM SPICE

P92943013 / 梁亦中

P91943014 / 方貴弘

Past History of SPICE

• SPICE : Simulation Program with Integrated Circuit Emphasis• 1968 : Ron Rohrer Berkeley,Larry Nagel CANCER• 1970 : SPICE1(Fortran)• 1975 : SPICE2(Fortran)• 1980 : SPICE3(C Language)• 1980~Now :

HSPICEPSPICEAIM-SPICE (AIM)Smart-SPICE (Silvaco)Eldo (Mentor)Spectre (Cadence)

HSPICE PSPICE

AIM-SPICE

Smar

tSPIC

E

EldoSpe

ctre

KernelBerkeleySPICE

Shell

SPICE Algorithms

Principle : Kirchhoff’s Law

Numerical analysis : Newton Method

01

N

nnI

01

N

nnV

node

Analog Circuit Design Flow

Circuit simulationSPICE

Schematic driven layout

Layout-Laker

Schematic edit

Post simulationSPICE

Parasitic R/C Extractor-Calibre RCX

DRC/LVS-Calibre

GDS II / Mask

Device model extraction 1. TEG data analysis 2. Curve fitting 3. Process characterization

Yes

No

AIM SPICE Parameter Extract_1

Modeled

Measured

IdVd CurveVg = 5V,10V,15V,20V,30V

IdVg CurveVd = 1V,4V,7V,10V,13V

TFT LCD Test Mask IV Curve

AIM SPICE Parameter Extract_2

-10 -5 0 5 10 15

Gate-source voltage [V]

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

Dra

in c

urren

t [

A]

-10 -5 0 5 10 15

Gate-source voltage [V]

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

Dra

in c

urren

t [

A]

-10 -5 0 5 10 15

Gate-source voltage [V]

10-13

10-12

10-11

10-10

10-9

10-8

10-7

10-6

10-5

10-4

Dra

in c

urren

t [

A]

Above Threshold Below Threshold Hole-InducedLeakage Current

IW

LC V V Vds lin FET ox g T ds, ( )

FET ng T ds

AA

V V V

V

I qW

LV n

t

d

V

Vsub n ds som

i

gFBe i

s

V Vs e

2

2( / )

I I EV V

V

VDSL

V

VGL

hl lth tho

ds gs

min exp

exp exp

1 1

1

ExtractParameter

AIM SPICE Parameter Extract_3

Pixel Equal Circuit & RC Calculation

Gate Linethe Nth

Gate Linethe (N-1)th

Data Linethe N-1th

Data Linethe N th

C gs C gd

C st(on gate)C lc

C pixel_data coup(next)

C pixel_data coup(own)

C gs_coup

C dg cross

C data_com ( lc )

C gate_com

Cgate =((Cst*Clc)/(Cst + Clc) + Cgs + Cgs_coup + Cdg cross + Cgate_com)*1280*3

Rgate =(ρ * L1/W1)*1280*3Cdata =Cgd + Cdg cross + Cdata_com + Cpixel_data_coup)*1024

Rdata=(ρ * L2/W2)*1024

Cpixel = Cgs + Cgs_coup + Clc + Cst + Cpixel_data_coup

12

3 4

5

6

7

9

8

10

1

2

3 4

5

6

7

9

810

L1

W1

L2

W2

We using 4 π Model to simulated one gate line and data line

2_1414_1

0_20_140_1

12_2626_1010_2323_10

5_2020_44_1717_3

0_120_260_110_230_10

0_50_200_40_170_3

4

12

1

2

1

8

1

4

12

1

2

1

2

12

1

2

1

2

1

8

1

RRR

CCCC

RRRR

RRRRR

CCCCC

CCCCCC

data

data

gate

gate

One πmodel

Using Pi(π) Model to Simulated

R

C

Panel Equal Circuit of Simulation

V

V

1

2

3 4 5

6 7 8

9 9 9

17 20

10 11 12

23 26

14V

Signal in

Gate n-1 Pulse

Gate n Pulse

If Resolution = 1280*1024Node 3 = Sub_pixel (0,512)Node 4 = Sub_pixel (1920,512)Node 5 = Sub_pixel (3840,512)

Driving Direction

1

6 7 8

2

SPICE Program Description 1 - Basic Definition

(Device+Name) Node Value / Parameter

ex: Rgate 1 3 25k Cgate 1 3 25p

Vgate 1 3 25V

M1 2(D) 3(G) 6(S) 0(GND) Model()

Device:D: DiodeC: CapacitanceI: Independent Current SourceJ: JFETM: MOSQ: BJTR: ResisterV: Independent Current Source

SPICE Program Description 2 - Basic Definition

Dot CommandFormat => . command

.DC 直流掃描

.END 檔案結束

.IC 設定起始電壓電流

.MODEL MODEL 宣告

.PLOT 輸出圖形

.PRINT 輸出數值

.TRAN 暫態分析

SPICE Program Description 3 – Power definitionVGATE1 3 0 PWL 0u vgl 25u vgl 25.01u vgh 35.31u vgh 35.32u vgl 150u vgl

VSIG1 2 0 PULSE (vdl vdh 12.5u 1n 1n 12.499u 25u) V1 V2 start rise fall pulse width period

VCOM2 9 0 5V 5V DC voltage source

V1

V2

SPICE Program Description 4 - Example 1

'v(4)' 'v(5)''v(3)'

0.0u 20.0u 40.0u 60.0u 80.0u 100.0utime [sec]

-10.0

0.0

10.0

20.0

30.0

Y A

xis

Tit

le [

V]

*** Simulation of One Gate Delay by AIM-Spice ***

.param vgh=27V vgl=-6V vgc=-6V

.param gpi_r=1.176k gpi_c=24.27p

.param gpx_r=0.3k

.param length=9u width=18u

VGATE1 3 0 PWL 0u vgl 25u vgl 25.01u vgh

+35.31u vgh 35.32u vgl 150u vgl

.IC V(10)=vgl V(3)=vgl

***GATE DELAY 0 *** Drive IC

RGATE01 0 3 gpx_r

CGATE01 0 3 2.5p

CGATE02 0 10 2.5p

***GATE DELAY 1 *** PI-g1

RGATE11 3 6 gpi_r

RGATE12 6 4 gpi_r

CGATE11 3 0 gpi_c

CGATE12 6 0 gpi_c*2

CGATE13 4 0 gpi_c

***GATE DELAY 2 *** PI-g2

RGATE21 4 7 gpi_r

RGATE22 7 5 gpi_r

CGATE21 4 0 gpi_c

CGATE22 7 0 gpi_c*2

CGATE23 5 0 gpi_c

.TRAN 1.000000e-07 100u

.PLOT TRAN V(3) V(4) V(5)

.END

0 3 4 56 7

SPICE Program Description 5 - Model - 1

a-Si TFT in SMART SPICE.MODEL TFT NTFT (LEVEL = 35, ******* )

a-Si TFT in AIM SPICE.MODEL TFT NMOS (LEVEL = 15, ******* )

General form:

MXXXXXXX ND NG NS NB MNAME <L=VALUE> <W=VALUE> <AD=VALUE>+ <AS=VALUE> <PD=VALUE> <PS=VALUE> <NRD=VALUE>+ <NRS=VALUE> <OFF> <IC=VDS,VGS,VBS> <TEMP=T>

SPICE Program Description 6 - Model - 2

.MODEL TFT NMOS ( LEVEL = 15 TOX = 3.5E-7 +TNOM = 27 VTO = 1.6 +ALPHASAT= 0.8101843 DEFO = 0.598965 DELTA = 9.2 +EL = 1.1 EMU = 0.06 EPS = 11 +EPSI = 4.7 GAMMA = 0.3709371 GMIN = 3.98107E22 +IOL = 6.30957E-14 KASAT = 1E-3 KVT = -0.036 +LAMBDA = 0 M = 1.1733413 MUBAND = 1E-3 +SIGMAO = 3.16228E-15 VO = 0.37 VAA = 3.117726E4 +VDSL = 15 VFB = -2.41736 VGSL = 100 +VMIN = 0.797118 CGDO = 0.6n CGSO = 0.6n )

M1 2 3 6 0 TFT L=length W=width

Example of a-Si TFT Description by AIM Spice

SPICE Program Description 7 - Example 2

'v(6)''v(3)''v(2)'

0.0u 20.0u 40.0u 60.0u 80.0u 100.0utime [sec]

-10.0

0.0

10.0

20.0

30.0

Y A

xis

Tit

le [

V]

*** Simulation of One Pixel By AIM-Spice ***

.param vgh=27V vgl=-6V

.param vdl=1V vdh=10V

.param gpx_r=0.3k

.param lcc=0.179p csc=0.164p cgsc=0.0078p

.param length=9u width=18u

VGATE1 3 0 PWL 0u vgl 25u vgl 25.01u vgh 35.31u

+ vgh 35.32u vgl 150u vgl

VGATE2 10 0 vgl

VSIG1 2 0 PULSE (vdh vdl 12.5u 1n 1n 12.499u 25u)

VCOM2 9 0 5V

.IC V(10)=vgl V(3)=vgl V(9)=5V

.IC V(2)=vdh

.IC V(6)=vdl

RGATE01 0 3 gpx_r

RGATE02 0 10 gpx_r

CGATE01 0 3 2.5p

CGATE02 0 10 2.5p

CLC1 6 9 lcc

Cs1 6 10 csc

CGS1 3 6 cgsc

***TFT***

M1 2 3 6 0 TFT L=length W=width

* SiOx thickness 3500A

.model TFT NMOS(level=15 alphasat=0.715 defo=0.6 delta=5 emu=0.02

+ el=0.1 eps=11 epsi=4.7 gamma=0.535 gmin=1e+023 iol=2.8e-012

+ kvt=-0.01 lambda=0.001 m=1.2 muband=0.001 rd=220000 rs=220000

+ sigmao=5e-014 tnom=27 tox=3.5e-007 vaa=2400 vdsl=30 vfb=-5.38

+ vgsl=50 vmin=0.3 vo=0.29 vto=1.8 )

.TRAN 1.000000e-07 100u

.PLOT TRAN V(2) V(3) V(6)

.END

SPICE Output Node Waveform

'v(1)' 'v(12)''v(10)''v(8)''v(7)''v(6)''v(5)''v(3)''v(2)'

3.9u 17.7u 31.6u 45.4utime [sec]

-15.0

-0.2

14.5

29.3

Y A

xis

Tit

le [

V]

What can we gain from this Waveform Chart?• Gate Delay• Charging Capability• Feedthrough Voltage

Gate Delay Simulation Data

-10

-5

0

5

10

15

20

25

30

22 24 26 28 30 32 34 36 38 40 42 44

Start

End

Gate Delay(at Vg=0V)Measured=1.2usSimulated=1.2us

17” Gate Delay at charge time 10.3us

Gray level = L0 (black)

Other Case about SPICE Simulation_1

'v(8)''v(7)''v(6)''v(5)''v(3)''v(2)''v(1)'

0.0u 50.0u 100.0u 150.0utime [sec]

-10.0

0.0

10.0

20.0

30.0

Y A

xis

Tit

le [

V]

19” Gate Pulse Cut (Cs on Com)

Other Case about SPICE Simulation_2-1

dVcom = (dVp_P + dVp_N)/2

Other Case about SPICE Simulation_2-2

Smart SPICE & Measurement Comparison

0.0

50.0

100.0

150.0

200.0

250.0

300.0

1 2 3 4 5 6 7 8 9

Position

dVco

m (

mV

)

Measure

Simulation

Modify

Modify = Simulation * 1.5 17 inch

Other Case about SPICE Simulation_3

Cpd Coupling Effect Simulation

LCD Circuit for Smart Spice ( Orcad )

LCD Pixel Circuit for Smart Spice

Pixel CapacitanceClc=0.139pFCst=0.229pFCgs=0.011pFCpd_L=0.012pFCpd_R=0.010pFRlc=10E12ohm

Other CapacitanceCgc=0.009pFCdc=0.022pFCgd=0.056pF

The End