The Hardware/Software Interface Editionmenasce/cs465/slides-new/Chapter_05.pdfThe Hardware/Software Interface 5th Edition Chapter 5 ... Advanced DRAM Organization ! ... Solution: write

COMPUTER ORGANIZATION AND DESIGN The Hardware/Software Interface

5th Edition

Chapter 5

Large and Fast: Exploiting Memory Hierarchy

Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 2

Impact of Memory Access §5.1 Introduction

Program accesses 7 GB of RAM


Impact of Memory Access §5.1 Introduction

Program accesses 7 GB of RAM

14 sec

88 sec (74 sec memory contention)


Principle of Locality n  Programs access a small proportion of

their address space at any time n  Temporal locality

n  Items accessed recently are likely to be accessed again soon

n  e.g., instructions in a loop, induction variables n  Spatial locality

n  Items near those accessed recently are likely to be accessed soon

n  E.g., sequential instruction access, array data

§5.1 Introduction


Taking Advantage of Locality n  Memory hierarchy n  Store everything on disk n  Copy recently accessed (and nearby)

items from disk to smaller DRAM memory n  Main memory

n  Copy more recently accessed (and nearby) items from DRAM to smaller SRAM memory n  Cache memory attached to CPU


Memory Hierarchy Levels n  Block (aka line): unit of copying

n  May be multiple words

n  If accessed data is present in upper level n  Hit: access satisfied by upper level

n  Hit ratio: hits/accesses

n  If accessed data is absent n  Miss: block copied from lower level

n  Time taken: miss penalty n  Miss ratio: misses/accesses

= 1 – hit ratio n  Then accessed data supplied from

upper level


Memory Technology n  Static RAM (SRAM)

n  0.5ns – 2.5ns, $2000 – $5000 per GB

n  Dynamic RAM (DRAM) n  50ns – 70ns, $20 – $75 per GB

n  Flash memory n  5,000 – 50,000 ns, $0.75-$1.00 per GB

n  Magnetic disk n  5ms – 20ms, $0.20 – $2 per GB

n  Ideal memory n  Access time of SRAM n  Capacity and cost/GB of disk

§5.2 Mem

ory Technologies

DRAM Technology n  Data stored as a charge in a capacitor

n  Single transistor used to access the charge n  Must periodically be refreshed

n  Read contents and write back n  Performed on a DRAM “row”



Advanced DRAM Organization n  Bits in a DRAM are organized as a

rectangular array n  DRAM accesses an entire row n  Burst mode: supply successive words from a

row with reduced latency n  Double data rate (DDR) DRAM

n  Transfer on rising and falling clock edges n  Quad data rate (QDR) DRAM

n  Separate DDR inputs and outputs


DRAM Generations

0

50

100

150

200

250

300

'80 '83 '85 '89 '92 '96 '98 '00 '04 '07

TracTcac

Year Capacity $/GB

1980 64Kbit $1500000

1983 256Kbit $500000

1985 1Mbit $200000

1989 4Mbit $50000

1992 16Mbit $15000

1996 64Mbit $10000

1998 128Mbit $4000

2000 256Mbit $1000

2004 512Mbit $250

2007 1Gbit $50

DRAM Performance Factors n  Row buffer

n  Allows several words to be read and refreshed in parallel

n  Synchronous DRAM n  Allows for consecutive accesses in bursts without

needing to send each address n  Improves bandwidth

n  DRAM banking n  Allows simultaneous access to multiple DRAMs n  Improves bandwidth



DRAM Performance n  DDR4-3200 DRAM can do 3200 million

transfers/sec n  2 transfers/clock cycle è1600 million cycles/sec è

1600 MHz. n  DRAMs are internally organized to read/write

from multiple banks, each with its own row buffer. n  Bandwidth multiplied by number of banks

n  Dual Inline Memory Modules (DIMMs): 4-16 DRAMs, 8 bytes wide. n  DIMM with DDR4-3200 SDRAMs transfers at 8 * 3200

= 25,600 MB/sec. Called PC25600.


Increasing Memory Bandwidth

n  4-word wide memory n  Miss penalty = 1 + 15 + 1 = 17 bus cycles n  Bandwidth = 16 bytes / 17 cycles = 0.94 B/cycle

n  4-bank interleaved memory n  Miss penalty = 1 + 15 + 4×1 = 20 bus cycles n  Bandwidth = 16 bytes / 20 cycles = 0.8 B/cycle

Chapter 6 — Storage and Other I/O Topics — 14

Flash Storage n  Nonvolatile semiconductor storage

n  100× – 1000× faster than disk n  Smaller, lower power, more robust n  But more $/GB (between disk and DRAM)

§6.4 Flash Storage


Flash Types n  NOR flash: bit cell like a NOR gate

n  Random read/write access n  Used for instruction memory in embedded systems

n  NAND flash: bit cell like a NAND gate n  Denser (bits/area), but block-at-a-time access n  Cheaper per GB n  Used for USB keys, media storage, …

n  Flash bits wears out after 1000’s of accesses n  Not suitable for direct RAM or disk replacement n  Wear leveling: remap data to less used blocks


NAND Flash Types n  Organized in blocks, which are organized in pages. n  Pages cannot be rewritten in-place. n  Pages have to be written into any available page: “write-

anywhere.” n  Page of original data is invalidated. n  When all pages of a block are invalid, the block is given

to a pool of blocks to be garbage collected. n  The garbage collector erases blocks and returns them to

a pool of available blocks. n  Page states: available and unused è available and used

è unavailable è available and unused


Disk Storage n  Nonvolatile, rotating magnetic storage

§6.3 Disk S

torage


Disk Sectors and Access n  Each sector records

n  Sector ID n  Data (512 bytes, 4096 bytes proposed) n  Error correcting code (ECC)

n  Used to hide defects and recording errors n  Synchronization fields and gaps

n  Access to a sector involves n  Queuing delay if other accesses are pending n  Seek: move the heads n  Rotational latency n  Data transfer n  Controller overhead


Disk Access Example n  Given

n  512B sector, 15,000rpm, 4ms average seek time, 100MB/s transfer rate, 0.2ms controller overhead, idle disk

n  Average read time n  4ms seek time

+ ½ / (15,000/60) = 2ms rotational latency + 512 / 100MB/s = 0.005ms transfer time + 0.2ms controller delay = 6.2ms

n  If actual average seek time is 1ms n  Average read time = 3.2ms


Disk Performance Issues n  Manufacturers quote average seek time

n  Based on all possible seeks n  Locality and OS scheduling lead to smaller actual

average seek times n  Smart disk controller allocates physical sectors

on disk n  Present logical sector interface to host n  SCSI, ATA, SATA


Disk Performance Issues n  Disk drives include caches

n  Prefetch sectors in anticipation of access n  Avoid seek and rotational delay

n  http://www.wdc.com/wdproducts/library/SpecSheet/ENG/2879-771429.pdf


Cache Memory n  Cache memory

n  The level of the memory hierarchy closest to the CPU

n  Given accesses X1, …, Xn–1, Xn

§5.3 The Basics of C

aches

n  How do we know if the data is present?

n  Where do we look?


Direct Mapped Cache n  Location determined by address n  Direct mapped: only one choice

n  (Block address) modulo (#Blocks in cache)

n  #Blocks is a power of 2

n  Use low-order address bits


Tags and Valid Bits n  How do we know which particular block is

stored in a cache location? n  Store block address as well as the data n  Actually, only need the high-order bits n  Called the tag

n  What if there is no data in a location? n  Valid bit: 1 = present, 0 = not present n  Initially 0


Cache Example n  8-blocks, 1 word/block, direct mapped n  Initial state

Index V Tag Data 000 N 001 N 010 N 011 N 100 N 101 N 110 N 111 N


Cache Example

Index V Tag Data 000 N 001 N 010 N 011 N 100 N 101 N 110 Y 10 Mem[10110] 111 N

Word addr Binary addr Hit/miss Cache block 22 10 110 Miss 110


Cache Example

Index V Tag Data 000 N 001 N 010 Y 11 Mem[11010] 011 N 100 N 101 N 110 Y 10 Mem[10110] 111 N



Cache Example

Index V Tag Data 000 N 001 N 010 Y 11 Mem[11010] 011 N 100 N 101 N 110 Y 10 Mem[10110] 111 N

Word addr Binary addr Hit/miss Cache block 22 10 110 Hit 110 26 11 010 Hit 010


Cache Example

Index V Tag Data 000 Y 10 Mem[10000] 001 N 010 Y 11 Mem[11010] 011 Y 00 Mem[00011] 100 N 101 N 110 Y 10 Mem[10110] 111 N

Word addr Binary addr Hit/miss Cache block 16 10 000 Miss 000 3 00 011 Miss 011

16 10 000 Hit 000


Cache Example

Index V Tag Data 000 Y 10 Mem[10000] 001 N 010 Y 10 Mem[10010] 011 Y 00 Mem[00011] 100 N 101 N 110 Y 10 Mem[10110] 111 N



Address Subdivision


Example: Larger Block Size n  64 blocks, 16 bytes/block

n  To what block number does address 1200 map?

n  Block address = ⎣1200/16⎦ = 75 n  Block number = 75 modulo 64 = 11

Tag Index Offset 0 3 4 9 10 31

4 bits 6 bits 22 bits


Larger Block Size n  Cache size= 2n blocks, 2m words/block n  22 bytes per block è 2m+2 bytes/block n  No. bits of tag field

n  32 – (n + m + 2) n  To what block number address x maps?

n  ⎣x /2m+2 ⎦ modulo 2n

Tag Index Offset 0 31

m+2 bits n bits 32-(n+m+2) bits


Block Size Considerations n  Larger blocks should reduce miss rate

n  Due to spatial locality n  But in a fixed-sized cache

n  Larger blocks ⇒ fewer of them n  More competition ⇒ increased miss rate

n  Larger blocks ⇒ cache pollution n  Larger miss penalty

n  Can override benefit of reduced miss rate n  Early restart and critical-word-first can help


Block Size Considerations n  Larger blocks should reduce miss rate

n  Due to spatial locality n  But in a fixed-sized cache

n  Larger blocks ⇒ fewer of them n  More competition ⇒ increased miss rate

n  Larger blocks ⇒ cache pollution n  Larger miss penalty

n  Can override benefit of reduced miss rate n  Early restart and critical-word-first can help

Resume execution as soon as requested word is returned instead of waiting for the entire block.

Transfer requested word first and then transfer remainder of the block.


Cache Misses n  On cache hit, CPU proceeds normally n  On cache miss

n  Stall the CPU pipeline n  Fetch block from next level of hierarchy n  Instruction cache miss

n  Restart instruction fetch

n  Data cache miss n  Complete data access


Write-Through n  On data-write hit, could just update the block in

cache n  But then cache and memory would be inconsistent

n  Write through: also update memory n  But makes writes take longer

n  e.g., if base CPI = 1, 10% of instructions are stores, write to memory takes 100 cycles

n  Effective CPI = 1 + 0.1×100 = 11

n  Solution: write buffer n  Holds data waiting to be written to memory n  CPU continues immediately

n  Only stalls on write if write buffer is already full


Write-Through Cache Hit

Cache

Write buffer

Memory


Write-Back n  Alternative: On data-write hit, just update

the block in cache n  Keep track of whether each block is dirty

n  When a dirty block is replaced n  Write it back to memory n  Can use a write buffer to allow replacing block

to be read first


Write Back Cache Hit

Cache


Write Back Cache Hit

Cache

Write buffer

Memory


Write Allocation n  What should happen on a write miss? n  Alternatives for write-through

n  Allocate on miss: fetch the block and overwrite appropriate portion of block.

n  Write around: don’t fetch the block n  Since programs often write a whole block before

reading it (e.g., initialization)

n  For write-back n  Usually fetch the block

Copyright © 2013, Daniel A. Menasce. All rights reserved.

Cache Basics Summary Introduction

CPU

000 001 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024

MEMORY

CACHE

Read 007

CACHE MISS!



CPU

000 001 003 004

005 006 007 008

009 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024

MEMORY

CACHE

007

005 006 007 008

005 006 007 008



CPU

000 001 003 004

005 006 007 008

009 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024

MEMORY

CACHE

Read 005

005 006 007 008

CACHE HIT!



CPU

000 001 003 004

005 006 007 008

009 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024

MEMORY

CACHE

005

005 006 007 008



CPU

000 001 003 004

005 006 007 008

009 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024

MEMORY

CACHE

Read 018

005 006 007 008

CACHE MISS!



CPU

000 001 003 004

005 006 007 008

009 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024

MEMORY

CACHE

018

005 006 007 008

CACHE MISS!

017 018 019 020

017 018 019 020


Direct-mapped Cache Introduction

000 001 003 004

009 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024

MEMORY

CACHE

005 006 007 008 Block 0 Block 1 Block 2 Block 3 Block 4 Block 5

Memory block 5 can only go into cache block (5 mod 4) = 1 in the cache.

Block 1 Block 2 Block 3

Block 0 SET 0 SET 1 SET 2 SET 3


Fully Associative Cache Introduction

000 001 003 004

009 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024

MEMORY

CACHE


Memory block 3 can go anywhere in the cache.


Block 0


2-Way Associative Cache Introduction

000 001 003 004

009 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024

MEMORY

CACHE


Memory block 3 can only go into set (3 mod 2) = 1 in the cache.


Block 0 SET 0

SET 1


Write-through Introduction

CPU

000 001 003 004

005 006 007 008

009 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024

MEMORY

CACHE

Write 018

005 006 007 008

CACHE HIT!

018

017 018 019 020 Block 1 Block 2 Block 3

Block 0


Write-back – Part I Introduction

CPU

000 001 003 004

005 006 007 008

009 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024

MEMORY

CACHE

Write 018

005 006 007 008

CACHE HIT! 017 018 019 020 Block 1

Block 2 Block 3

Block 0


Write-back – Part II Introduction

CPU

000 001 003 004

005 006 007 008

009 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024

MEMORY

CACHE

Read 024

005 006 007 008

CACHE MISS! 017 018 019 020 Block 1

Block 2 Block 3

Block 0

018


Example: Intrinsity FastMATH n  Embedded MIPS processor

n  12-stage pipeline n  Instruction and data access on each cycle

n  Split cache: separate I-cache and D-cache n  Each 16KB: 256 blocks × 16 words/block n  D-cache: write-through or write-back

n  SPEC2000 miss rates n  I-cache: 0.4% n  D-cache: 11.4% n  Weighted average: 3.2%


Example: Intrinsity FastMATH


Main Memory Supporting Caches n  Use DRAMs for main memory

n  Fixed width (e.g., 1 word) n  Connected by fixed-width clocked bus

n  Bus clock is typically slower than CPU clock

n  Example cache block read n  1 bus cycle for address transfer n  15 bus cycles per DRAM access n  1 bus cycle per data transfer

n  For 4-word block, 1-word-wide DRAM n  Miss penalty = 1 + 4×15 + 4×1 = 65 bus cycles n  Bandwidth = 16 bytes / 65 cycles = 0.25 B/cycle


Measuring Cache Performance n  Components of CPU time

n  Program execution cycles n  Includes cache hit time

n  Memory stall cycles n  Mainly from cache misses

n  With simplifying assumptions:

§5.4 Measuring and Im

proving Cache P

erformance

penalty MissnInstructio

MissesProgram

nsInstructio

penalty Missrate MissProgram

accessesMemory

cycles stallMemory

××=

××=


Cache Performance Example n  Given

n  I-cache miss rate = 2% n  D-cache miss rate = 4% n  Miss penalty = 100 cycles n  Base CPI (ideal cache) = 2 n  Load & stores are 36% of instructions

n  Miss cycles per instruction n  I-cache: 0.02 × 100 = 2 n  D-cache: 0.36 × 0.04 × 100 = 1.44

n  Actual CPI = 2 + 2 + 1.44 = 5.44 n  Ideal CPU is 5.44/2 =2.72 times faster


Memory Impact on Performance n  Speedup the computer by reducing CPI

from 2 to 1 without changing the clock rate. n  CPI with cache misses:

n  1 + 3.44 = 4.44 n  System with perfect cache is 4.44 times faster.

n  Amount of execution time spent on memory stalls would have risen from n  3.44/5.44 = 63% to n  3.44/4.44 = 77%.

n  Amdahl’s Law!


Average Access Time n  Hit time is also important for performance n  Average memory access time (AMAT)

n  AMAT = Hit time + Miss rate × Miss penalty n  Example

n  CPU with 1ns clock, hit time = 1 cycle, miss penalty = 20 cycles, I-cache miss rate = 5%

n  AMAT = 1 + 0.05 × 20 = 2ns n  2 cycles per instruction


Performance Summary n  When CPU performance increased

n  Miss penalty becomes more significant n  Decreasing base CPI

n  Greater proportion of time spent on memory stalls

n  Increasing clock rate n  Memory stalls account for more CPU cycles

n  Can’t neglect cache behavior when evaluating system performance


Associative Caches n  Fully associative

n  Allow a given block to go in any cache entry n  Requires all entries to be searched at once n  Comparator per entry (expensive)

n  n-way set associative n  Each set contains n entries n  Block number determines which set

n  (Block number) modulo (#Sets in cache) n  Search all entries in a given set at once n  n comparators (less expensive)


Associative Cache Example


Spectrum of Associativity n  For a cache with 8 entries


Associativity Example n  Compare 4-block caches

n  Direct mapped, 2-way set associative, fully associative

n  Block access sequence: 0, 8, 0, 6, 8

n  Direct mapped Block

address Cache index

Hit/miss Cache content after access 0 1 2 3

0 0 miss Mem[0] 8 0 miss Mem[8] 0 0 miss Mem[0] 6 2 miss Mem[0] Mem[6] 8 0 miss Mem[8] Mem[6]


Associativity Example n  2-way set associative

Block address

Cache index

Hit/miss Cache content after access Set 0 Set 1

0 0 miss Mem[0] 8 0 miss Mem[0] Mem[8] 0 0 hit Mem[0] Mem[8] 6 0 miss Mem[0] Mem[6] 8 0 miss Mem[8] Mem[6]

n  Fully associative Block

address Hit/miss Cache content after access

0 miss Mem[0] 8 miss Mem[0] Mem[8] 0 hit Mem[0] Mem[8] 6 miss Mem[0] Mem[8] Mem[6] 8 hit Mem[0] Mem[8] Mem[6]


Associativity Example n  2-way set associative

Block address

Cache index

Hit/miss Cache content after access Set 0 Set 1

0 0 miss Mem[0] 8 0 miss Mem[0] Mem[8] 0 0 hit Mem[0] Mem[8] 6 0 miss Mem[0] Mem[6] 8 0 miss Mem[8] Mem[6]

n  Fully associative Block

address Hit/miss Cache content after access

0 miss Mem[0] 8 miss Mem[0] Mem[8] 0 hit Mem[0] Mem[8] 6 miss Mem[0] Mem[8] Mem[6] 8 hit Mem[0] Mem[8] Mem[6]

Used Least Recently Used (LRU) as replacement rule.


How Much Associativity n  Increased associativity decreases miss

rate n  But with diminishing returns

n  Simulation of a system with 64KB D-cache, 16-word blocks, SPEC2000 n  1-way: 10.3% n  2-way: 8.6% n  4-way: 8.3% n  8-way: 8.1%


Set Associative Cache Organization


Replacement Policy n  Direct mapped: no choice n  Set associative

n  Prefer non-valid entry, if there is one n  Otherwise, choose among entries in the set

n  Least-recently used (LRU) n  Choose the one unused for the longest time

n  Simple for 2-way (use a single bit), manageable for 4-way, too hard beyond that

n  Random n  Gives approximately the same performance

as LRU for high associativity


Size of Tags vs. Set Associativity n  Higher associativity èmore comparators,

more tag bits per cache block. n  Example: 4096 blocks in the cache, 4-word

block size, 32-bit address. What is the total number of sets and total number of tag bits for direct mapped caches, 2-way, 4-way, and full-associative caches?





n  Direct mapped cache: n  # blocks = # entries = 4096 è 12 bits for the

index. 16 bytes/block è 4 bits to address byte in a block. è (32 – 12 – 4) = 16 bits/tag

n  # tag bits in the cache = 4096 * 16 = 64 Kbits





n  2-way associative: n  # sets è 4096/2 = 2048. è 11bits for the







n  4-way associative: n  # sets è 4096/4 = 1024. è 10 bits for the







n  Fully associative: n  # sets è 1, 16 bytes/block è 4 bits to

address byte in a block. è (32 – 4) = 28 bits/tag

n  # tag bits in the cache = 28*4096 = 112 Kbits


Size of Tags vs. Set Associativity

Cache type # sets #blocks/set #tag bits #index bits Direct 4096 1 16 12 2-way 2048 2 17 11 4-way 1024 4 18 10 Fully associative

1 4096 28 0


Multilevel Caches n  Primary cache attached to CPU

n  Small, but fast n  Level-2 cache services misses from

primary cache n  Larger, slower, but still faster than main

memory n  Main memory services L-2 cache misses n  Some high-end systems include L-3 cache


Multilevel Cache Example n  Given

n  CPU base CPI = 1, clock rate = 4GHz n  Miss rate/instruction = 2% n  Main memory access time = 100ns

n  With just primary cache n  Miss penalty = 100ns/(0.25ns/cycle)

= 400 cycles n  Effective CPI = 1 + 0.02 × 400 = 9


Example (cont.) n  Now add L-2 cache

n  Access time = 5ns n  Global miss rate to main memory = 0.5%

n  Primary miss with L-2 hit n  Penalty = 5ns/(0.25ns/cycle) = 20 cycles

n  Primary miss with L-2 miss n  Extra penalty = 400 cycles

n  CPI = 1 + 0.02 × 20 + 0.005 × 400 = 3.4 n  Performance ratio = 9/3.4 = 2.6


Multilevel Cache Considerations n  Primary cache

n  Focus on minimal hit time n  L-2 cache

n  Focus on low miss rate to avoid main memory access

n  Hit time has less overall impact n  Results

n  L-1 cache usually smaller than a single cache n  L-1 block size smaller than L-2 block size


Interactions with Advanced CPUs

n  Out-of-order CPUs can execute instructions during cache miss n  Pending store stays in load/store unit n  Dependent instructions wait in reservation

stations n  Independent instructions continue

n  Effect of miss depends on program data flow n  Much harder to analyse n  Use system simulation


Interactions with Software n  Misses depend on

memory access patterns n  Algorithm behavior n  Compiler

optimization for memory access













Software Optimization via Blocking

n  Goal: maximize accesses to data before it is replaced

n  Consider inner loops of DGEMM (C = A x B):

for (int j = 0; j < n; ++j) {

double cij = C[i+j*n];

for( int k = 0; k < n; k++ )

cij += A[i+k*n] * B[k+j*n];

C[i+j*n] = cij; }


DGEMM Access Pattern n  C, A, and B arrays


older accesses

new accesses

Cache Blocked DGEMM 1 #define BLOCKSIZE 32 2 void do_block (int n, int si, int sj, int sk, double *A, double

3 *B, double *C)

4 {

5 for (int i = si; i < si+BLOCKSIZE; ++i)

6 for (int j = sj; j < sj+BLOCKSIZE; ++j)

7 {

8 double cij = C[i+j*n];/* cij = C[i][j] */

9 for( int k = sk; k < sk+BLOCKSIZE; k++ )

10 cij += A[i+k*n] * B[k+j*n];/* cij+=A[i][k]*B[k][j] */

11 C[i+j*n] = cij;/* C[i][j] = cij */

12 }

13 }

14 void dgemm (int n, double* A, double* B, double* C)

15 {

16 for ( int sj = 0; sj < n; sj += BLOCKSIZE )

17 for ( int si = 0; si < n; si += BLOCKSIZE )

18 for ( int sk = 0; sk < n; sk += BLOCKSIZE )

19 do_block(n, si, sj, sk, A, B, C);

20 }


Blocked DGEMM Access Pattern


Unoptimized Blocked


Dependability

n  Fault: failure of a component n  May or may not lead

to system failure

Service accomplishment Service delivered

as specified

Service interruption Deviation from

specified service

Failure Restoration

§5.5 Dependable M

emory H

ierarchy


Dependability Measures n  Reliability: mean time to failure (MTTF) n  Service interruption: mean time to repair (MTTR) n  Mean time between failures

n  MTBF = MTTF + MTTR n  Availability = MTTF / (MTTF + MTTR) n  Improving Availability

n  Increase MTTF: fault avoidance, fault tolerance, fault forecasting

n  Reduce MTTR: improved tools and processes for diagnosis and repair


Dependability Measures

time

failure machine is fixed

MTTR MTTF

MTBF

The Hamming SEC Code n  Hamming distance

n  Minimum number of bits that are different between two bit patterns (e.g., dist. = 2 between 011011 and 00111)

n  Minimum distance = 2 provides single bit error detection n  E.g. parity code

n  Minimum distance = 3 provides single error correction, 2 bit error detection


Parity Bit n  Count the number of ones in a word and

write 1 in the parity bit if the number of ones in the word is odd and 0 if it is even.

n  Word+parity bit always has an even number of 1’s. n  00011111 è par. bit = 1 n  Assume error changes word to 10011111. n  When word is read from memory, the number

of bits in the word + parity bit will be odd è memory error detected!


Encoding SEC n  To calculate Hamming code:

n  Number bits from 1 on the left n  All bit positions that are a power of 2 are parity

bits n  Each parity bit checks certain data bits:


Encoded data bits

Parity bit

coverage

ECC Example n  Hamming code for 10011010? n  _ _ 1 _ 0 0 1 _ 1 0 1 0 n  P1 covers bits 1, 3, 5, 7, 9, 11:

n  _ _ 1 _ 0 0 1 _ 1 0 1 0 => 0 _ 1 _ 0 0 1 _ 1 0 1 0 n  P2 covers bits 2, 3, 6, 7, 10, 11:

n  0 _ 1 _ 0 0 1 _ 1 0 1 0 => 0 1 1 _ 0 0 1 _ 1 0 1 0 n  P4 covers bits 4, 5, 6, 7, 12:

n  0 1 1 _ 0 0 1 _ 1 0 1 0 => 0 1 1 1 0 0 1 _ 1 0 1 0 n  P8 covers bits 8-12:

n  0 1 1 1 0 0 1 _ 1 0 1 0 => 0 1 1 1 0 0 1 0 1 0 1 0 Chapter 5 — Large and Fast: Exploiting Memory Hierarchy — 97

ECC Example n  Error inverts bit 10: 0 1 1 1 0 0 1 0 1 1 1 0 n  P1 covers bits 1, 3, 5, 7, 9, 11:

n  0 1 1 1 0 0 1 0 1 1 1 0 => even group parity n  P2 covers bits 2, 3, 6, 7, 10, 11:

n  0 1 1 1 0 0 1 0 1 1 1 0 => odd group parity! n  P4 covers bits 4, 5, 6, 7, 12:

n  0 1 1 1 0 0 1 0 1 1 1 0 => even group parity n  P8 covers bits 8-12:

n  0 1 1 1 0 0 1 0 1 1 1 0 => odd group parity!


ECC Example n  Error inverts bit 10: 0 1 1 1 0 0 1 0 1 1 1 0 n  P2 covers bits 2, 3, 6, 7, 10, 11:

n  0 1 1 1 0 0 1 0 1 1 1 0 => odd group parity! n  P8 covers bits 8-12:

n  0 1 1 1 0 0 1 0 1 1 1 0 => odd group parity! n  Parity bits 2 and 8 are incorrect => bit 2+8

(10) is incorrect. Flip bit 10: n  0 1 1 1 0 0 1 0 1 0 1 0 => word corrected


Decoding SEC n  Value of parity bits indicates which bits are

in error n  Use numbering from encoding procedure n  E.g.

n  Parity bits = 0000 indicates no error n  Parity bits = 1010 indicates bit 10 was flipped n  Parity bits = 0110 indicates bit 6 was flipped


SEC/DEC Code n  Add an additional parity bit for the whole word

(pn) n  Make Hamming distance = 4 n  Decoding:

n  Let H = SEC parity bits n  H even, pn even, no error n  H odd, pn odd, correctable single bit error n  H even, pn odd, error in pn bit n  H odd, pn even, double error occurred

n  Note: ECC DRAM uses SEC/DEC with 8 bits protecting each 64 bits



Virtual Machines n  Host computer emulates guest operating system

and machine resources n  Improved isolation of multiple guests n  Avoids security and reliability problems n  Aids sharing of resources

n  Virtualization has some performance impact n  Feasible with modern high-performance computers

n  Examples n  IBM VM/370 (1970s technology!) n  VMWare n  Microsoft Virtual PC

§5.6 Virtual Machines

103

Virtualized Environments n  OSs (guest OSs) run in user mode

and the VMM runs in supervisor mode

n  Virtual machines are allocated the CPU based on their priority or assigned CPU shares

n  Examples: VMWare, Xen, IBM LPARs.

OS 1 OS 2

Virtual Machine Monitor

Hardware

App 1 App 2 App

1

App3

App2

aka hypervisor


Virtual Machine Monitor n  Maps virtual resources to physical

resources n  Memory, I/O devices, CPUs

n  Guest code runs on native machine in user mode n  Traps to VMM on privileged instructions and

access to protected resources n  Guest OS may be different from host OS n  VMM handles real I/O devices

n  Emulates generic virtual I/O devices for guest


Use Virtualization in the Cloud n  Data centers that provide Infrastructure as

a Service (IaaS) provide VMs of different prices and types.

n  E.g., Amazon EC2 n  Types:

http://aws.amazon.com/ec2/instance-types/ n  Pricing: http://aws.amazon.com/ec2/pricing/


Example: Timer Virtualization n  In native machine, on timer interrupt

n  OS suspends current process, handles interrupt, selects and resumes next process

n  With Virtual Machine Monitor n  VMM suspends current VM, handles interrupt,

selects and resumes next VM n  If a VM requires timer interrupts

n  VMM emulates a virtual timer n  Emulates interrupt for VM when physical timer

interrupt occurs


Instruction Set Support n  User and System modes n  Privileged instructions only available in

system mode n  Trap to system if executed in user mode

n  All physical resources only accessible using privileged instructions n  Including page tables, interrupt controls, I/O

registers n  Renaissance of virtualization support

n  Current ISAs (e.g., x86) adapting


Virtual Memory n  Use main memory as a “cache” for

secondary (disk) storage n  Managed jointly by CPU hardware and the

operating system (OS) n  Programs share main memory

n  Each gets a private virtual address space holding its frequently used code and data

n  Protected from other programs n  CPU and OS translate virtual addresses to

physical addresses n  VM “block” is called a page n  VM translation “miss” is called a page fault

§5.7 Virtual Mem

ory


Address Translation Example n  Fixed-size pages (e.g., 4K)

220 4K virtual pages = 4-GB virtual address space 218 4K physical pages = 1-GB physical address space


Page Fault Penalty n  On page fault, the page must be fetched

from disk n  Takes millions of clock cycles n  Handled by OS code

n  Try to minimize page fault rate n  Fully associative placement n  Smart replacement algorithms


Page Tables n  Stores placement information

n  Array of page table entries, indexed by virtual page number

n  Page table register in CPU points to page table in physical memory

n  If page is present in memory n  PTE stores the physical page number (aka

frame) n  Plus other status bits (referenced, dirty, …)

n  If page is not present n  PTE can refer to location on paging disk


Mapping Pages to Storage


Translation Using a Page Table the CPU issues virtual

addresses

4K pages è12 bits for page offset


Translation Using a Page Table

Copyright © 2013, D.A. Menasce. All rights reserved.

Virtual Memory Basics Virtual M

emory and Virtual M

achines

Page 0 Page 1 Page 2 Page 3 Page 4 Page 5 Page 6 Page 7 Page 8 Page 9 Page 10 Page 11 Page 12 Page 13 Page 14 Page 15

Paging Disk (process address

space)

Page Frame 0 Page Frame 1 Page Frame 2 Page Frame 3

Main memory

Page Table

VPN Frame Number

… …

Page 0 Page 1 Page 2


A B C D E F G H I J K L M N 0 P

C

0

B

3

P

1

N

2

Virtual Address

VPN Page Offset

Physical Address PFN Page Offset



emory and Virtual M

achines



space)


Main memory

Page Table

VPN Frame Number

… …




C

0

B

3

P

1

N

2

Virtual Address VPN

Page Offset

Physical Address 0 Page Offset

2

-

-



emory and Virtual M

achines



space)


Main memory

Page Table

VPN Frame Number

… …




C

0

B

3

P

1

N

2

Virtual Address VPN

Page Offset

Physical Address Page Offset

14

-

- Page Fault!



emory and Virtual M

achines



space)


Main memory

Page Table

VPN Frame Number

… …




C

0

B

3

P

1

O

2

Virtual Address VPN

Page Offset

Physical Address Page Offset

14

-

-

2


Virtual Memory Example A computer system has 1 GB of main memory and a virtual address space equal to 4 GB. Each page is 8 KB long. How many pages are there in the virtual address space? How many page frames are there in memory? How many bits are needed for the VPN field of an address? How many bits are needed for the page frame bit of an address? How many bits are needed for the page offset field?

Virtual Mem

ory and Virtual Machines


Virtual Memory Example A computer system has 1 GB of main memory and a virtual address space equal to 4 GB. Each page is 8 KB long. How many pages are there in the virtual address space? 4 * 230 / (8 * 210) = 232 / 213 = 219 pages

Virtual Mem


Copyright © 2013, D.A. Menasce All rights reserved.

Virtual Memory Example A computer system has 1 GB of main memory and a virtual address space equal to 4 GB. Each page is 8 KB long. How many page frames are there in memory?

1 * 230 / (8 * 210) = 230 / 213 = 217 page frames

Virtual Mem



Virtual Memory Example A computer system has 1 GB of main memory and a virtual address space equal to 4 GB. Each page is 8 KB long. How many bits are needed for the VPN field of an address?

219 pages => 19 bits

Virtual Mem



Virtual Memory Example A computer system has 1 GB of main memory and a virtual address space equal to 4 GB. Each page is 8 KB long. How many bits are needed for the page frame bit of an address?

217 page frames => 17 bits

Virtual Mem



Virtual Memory Example A computer system has 1 GB of main memory and a virtual address space equal to 4 GB. Each page is 8 KB long. How many bits are needed for the page offset field?

Each page has 23 * 210 = 213 bytes

=> 13 bits are needed for the offset

Virtual Mem



Replacement and Writes n  To reduce page fault rate, prefer least-

recently used (LRU) replacement n  Reference bit (aka use bit) in PTE set to 1 on

access to page n  Periodically cleared to 0 by OS n  A page with reference bit = 0 has not been

used recently n  Disk writes take millions of cycles

n  Block at once, not individual locations n  Write through is impractical n  Use write-back n  Dirty bit in PTE set when page is written


Fast Translation Using a TLB n  Address translation would appear to require

extra memory references n  One to access the PTE n  Then the actual memory access

n  But access to page tables has good locality n  So use a fast cache of PTEs within the CPU n  Called a Translation Look-aside Buffer (TLB) n  Typical: 16–512 PTEs, 0.5–1 cycle for hit, 10–100

cycles for miss, 0.01%–1% miss rate n  Misses could be handled by hardware or software


Fast Translation Using a TLB


TLB Misses n  If page is in memory

n  Load the PTE from memory and retry n  Could be handled in hardware

n  Can get complex for more complicated page table structures

n  Or in software n  Raise a special exception, with optimized handler

n  If page is not in memory (page fault) n  OS handles fetching the page and updating

the page table n  Then restart the faulting instruction


TLB Miss Handler n  TLB miss could indicate

n  Page present, but PTE not in TLB n  Page not present

n  Must recognize TLB miss before destination register overwritten n  Raise exception

n  Handler copies PTE from memory to TLB n  Then restarts instruction n  If page not present, page fault will occur


Page Fault Handler n  Use faulting virtual address to find PTE n  Locate page on disk n  Choose page to replace

n  If dirty, write to disk first (page-out) n  Read page into memory and update page

table (page-in) n  Make process runnable again

n  Restart from faulting instruction


TLB and Cache Interaction n  If cache tag uses

physical address n  Need to translate

before cache lookup

n  Alternative: use virtual address tag n  Complications due to

aliasing n  Different virtual

addresses for shared physical address


Memory Protection n  Different tasks can share parts of their

virtual address spaces n  But need to protect against errant access n  Requires OS assistance

n  Hardware support for OS protection n  Privileged supervisor mode (aka kernel mode) n  Privileged instructions n  Page tables and other state information only

accessible in supervisor mode n  System call exception (e.g., syscall in MIPS)


The Memory Hierarchy

n  Common principles apply at all levels of the memory hierarchy n  Based on notions of caching

n  At each level in the hierarchy n  Block placement n  Finding a block n  Replacement on a miss n  Write policy

§5.8 A Com

mon Fram

ework for M

emory H

ierarchies

The BIG Picture


Block Placement n  Determined by associativity

n  Direct mapped (1-way associative) n  One choice for placement

n  n-way set associative n  n choices within a set

n  Fully associative n  Any location

n  Higher associativity reduces miss rate n  Increases complexity, cost, and access time


Finding a Block

n  Hardware caches n  Reduce comparisons to reduce cost

n  Virtual memory n  Full table lookup makes full associativity feasible n  Benefit in reduced miss rate

Associativity Location method Tag comparisons Direct mapped Index 1 n-way set associative

Set index, then search entries within the set

n

Fully associative Search all entries #entries Full lookup table 0


Replacement n  Choice of entry to replace on a miss

n  Least recently used (LRU) n  Complex and costly hardware for high associativity

n  Random n  Close to LRU, easier to implement

n  Virtual memory n  LRU approximation with hardware support


Write Policy n  Write-through

n  Update both upper and lower levels n  Simplifies replacement, but may require write

buffer n  Write-back

n  Update upper level only n  Update lower level when block is replaced n  Need to keep more state

n  Virtual memory n  Only write-back is feasible, given disk write

latency


Sources of Misses n  Compulsory misses (aka cold start misses)

n  First access to a block n  Capacity misses

n  Due to finite cache size n  A replaced block is later accessed again

n  Conflict misses (aka collision misses) n  In a non-fully associative cache n  Due to competition for entries in a set n  Would not occur in a fully associative cache of

the same total size


Cache Design Trade-offs

Design change Effect on miss rate Negative performance effect

Increase cache size Decrease capacity misses

May increase access time

Increase associativity Decrease conflict misses

May increase access time

Increase block size Decrease compulsory misses

Increases miss penalty. For very large block size, may increase miss rate due to pollution.


Cache Control n  Example cache characteristics

n  Direct-mapped, write-back, write allocate n  Block size: 4 words (16 bytes) n  Cache size: 16 KB (1024 blocks) n  32-bit byte addresses n  Valid bit and dirty bit per block n  Blocking cache

n  CPU waits until access is complete

§5.9 Using a Finite S

tate Machine to C

ontrol A Sim

ple Cache

Tag Index Offset 0 3 4 9 10 31

4 bits 10 bits 18 bits


Interface Signals

Cache CPU Memory

Read/Write Valid

Address

Write Data

Read Data

Ready

32

32

32

Read/Write Valid

Address

Write Data

Read Data

Ready

32

128

128

Multiple cycles per access


Interface Signals

Cache CPU Memory

Read/Write Valid

Address

Write Data

Read Data

Ready

32

32

32

Read/Write Valid

Address

Write Data

Read Data

Ready

32

128

128

Multiple cycles per access

1: memory access needed

32

1: memory operation complete


Finite State Machines n  Use an FSM to

sequence control steps n  Set of states, transition

on each clock edge n  State values are binary

encoded n  Current state stored in a

register n  Next state

= fn (current state, current inputs)

n  Control output signals = fo (current state)


Cache Controller FSM

Could partition into separate

states to reduce clock

cycle time


Cache Coherence Problem n  Suppose two CPU cores share a physical

address space n  Write-through caches

§5.10 Parallelism

and Mem

ory Hierarchies: C

ache Coherence

Time step

Event CPU A’s cache

CPU B’s cache

Memory

0 0

1 CPU A reads X 0 0

2 CPU B reads X 0 0 0

3 CPU A writes 1 to X 1 0 1


Coherence Defined n  Informally: Reads return most recently

written value n  Formally:

n  P writes X; P reads X (no intervening writes) ⇒ read returns written value

n  P1 writes X; P2 reads X (sufficiently later) ⇒ read returns written value

n  c.f. CPU B reading X after step 3 in example n  P1 writes X, P2 writes X ⇒ all processors see writes in the same order

n  End up with the same final value for X


Cache Coherence Protocols n  Operations performed by caches in

multiprocessors to ensure coherence n  Migration of data to local caches

n  Reduces bandwidth for shared memory n  Replication of read-shared data

n  Reduces contention for access

n  Snooping protocols n  Each cache monitors bus reads/writes

n  Directory-based protocols n  Caches and memory record sharing status of

blocks in a directory


Invalidating Snooping Protocols n  Cache gets exclusive access to a block

when it is to be written n  Broadcasts an invalidate message on the bus n  Subsequent read in another cache misses

n  Owning cache supplies updated value

CPU activity Bus activity CPU A’s cache

CPU B’s cache

Memory

0 CPU A reads X Cache miss for X 0 0 CPU B reads X Cache miss for X 0 0 0 CPU A writes 1 to X Invalidate for X 1 0 CPU B read X Cache miss for X 1 1 1


Memory Consistency n  When are writes seen by other processors

n  “Seen” means a read returns the written value n  Can’t be instantaneously

n  Assumptions n  A write completes only when all processors have seen

it n  A processor does not reorder writes with other

accesses n  Consequence

n  P writes X then writes Y ⇒ all processors that see new Y also see new X

n  Processors can reorder reads, but not writes


Multilevel On-Chip Caches §5.13 The A

RM

Cortex-A

8 and Intel Core i7 M

emory H

ierarchies


2-Level TLB Organization


Supporting Multiple Issue n  Both have multi-banked caches that allow

multiple accesses per cycle assuming no bank conflicts

n  Core i7 cache optimizations n  Return requested word first n  Non-blocking cache

n  Hit under miss n  Miss under miss

n  Data prefetching

DGEMM n  Combine cache blocking and subword

parallelism


§5.14 Going Faster: C

ache Blocking and M

atrix Multiply


Pitfalls n  Byte vs. word addressing

n  Example: 32-byte direct-mapped cache, 4-byte blocks

n  Byte 36 maps to block 1 n  Word 36 maps to block 4

n  Ignoring memory system effects when writing or generating code n  Example: iterating over rows vs. columns of

arrays n  Large strides result in poor locality

§5.15 Fallacies and Pitfalls


Pitfalls n  In multiprocessor with shared L2 or L3

cache n  Less associativity than cores results in conflict

misses n  More cores ⇒ need to increase associativity

n  Using AMAT to evaluate performance of out-of-order processors n  Ignores effect of non-blocked accesses n  Instead, evaluate performance by simulation


Pitfalls n  Extending address range using segments

n  E.g., Intel 80286 n  But a segment is not always big enough n  Makes address arithmetic complicated

n  Implementing a VMM on an ISA not designed for virtualization n  E.g., non-privileged instructions accessing

hardware resources n  Either extend ISA, or require guest OS not to

use problematic instructions


Concluding Remarks n  Fast memories are small, large memories are

slow n  We really want fast, large memories L n  Caching gives this illusion J

n  Principle of locality n  Programs use a small part of their memory space

frequently n  Memory hierarchy

n  L1 cache ↔ L2 cache ↔ … ↔ DRAM memory ↔ disk

n  Memory system design is critical for multiprocessors

§5.16 Concluding R

emarks

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