The integrated Development of Embedded linux and SOC IP

吳奇峰新華電腦股份有限公司

應用工程師

Topics

• SOC 系統發展流程

• FPGA 發展工具

• SOPC Builder 流程

SOC 嵌入式系統開發流程System Requirement

Components,

IP Sourcing

CO-simulation

H/W & S/W adoption trade-off by verification

Product

Design Specification

H/W & S/W

partitioning

H/W Design synthesis

S/W Design

CompilerICE

Debugger

OS

IC Tool

Creator Motherboard

• Memory: 2M Bytes Flash Memory 、 16M Bytes SDRAM 、 EEPROM• Communication: UART 、 Ethernet 、 USB 1.1 、 I2C• Human-Machine Interface: Codec 、 CMOS Camera 、Ｋ eypad 、 LED 、 7-Seg 、　 DIP

Switch 、 LCD• Master and Slave Bus for daughter board Changeab

le: Create S3C4510 (ARM7TDMI) Create ARM920T-S3C2410 Create ARM922T-EPXA1 (for SOPC) Create FPGA-EP1C6 Create FPGA-XC2S Create TIDSP-5502

Create FPGA-EP1C6

• FPGA:

EP1C6;BQ240(5980LEs)

• Codec:

Stereo out

Microphone in

• 8-Bit serial I/O ADC with 2-channel multiplexed

• SRAM:128K*8-Bit

• 7-Seg LED

• 9 LED Lamps

• 4-Way DIP Swich

• 1 Tag Switch

• 1 DC Buzzer for tone generation

Create FPGA-EP1C6• PS2 Connector

• Build-in Altera ByteBlasterMV Parallel Port download cable header circuit

• Extension connector

27 pins for memory interface

50 pins for user definable I/O

One 8-Bit ADC input

4 Pins Codec I/O

5V DC output

• Slave Bus

Communicate with Master Bus site CPU

Keypad Switch 、 UART interface

Create FPGA-EP1C6 Block Diagram

DIP-SW

LED

7-Seg

PS2

Buzzer

A2D

CODEC

Cyclone

EP1C6

FPGA

Expansion I/O

Buffer

Clock

SRAM

Regulator

Config

CKT

Creator

BUS

(Slave Bus)

ICE

PC

MIC

STEREO

VR

Create FPGA-XC2S• FPGA:

XC2S,PQ208(200K gate counts)

• Codec:

16-Bit, 26-KSPS,TLV320AIC12

Built-in Microphone

• 8-Bit serial I/O ADC with 2-channel multiplexer

• SRAM:

128K*8Bit

• 7-Seg LED

• 9 LED Lamps

• 4-Way DIP Switch

• 1 Tag Switch

Create FPGA-XC2S

• PS2 Connector• Build-in Xilinx download cable h

eader circuit• Extension connector 27 pins for memory interface 10 pins for user definable I/O One 8-Bit ADC input One 16-Bit Codec Aux input 5V DC output• Slave Bus Communicate with Master Bus site CPU

Keypad Switch UART interface

Create FPGA-XC2S Block Diagram

DIP-SW

LED

7-Seg

PS2

Buzzer

A2D

CODEC

Spartan-IIFPGA

Expansion I/O

Buffer

Clock

SRAM

Regulator

ConfigCKT

CreatorBUS

(Slave Bus)

ICE

PC

MIC

STEREO

VR

Creator Mother Board

FPGA

Config.

UART

Key Pad

Power

Master Bus (CPU)

Slave Bus

Address Bus

Data Bus

I/O

IRQ

DMA

Controls

Creator Bus Communication

TI DSP

5502

S3C4510

(ARM7TDMI)ARM920T

S3C2410ARM922T

EPXA1

(for SOPC)

Create ARM922T-EPXA1

• CPU:EPXA1F484C3

ARM922T Core

100K Gate Count FPGA

• 10/100 Ethernet

• Master Bus

• Two Clock Sources

• 8M-Byte Flash Memory

• 32M-Byte SDRAM

• 8 LED Lamps

• 4-Way DIP switch

• 1 Tag Switch

Create ARM922T-EPXA1• 4 extension connectors for wire

wrap board or special hardware module

Totally 118 I/O pins

3 Clock Output pins

2 Fast input pins

5V DC Output

• Header for ARM ICE JTAG Connector

• Header for Altera Byte Blaster MV download cable

• Running Linux,Linux open source codes provided

Create ARM922T-EPXA1 Board Architecture

EPXA1 Control

EPXA1 PLD

EPXA1ARM-Strip

Extension I/O

LED/DIP SW/TAG SW

SDRAM Flash Ethernet

ARM

JTAG

PLD

JTAG

POWER

Clocks

Creator Motherboard

Master BusJH1 JH2

Create ARM922T-EPXA1

Excalibur ARM Configuration

WatchdogTimer

Phase-Locked

Loop (PLL)

AHB 1-2Bridge

Dual-Port SRAM

SDRAMController

Single--Port SRAM

ARM922T Processor

Interrupt Controller

AHB1

AHB2

SDRAM SRAMFlash

ConfigurationLogic Master

Reset Module

Timer

UARTExpansion

Bus Interface (EBI)

ROM

Excalibur Hard Processor

External Devices

IP

PLD-to-Stripe Bridge

Programmable Logic Master

Peripheral

ProgrammableLogic SlavePeripheral

Stripe-to-PLD

Bridge

ProgrammableLogic SlavePeripheral

Programmable Logic Module

Programmable Logic

Module

FPGA Logic

ConfigurationRegister

AHB

AHB: AMBA™ High-Performance Bus

AHB

SOPC Builder Flow SOPC Builder FlowSOPC Builder GUI

Connect Blocks

Processor Library Custom Instructions

Peripheral Library Select & Configure Peripherals, IP

IP Modules

Configure Processor

C Header files

Custom Library

Peripheral Drivers

GNUPro CompilerIAR ARM Compiler

uClinux/Linux

Software Development

User Code

Libraries

OS(Kernel……..

Software Tools

Generate

EDIF Netlist

HDL Source Files

Testbench

Synthesis &Fitter

User Design

Other IP Blocks

Hardware Development

Quartus IICREAEARM922TEXPA1

Microtime Carrier ICE

ExecutableCode

HardwareConfiguration

FileVerification

& Debug

Intellectual PropertyIntellectual Property

JTAG

DomingoDebugger

For uClinux/Linux