Thesis.pdf

TRNG I HC BCH KHOA H NI

VIN IN T - VIN THNG

-*-

BI TP LN VLSI

KHI D ON CHUYN NG LIN NH TRONG NN VIDEO

GVHD: TS. Nguyn V Thng

Nhm thc hin:

Vit Ho TVT 3 K55 20101033

V Duy Sn TVT 3 K55 20102112

Nghim L Hoa TVT 4 K55 20101551

Hong Tng Anh TVT 10 K55 20101074

Phm Th Huy TVT 10 K55 20101625

H Ni, 05/2014

THIT K ASIC KHI D ON CHUYN NG LIN NH TRONG NN VIDEO

2

LI NI U

Thit k VLSI l mn hc chuyn ngnh quan trng trong chng trnh o to

ca sinh vin in t Vin thng ni chung cng nh chng trnh in t v K

thut my tnh ni ring. Mn hc cung cp nhng kin thc c bn nht v thit k

ASIC, s dng ngn ng m t phn cng Verilog cng b cng c thit k, tng hp

mnh m Synopsys.

Bi tp ln l mt cch tip cn vi nhng kin thc hc c trn lp mt cch

nhanh chng v hu hiu nht, ng thi sinh vin c c hi tri nghim vi nhng

yu cu thit k, tng hp cht ch nht thc hin mt chc nng c th no . Bn

cnh , thc hin bi tp ln cng l mt cch gip sinh vin rn luyn nhng k

nng mm nh k nng lp k hoch, k nng lm vic nhm, kh nng t duy c

lp v kh nng iu tit lng cng vic.

Khi d on chuyn ng lin nh trong nn video c s dng rt rng ri

trong thc t v c tch hp vo nhiu h thng x l phc tp khc. Thit k khi

d on chuyn ng lin nh trong nn video l mt trong nhng kha cnh trng

yu trong thit k ASIC. Trong bi tp ln ny, chng em s d on chuyn ng

lin nh trong nn video vi khung nh nh dng 640x480, s dng qut ton khung

nh tham chiu.

Chng em xin chn thnh cm n TS. Nguyn V Thng v KS. Nguyn Nam

Phong nhit tnh ging dy, hng dn v gii p thc mc ca chng em trong

qu trnh thc hin bi tp ln ny cng nh vic hc tp trn lp c thun li.


3

MC LC

Li ni u .................................................................................................................. 2

Mc lc ........................................................................................................................ 3

Danh mc hnh nh ..................................................................................................... 5

Danh mc bng biu .................................................................................................... 8

1. Tng quan ................................................................................................................ 9

1.1. Gii thiu tng ............................................................................................ 9

1.2. K hoch thc hin ........................................................................................... 9

2. c t chi tit ........................................................................................................ 11

2.1. Cc khi nim ................................................................................................. 11

2.2. Chc nng ca mch ...................................................................................... 12

2.3. Cc yu cu phi chc nng ............................................................................. 15

3. Thit k kim th .................................................................................................. 16

3.1. Kim th h thng .......................................................................................... 16

3.2. Kim th tng khi ........................................................................................ 18

4. Thit k thut ton v kin trc ............................................................................. 19

4.1. tng thut ton .......................................................................................... 19

4.2. Thit k thut ton .......................................................................................... 22

4.3. Thit k kin trc ........................................................................................... 24

5. Thit k RTL ......................................................................................................... 26

5.1. Khi iu khin (control_unit) ....................................................................... 26

5.2. Khi b m khung hnh hin ti (curr_mem) ............................................... 29

5.3. Khi b m khung hnh tham chiu (ref_mem) ........................................... 30

5.4. Khi tnh ton tng tr tuyt i sai khc SAD (sad_calc64) ........................ 32

5.5. Khi tnh ton vector chuyn ng (mv_calc) ............................................... 33

5.6. Khi so snh (comp_unit.v) ........................................................................... 34

6. Kim th chc nng .............................................................................................. 37

6.1. Check li code: ............................................................................................... 37

6.2. M phng trc khi tng hp mch ............................................................... 45

7. Tng hp ............................................................................................................... 47

8. Kim th sau tng hp .......................................................................................... 66


4

8.1. Kim th chc nng sau tng hp ................................................................. 66

8.2. Kim th thi gian sau tng hp .................................................................... 68

9. Kim tra tnh tng ng .................................................................................... 69

10. Phn tch thi gian trc layout .......................................................................... 76

11. Layout.................................................................................................................. 80

12. Kim th sau layout ............................................................................................ 95

13. Phn tch thi gian sau layout ............................................................................. 96

14. Kt lun ............................................................................................................... 98

14.1. Kt qu ......................................................................................................... 98

14.2. Nhn xt ....................................................................................................... 98

Ti liu tham kho ..................................................................................................... 99


5

DANH MC HNH NH

Hnh 2.1. Giao din giao tip ca mch .............................................................. 12

Hnh 2.2. S thi gian cc tn hiu ng b ................................................... 13

Hnh 2.3. S thi gian ca qu trnh c b nh ........................................... 14

Hnh 2.4. S thi gian ca cc tin hiu kt qu tnh ton .............................. 14

Hnh 3.1. Kim th t ng ................................................................................ 18

Hnh 4.1. Qut khi 8x8 trn khung hnh tham chiu ......................................... 19

Hnh 4.2. S dng thanh ghi dch qut, mi bc dch c 8 pixel nh ........ 20

Hnh 4.3. S dng thanh ghi dch lu 8 dng, mi bc dch c 1 pixel ......... 20

Hnh 4.4. Qut khung hnh tham chiu tn dng gi tr hai bin ........................ 21

Hnh 4.5. Qut khung hnh tham chiu tn dng gi tr hai bin ........................ 21

Hnh 4.6. Kin trc chung ca mch ................................................................... 24

Hnh 5.1. S khi iu khin ......................................................................... 26

Hnh 5.2. S khi b m khung hnh hin ti .............................................. 29

Hnh 5.3. S khi b m khung hnh tham chiu ........................................ 30

Hnh 5.4. S khi tnh ton SAD ................................................................... 32

Hnh 5.5. S tnh gi tr SAD theo kin trc pipeline .................................... 33

Hnh 5.6. S khi tnh ton vector chuyn ng ........................................... 33

Hnh 5.7. S tnh ton vector chuyn ng theo kin trc pipeline ............... 34

Hnh 5.8. S khi so snh .............................................................................. 34

Hnh 6.1. Ca s to project trong Leda ............................................................. 37

Hnh 6.2. Ca s t tn cho project ................................................................... 38

Hnh 6.3. Chn phin bn cho Verilog ............................................................... 39

Hnh 6.4. Xc nh ng dn th vin cn dng .............................................. 40

Hnh 6.5. Xc nh ng dn source code ........................................................ 41

Hnh 6.6. Ca s kt thc to project .................................................................. 42

Hnh 6.7. Ca s xc nh top module ................................................................ 43

Hnh 6.8. Thit lp clock v reset ....................................................................... 44

Hnh 6.9. Ca s cui cng thng bo cc li .................................................... 45

Hnh 6.10. Chn xem dng sng ca top module ............................................... 46

Hnh 6.11. Ca s dng sng .............................................................................. 46


6

Hnh 6.12. Kt qu m phng dng sng ............................................................ 47

Hnh 7.1. Ca s thit lp ................................................................................... 48

Hnh 7.2. Chn ng dn dn n th vin tng hp ....................................... 49

Hnh 7.3. To th vin Milkyway ....................................................................... 50

Hnh 7.4 ............................................................................................................... 51

Hnh 7.5. Thm cc file code .............................................................................. 51

Hnh 7.6. Chn top module ................................................................................. 52

Hnh 7.7. Xem s khi ................................................................................... 52

Hnh 7.8. S nguyn l trc tng hp .......................................................... 53

Hnh 7.9. Ca s kim tra li .............................................................................. 53

Hnh 7.10. To clock v thit lp cc thng s clock ......................................... 54

Hnh 7.11. Thit lp tr u vo.......................................................................... 55

Hnh 7.12. Lu lch s s dng lnh trong DC ................................................... 65

Hnh 7.13. Lu file TCL ..................................................................................... 65

Hnh 8.1. Chn tn hiu xem th sng ............................................................ 67

Hnh 8.2. th sng m phng chc nng sau tng hp .................................. 67

Hnh 8.3. th sng m phng c tr sau tng hp ......................................... 68

Hnh 9.1. Giao din khi ng Formality ........................................................... 69

Hnh 9.2. Np Guidance file ............................................................................... 70

Hnh 9.3. Chn tt c cc file thit k (tr testbench) ........................................ 70

Hnh 9.4. Thit lp top module ca thit k ........................................................ 71

Hnh 9.5. Np file thit k sau khi tng hp ....................................................... 71

Hnh 9.6. Np file th vin ................................................................................. 72

Hnh 9.7. Bt u kim tra tnh tng ng ....................................................... 72

Hnh 9.8. Kt qu kim tra tnh tng ng ....................................................... 73

Hnh 9.9. Verify thit k ..................................................................................... 73

Hnh 9.10. Passing Points ................................................................................... 74

Hnh 10.1. Giao din phn mm Prime Time ..................................................... 77

Hnh 10.2. Xut file coverage report................................................................... 77

Hnh 10.3. To timing report .............................................................................. 78

Hnh 10.4. Xut bo co ng c tr nh nht ................................................. 79


7

Hnh 11.1. M th vin Milkyway to sn trc khi tng hp ..................... 80

Hnh 11.2. c file thit k DDC ....................................................................... 81

Hnh 11.3. c file rng buc thit k SDC. ...................................................... 81

Hnh 11.4. Giao din thit k layout ................................................................... 82

Hnh 11.5. To nn .............................................................................................. 83

Hnh 11.6. Thit k sau khi to nn .................................................................... 83

Hnh 11.7. Cc cell c xp pha ngoi nn to .......................................... 84

Hnh 11.8. To chn ngun v t ...................................................................... 84

Hnh 11.9. To vng dy VDD ........................................................................... 85

Hnh 11.10. To vng dy VSS .......................................................................... 85

Hnh 11.11. Cc vng dy VDD v VSS xung quanh thit k ........................... 85

Hnh 11.12. Thit lp rng vng dy VDD ................................................... 86

Hnh 11.13. Thit lp rng vng dy VSS ..................................................... 86

Hnh 11.14. To vng m.................................................................................. 86

Hnh 11.15. Xp linh kin t ng ...................................................................... 87

Hnh 11.16. Mch sau khi xp linh kin ............................................................. 88

Hnh 11.17. To mng clock ............................................................................... 89

Hnh 11.18. Mng clock c to ra ................................................................... 90

Hnh 11.19. Tn hiu clock c a ti tng cell ............................................. 90

Hnh 11.20. i dy t ng ................................................................................. 91

Hnh 11.21. Ti nguyn x l ca h thng c tn dng ti a ...................... 92

Hnh 11.22. Thit k hon chnh sau khi i dy ................................................. 93

Hnh 11.23. Extract RC ....................................................................................... 93


8

DANH MC BNG BIU

Bng 1.1. Cc mc thi gian cn t c ca d n ........................................... 9

Bng 1.2. Phn cng cng vic chi tit ................................................................. 9


9

1. TNG QUAN

1.1. Gii thiu tng

D on chuyn ng lin nh (Motion Estimation) l mt trong nhng cng on

quan trng trong nn video. Thut ton cho php tm ra khi nh ging nht gia 2

khung hnh, nhm gim thiu lng d liu cn m ho v lu tr. Mt trong cc

thut ton tm vector chuyn ng (Motion vector) l thut ton Full-Search (duyt

vt cn).

Trong bi tp ln ny, nhm thc hin vic thit k ASIC khi d on chuyn

ng lin nh gia 2 khung hnh c lu trong b nh. Qu trnh tm kim c

din ra trong ton khung hnh.

1.2. K hoch thc hin

1.2.1. Milestones

Bng 1.1. Cc mc thi gian cn t c ca d n

STT Milestone Thi gian

1 Hon thnh c t chi tit 26/02/2014

2 Hon thnh phc tho thit k thut ton v thit k

s khi

12/03/2014

3 Hon thnh code RTL 19/03/2014

4 Hon thnh ton b cng vic, bo v ln 1 23/04/2014

1.2.2. Phn chia cng vic

Cng vic c phn cng da trn cc giai on ca quy trnh thit k, cng nh

vic phn chia thit k thnh cc khi nh. C th nh sau:

Bng 1.2. Phn cng cng vic chi tit

STT Cng vic Deps. Thc hin Khi lng

1 Vit c t chi tit Vit Ho 7 ngy


10

2 Thit k thut ton

Thit k s khi

1 Nghim L Hoa

Vit Ho

14 ngy

3 Thit k RTL v kim th

tng khi

2 C nhm 21 ngy

3.1 Khi iu khin Nghim L Hoa

V Duy Sn

5 ngy

3.2 Khi b nh m block hin

ti

Hong Tng Anh

Phm Th Huy

2 ngy

3.3 Khi b nh m block

tham chiu

Vit Ho

Nghim L Hoa

14 ngy

3.4 Khi tnh ton SAD Vit Ho

V Duy Sn

7 ngy

3.5 Khi tm gi tr nh nht Hong Tng Anh

Phm Th Huy

5 ngy

3.6 Thanh ghi dch SISO Hong Tng Anh

Phm Th Huy

2 ngy

3.7 Thit k chnh (top module) 3.1,2..6 V Duy Sn 2 ngy

3.8 Testbench h thng Vit Ho 5 ngy

4 Sa code, thc hin cc

bc front-end (m phng,

tng hp)

3 C nhm 14 ngy

5 Sa code, thc hin cc

bc back-end

4 C nhm 3 ngy

6 Tng hp kt qu

Vit bo co

5 C nhm 5 ngy


11

2. C T CHI TIT

2.1. Cc khi nim

2.1.1. To im v to khi

To im c tnh t 0, tc l = 0, 1, ; = 0, 1, .

To (, ) ca mt khi l to ca pixel trn cng bn tri ca khi (tc

l pixel c v nh nht trong khi).

2.1.2. Tng tr tuyt i sai khc

Tng tr tuyt i sai khc (Sum of Absolute Difference SAD) l gi tr th hin

mc khc nhau ca 2 nh vi cng kch thc, c tnh bng cng thc:

= |(, )|

,

Trong (, ) = (, ) (, ) l hiu gi tr

chi ca 2 im nh tng ng trn 2 khung hnh.

Khi no trong khung hnh tham chiu c gi tr SAD nh nht l khi ging

nht vi khi ang xt ti khung hnh hin ti.

2.1.3. Vector chuyn ng

Vector chuyn ng (Motion Vector) ca mt khi l vector th hin lch ca

khi trn khung hnh tham chiu ging vi khi ang xt nht so vi khi ang xt

trn khung hnh hin ti.

Gi s ang xt khi c to (0, 0) trn khung hnh hin ti, tm c khi

c to (, ) trn khung hnh tham chiu c gi tr SAD nh nht, khi vector

chuyn ng c tnh theo cng thc:

= ( 0, 0)


12

2.2. Chc nng ca mch

Mch c chc nng d on chuyn ng (Motion Estimation), c 2 khung hnh:

khung hnh hin ti v khung hnh tham chiu t b nh, xt tng khi (Block) trong

khung hnh hin ti v a ra khi trong khung hnh tham chiu ging khi ang xt

trong khung hnh hin ti nht thng qua tng tr tuyt i sai khc (Sum of Absolute

Difference SAD) nh nht v vector chuyn ng (Motion Vector) ng vi SAD .

2.2.1. Cc tham s ca mch

phn gii khung hnh: 640480.

Kch thc mi khi: 88.

Mi im (pixel) c biu din bng mt gi tr chi 8-bit.

2.2.2. Cc tn hiu

Cc tn hiu vo/ra ca mch c m t bi Hnh .

Hnh 2.1. Giao din giao tip ca mch

Cc tn hiu c chia lm 4 nhm:

Cc tn hiu ng b

Giao tip b nh cha khung hnh hin ti

Giao tip b nh cha khung hnh tham chiu


13

Kt qu tnh ton

a) Cc tn hiu ng b

L nhm cc tn hiu c chc nng ng b mch tun t, bao gm:

STT Tn hiu KT Loi M t

1 clk

1 Vo Xung nhp ng h, ng b theo sn

ln

2 rst

1 Vo Reset ng b, tch cc mc cao

3 en 1 Vo Cho php mch hot ng

S thi gian ca cc tn hiu ng b c cho Hnh . Trc khi hot ng

mch cn reset (a tn hiu reset ln mc 1 ti sn ln ca xung ng h) v cp

mc logic 1 cho tn hiu enable cho php mch hot ng.

clk

rst

...

en

Hnh 2.2. S thi gian cc tn hiu ng b

b) Cc tn hiu giao tip b nh

Mch cn giao tip vi 2 khi b nh: b nh cha khung hnh hin ti v b nh

cha khung hnh tham chiu. Cc tn hiu giao tip vi b nh khung hnh hin ti c

tin t curr_, cc tn hiu giao tip b nh khung hnh tham chiu c tin t ref_.


1 curr_x, ref_x 10 Ra To ca im nh cn c gi tr

2 curr_y, ref_y 9 Ra To ca im nh cn c gi tr

3 curr_den, ref_den

1 Ra Tn hiu bo c d liu t b nh nh,

tch cc mc cao


14

4 curr_data, ref_data

8 Vo Gi tr im nh tr v t b nh

clk

curr_x, curr_y

ref_x, ref_y

curr_data

ref_datax

...

...

x

x

curr_den

ref_den

...

Hnh 2.3. S thi gian ca qu trnh c b nh

B nh cn thit k sao cho c th c d liu trong 1 chu k xung nhp.

c) Cc tn hiu kt qu tnh ton

Kt qu tnh ton c a ra bng cc tn hiu sau:


1 sad 14 Ra Gi tr SAD tng ng vi khi ang xt

(khi c a ch curr_addr)

2 mv_x 11 Ra To ca vector chuyn ng tng

ng vi khi ang xt.

3 mv_y 10 Ra To ca vector chuyn ng tng

ng vi khi ang xt.

4 curr_addr 13 Ra a ch ca khi ang xt

clk ...

rst

curr_addr x ...

en

sad

mv_x, mv_yx ...

Hnh 2.4. S thi gian ca cc tin hiu kt qu tnh ton

D liu ra bao gm 2 thnh phn: a ch ca khi v cc gi tr SAD, . Qu

trnh tnh ton cn din ra trong mt s chu k xung nhp nht nh, gi tr a ch s


15

c gi nguyn trong sut qu trnh tnh ton v ch thay i khi bt u xut d

liu ca khi tip theo. Gi tr ng s l gi tr a ra cui cng ng vi mi a ch.

2.3. Cc yu cu phi chc nng

Mch c thit k m bo cc ch tiu k thut phi chc nng nh sau:

Tn s hot ng: 500 MHz.

Kch thc: (cha c lng).


16

3. THIT K KIM TH

Cc bi kim th c thit k nhm m bo thit k t nhng yu cu ra

ca c t chi tit cng nh yu cu thit k ca tng khi. C 2 qu trnh kim th

c thc hin:

Kim th h thng: c thc hin sau khi tt c cc khi c ghp

li thnh cng, nhm m bo mch hot ng ng vi c t chi tit

ra.

Kim th tng khi: c thc hin cng vi qu trnh thit k chi tit

tng khi, nhm m bo tng khi nh trong h thng hot ng ng

vi thit k v thut ton ra.

3.1. Kim th h thng

Cc bi kim th h thng c thit k da trn c t chi tit ca h thng, song

song v khng ph thuc vo thut ton cng nh thit k RTL. Mc tiu ca ca

kim th h thng l m bo mch hot ng ng vi c t chi tit ra.

3.1.1. Thit k b test

a) Cu trc b test

Cc b test c sinh ra bng cc chng trnh nh vit bng ngn ng lp trnh

C, bao gm:

D liu b nh khung hnh hin ti, c xut ra di dng danh sch

tng byte d liu dng thp phn, tng ng vi tng pixel ca khung

hnh theo th t t tri sang phi, t trn xung di.

D liu b nh khung hnh tham chiu, c nh dng ging vi d liu b

nh khung hnh hin ti.

Cc gi tr u ra (SAD, vector chuyn ng) ng vi tng khi nh, c

xut ra di dng danh sch tng gi tr c phn sch nhau bi khong

trng, mi khi nh mt dng.

b) Phn loi b test

C 2 loi test c to ra vi cc mc ch khc nhau:


17

Test bit trc kt qu: b test c sinh t ng nhng vi nh sn,

m bo bit trc kt qu. Loi test ny khng ch c s dng kim

th thit k m cn dng kim th chnh chng trnh sinh test, m

bo chng trnh ny hot ng ng.

Test ngu nhin: b test c sinh t ng vi cc gi tr ngu nhin, kt

qu u ra c tnh ton t ng bng chng trnh sinh test. B test ny

dng kim th thit k.

c) Cc b test

Qu trnh kim th h thng din ra rt lu v phc tp, v th ch c 2 b test

c to ra tng ng vi 2 loi test c cp pha trn:

Test bit trc kt qu:

o Khung hnh hin ti: tt c cc pixel u c gi tr bng 1.

o Khung hnh tham chiu: c mt khi 88 duy nht to

(, ) = (22, 11) c gi tr cc pixel l 1, cc pixel cn li c gi

tr bng 0.

o Kt qu mong mun: tt c cc gi tr SAD u bng 0 v cc vector

chuyn ng u tr n to (, ) = (22, 11).

Test ngu nhin: cc gi tr c sinh ra ngu nhin v u ra c tnh

ton da trn chng trnh sinh test.

3.1.2. Kim th t ng

Qu trnh kim th h thng c thc hin thng qua testbench c vit bng

Verilog thc hin test t ng v thng bo kt qu ra mn hnh. Testbench ny s

c cc file d liu u vo c to sn phc v cho thit k thc thi, ng

thi ly gi tr u ra ca thit k so snh vi u ra chun ca b test.


18

THIT KD LIU VO D LIU RA

TESTBENCH

TR

NG

TH

IH

TH

NG

Hnh 3.1. Kim th t ng

Testbench cn c thit k c kh nng ly ra cc gi tr d liu nm trong thit

k trong qu trnh m phng nhm mc ch g li mch khi kt qu kim th khng

t yu cu.

3.2. Kim th tng khi

Kim th tng khi c thc hin i vi mi module trong mch trong qu

trnh code, m bo thit k hoch ng ng vi yu cu ca mi khi. Qu trnh

kim th ny c thc hin bng cc testbench n gin, a d liu c nh sn

vo thit k cn kim tra v hin th gi tr cc tn hiu cn thit ra mn hnh.

Khi pht hin ra li xy ra (tn hiu ra c gi tr khng ng vi yu cu ban u),

s sng (waveform) c s dng phc v cho vic g li.


19

4. THIT K THUT TON V KIN TRC

4.1. tng thut ton

tha mn yu cu bi ton a ra, vn quan trng nht i vi vic thit

k phn cng l thut ton qut khi 8x8 trong hai khung hnh hin ti v khung hnh

tham chiu. Nhm a ra cch qut hai khung hnh nh sau:

i vi khung hnh hin ti:

640

480

Hnh 4.1. Qut khi 8x8 trn khung hnh tham chiu

Chia khung hnh 640x480 thnh cc khi 8x8.

Bt u qut khi 8x8 u tin trn cng bn tri, ta (0, 0).

Tip tc qut cc khi 8x8 t tri sang phi v t trn xung di.

Khung hnh tham chiu c 3 cch qut nh sau:

Cch 1


20

0xFF

0xF

F

640

480

7

480 + 7

Hnh 4.2. S dng thanh ghi dch qut, mi bc dch c 8 pixel nh

Vi cch qut tng khi 8x8 t tri sang phi, t trn xung di, mi khi 8x8

tip theo khc khi 8x8 trc 8 pixel th mi ln qut phi a 8 gi tr pixel mi

vo b nh.

Cch 2

0xFF

0xF

F

640

480

7

480 + 7

Hnh 4.3. S dng thanh ghi dch lu 8 dng, mi bc dch c 1 pixel

S dng mt ca s kch thc (640 + 7) 8 thc hin qut ln lt t trn

xung di, mi khi 8x8 bn trong ca s ny s c dch t tri sang phi. Nh

vy mi ln qut, khi 8x8 tip theo ch khc khi 8x8 trc 1 pixel nn ch phi

a 1 gi tr pixel mi vo.


21

Cch 3:

0xFF

0xF

F0

xFF

640

480

7

480 + 7

Hnh 4.4. Qut khung hnh tham chiu tn dng gi tr hai bin

480

640 7

480 + 7

0xFF

0xF

F

Hnh 4.5. Qut khung hnh tham chiu tn dng gi tr hai bin

Nhn thy khung hnh c di 2 chiu khc nhau nn nu qut theo chiu rng

s tit kim c kch thc ca s (thnh (480 + 7) 8) v nu bt u qut t

di cng bn tay phi th khi 8x8 bit ht 63 gi tr, ch cn a thm 1 gi tr

pixel mi vo, v c th tip tc qut ca s t phi sang tri, cn khi 8x8 t di

ln trn. Nh vy mi ln qut cng ch cn a thm 1 gi tr pixel mi vo.

Quy trnh qut theo ct nh sau:


22

Ban u, trc khi qut khi 8x8 u tin, thm 7 pixel vo bn phi v bn di

ca khung hnh theo chiu di v chiu rng tng ng c gi tr mi pixel l 0xFF.

Bt u qut khi 8x8 u tin tn cng bn phi, tng ng vi to

(479, 639).

Dch khi ln trn theo tng pixel qut theo chiu rng t di ln trn,

t phi sang tri

Vi mi ln dch ca hai khi trong hai khung hnh nh trn, chng trnh thc

hin:

Tnh ton tr tuyt i sai khc ca tng pixel trong hai khi.

Tnh tng tr tuyt i sai khc gia hai khi 8x8.

Tnh lch ta gia hai khi ng vi mi tng tr tuyt i sai khc.

Sau khi qut xong ton b khung hnh tham chiu ng vi mt khung hnh

hin ti:

o Thc hin so snh cc tng tr tuyt i sai khc tm gi tr tng

tr tuyt i sai khc nh nht

o a ra lch ta ng vi tng tr tuyt i sai khc nh nht

, tc l vector chuyn ng ng vi khung hnh hin ti.

4.2. Thit k thut ton

Da vo tng trn, nhm xy dng thut ton qut cho hai khung hnh: khung

hnh hin ti v khung hnh tham chiu.

4.2.1. Thut ton qut khung hnh hin ti:

Thc hin c tng pixel theo chiu t tri sang phi, t trn xung di

ly ra cc khi nh 64x8 (kch thc 8 x 8 = 64).

gim phc tp ca vic thit k cc khi gii m a ch phc tp

cho mt khi nh kch thc 64x8, nhm s dng dy cc thanh ghi dch

lm b nh cha cc khi 8x8 nn cn c pixel theo chiu ngc li: t

im cui cng n im u tin v c mi ln dch mt pixel sang phi

l ng vi dy thanh ghi dch dch xung 1 thanh ghi.


23

4.2.2. Thut ton qut khung hnh tham chiu

Nhm dng cch qut th 3 trn thc hin qut khung hnh tham chiu. Cng

vi vic s dng dy thanh ghi dch kch thc (480 + 7) 8 thay th cho b nh

cng kch thc, tin trnh qut tng pixel c thc hin qut t im cui cng n

im u tin trong khung hnh tham chiu. u ra cn c c l khi 8x8 cn qut

phi v tr u tin (tng ng 64 thanh ghi u tin) ca dy cc thanh ghi dch.

Dy thanh ghi dch s qut dc t phi sang tri, nhng tng thanh ghi s tham gia 2

loi qut sau:

Qut dc tng pixel t di ln trn, ng vi mi pixel dch ln trn l dy

thanh ghi dch phi 1 thanh ghi

Qut ngang tng pixel t phi sang tri, do cn ly ra ng 64 thanh ghi

v tr u tin th ng vi mi pixel dch sang tri, dy thanh ghi dch dch

xung 8 (dch vng 8), dch phi 1 thanh ghi


24

4.3. Thit k kin trc

64 8

-BIT

VA

LUES

64 8

-BIT

VA

LUES

SAD

CA

LCU

LATO

R(8

)

MO

TIO

N V

ECTO

R C

ALC

ULA

TOR

(10

)

CON

TRO

LLER

AD

DRE

SS

SAD

VA

LUE

MO

TIO

N V

ECTO

R V

ALU

E

COM

PARA

TOR

(1)

MIN

SA

D V

ALU

E

MO

TIO

N V

ECTO

R

REF

EREN

CE

DA

TA

FRA

ME

(1)

CU

RR

EN

T

DA

TA

FRA

ME

(1)

8-B

IT V

ALU

E

8-B

IT V

ALU

EA

DD

RESS

CUR

REN

T A

DD

RES

S

CUR

REN

T FR

AM

E B

UFF

ER 6

4x8

(1)

SYN

C. R

EG(1

)

REF

EREN

CE

FRA

ME

BU

FFER

4

87

x8x8

(1)

SYN

C. R

EG(1

)

SYN

C. R

EG(1

1)

SYN

C. R

EG(1

0)

MO

TIO

N E

STIM

ATI

ON

Hnh 4.6. Kin trc chung ca mch1

1 Cc s trong ngoc n ca mi khi th hin tr tng ng ca khi


25

Bi ton xy dng da trn khi d on chuyn ng lin nh (motion

estimation) v c chia thnh 6 khi:

Khi iu khin (Controller).

Khi b m khung hnh hin ti (Current frame buffer), kch thc 64x8.

Khi b m khung hnh tham chiu (Reference frame buffer), kch thc

(487 8) 8.

Khi tnh ton tng tr tuyt i sai khc SAD (SAD calculator).

Khi tnh ton vector dch chuyn (Motion vector calculator).

Khi so snh (Comparator).

Mi khi thc hin cc chc nng ring bit nhng phi m bo c iu kin

ng b nh trn Hnh 4.6.


26

5. THIT K RTL

5.1. Khi iu khin (control_unit)

5.1.1. S khi

curr_x

next_block

ref_read_en

ref_shift

cur_read_en

cur_read_ok

curr_y

ref_x

ref_y

curr_addr

clk

rst

en

control_unit

curr_read_x

curr_read_y

clk

[9:0]

[8:0]

[9:0]

[8:0]

Hnh 5.1. S khi iu khin

5.1.2. Chc nng

Khi lm nhim v iu khin cc khi cn li trong h thng bng cch cp cc

tn hiu iu khin tng ng. ng vi mi xung nhp sn ln, khi thc hin:

Thc hin vic c d liu t cc b nh khung hnh hin ti v tham chiu

tng ng.

Thay i gi tr tng pixel ang c c.

Thay i gi tr ta qut ref_x, ref_y.

Kim tra vic dch cho.

Thay i ta khi 8x8 hin ti.

Kim tra vic c cc khi 8x8 tip theo trong khung hnh hin ti.


27

Cung cp a ch cho khi hin ti ang xt.

5.1.3. Cc cng vo ra

u vo:

o clk: Tn hiu xung nhp ng h, ng b theo sn ln

o en: Tn hiu cho php mch hot ng

o rst: Tn hiu reset ng b, tch cc mc cao

u ra:

o ref_read_en: Tn hiu cho php c d liu t b nh khung hnh

hin ti.

o ref_shift: Tn hiu iu khin dch cho khi ref_mem.

o ref_x, ref_y: Ta ca pixel khung hnh tham chiu.

o next_block: Tn hiu bo kt thc vic xt xong mt khi ca

khung hnh hin ti v chuyn sang khi tip theo trong khung hnh

.

o curr_read_en, curr_read_ok: Tn hiu iu khin cho khi

cur_mem.

o curr_read_x, curr_read_y: Ta ca pixel hin ti ang c.

o curr_x, curr_y: Ta ca khi c lu trong b m khung

hnh hin ti.

o curr_addr: a ch khi 8x8 c lu trong b m khung hnh

hin ti.

5.1.4. Thut ton

current-x 640 8 current-y 480 8 current-read-pixel-x 640 8 current-read-pixel-y 480 8 current-address (640 / 8) * (480 / 8) 2 reference-x 0 reference-y 64

While (rising-edge-clock)

Do

If (enable-read-current-data) then

If (reference-x = 0 and reference-y = 0) then

enable-read-current-data 0


28

enable-buffer-2 1 enable-read-reference-data 1 enable-next-block 1 current-address current-address + 1 If (current-x < 640 - 8) then current-x current-x + 8

Else

current-x 0 If (current-y < 480 8) then

current-y current-y + 8 Else

current-y 0 current-address 0 Else

If (reference-y 8) then current-read-pixel-x current-read-pixel-x + 7

current-read-pixel-y current-read-pixel-y 1 Else current-read-pixel-x current-read-pixel-x 1 Else

If (reference-x = 0 and reference-y = 64) then

enable-read-current-data 1 If (current-x < 640 8) then

current-read-pixel-x current-read-pixel-x + 15 current-read-pixel-y current-read-pixel-y + 7

Else

current-read-pixel-x 7 If (current-read-pixel-y < 480 8) then

current-read-pixel-y current-read-pixel-y + 15 Else

current-read-pixel-y 7

If (reference-y > 0) then

reference-y reference-y - 1 reference-shift 0

Else

reference-shift 1 reference-y 479

If (reference-x > 0) then reference-x reference-x 1 Else reference-y 639


29

5.2. Khi b m khung hnh hin ti (curr_mem)

5.2.1. S khi

clk

rst

en

curr_mem

data_out[64x8 - 1:0]

read_en

read_ok

read_data[7:0]

Hnh 5.2. S khi b m khung hnh hin ti

5.2.2. Chc nng

Khi lm b m cho khung hnh hin ti ly ra cc khi 8x8 c

chia sn.

Mi sn ln ca xung nhp, gi tr tng pixel khung hnh hin ti c

a vo cc thanh ghi.

u ra l 64 gi tr khi 8x8 khung hnh hin ti.

5.2.3. Cc cng vo ra

u vo:




o read_en: Tn hiu cho php in y b m khung hin ti 1.

o read_ok: Tn hiu cht b m khung hin ti 2.

o read_data (8 bits): D liu khung hnh hin ti i vo b m.

u ra:

o data_out: 64 gi tr 8 bits, tng ng vi mt khi 8x8 khung

hnh hin ti.


30

5.2.4. Thut ton


Do

If (done-buffer-1) then buffer-2 buffer-1 Else

If (enable-buffer-1) then buffer-1[i] buffer-1[i 1] buffer-1[0] data-input

5.3. Khi b m khung hnh tham chiu (ref_mem)

5.3.1. S khi

clk

rst

en

ref_mem

data_out [64x8 1:0]

shift

data_in[7:0]

next_block

Hnh 5.3. S khi b m khung hnh tham chiu

5.3.2. Chc nng

Khi lm b m ly ra khi tham chiu 8x8 so snh

Khi to ca s (480 + 7) 8 vi ton b pixel c gi tr 0.

C mi mt xung nhp, ca s thc hin dch xung hay dch cho ty theo

ang dch theo chiu dc hay chiu ngang.

u ra cn ly l khi 8x8 (64 gi tr) v tr u tin trn cng ca ca

s.

5.3.3. Cc cng vo ra

u vo:




31


o next_block: Tn hiu thng bo kt thc khi 8x8 ang xt, chuyn

sang tnh ton khi 8x8 tip theo trong khung hnh hin ti

o shift: Tn hiu dch ca s kch thc (480+7)x8 i xung hoc i

cho

o data_in (8 bits): D liu khung hnh tham chiu

u ra:

o data_out: 64 gi tr 8 bits, tng ng vi mt khi qut 8x8 khung

hnh tham chiu

5.3.4. Thut ton

Chia ca s kch thc 487x8 thnh 59 khi 8x8 v 1 khi 15x8. Vi mi khi

u phi thc hin 2 loi dch: dch ln v dch xung nn nhm chia ra lm 2 khi

nh l khi 1x8 (dch ln), khi nx8 (khi dch xung, n c th bng 8 hoc 15), u

ra l khi d liu 8x8 dng a vo khi tnh ton tng tr tuyt i sai khc SAD.

data-out-8x8 block-8x8 out-block-1x8 block-8x8[n - 1] out-block-7x8[row][col] block-8x8[row + (n 8)][col]


Do

If (active-next-block) then

If (row 0 or col 0) then block-8x8[row][col] 0xFF block-8x8[0][0] in-block-1x8[0] Else

If (enable-shift-up) then

block-8x8[row][col] block-8x8[row 1][col] block-8x8[0][col] in-block-1x8[col]

Else

block-8x8[row][col] in-block-nx8[row][col 1] row 8:n col 2:8 block-8x8[row][col] block-8x8[row 8][x 1] block-8x8[row][0] 0xFF block-8x8[0][0] in-block-1x8[0]


32

5.4. Khi tnh ton tng tr tuyt i sai khc SAD (sad_calc64)

5.4.1. S khi

clk

rst

en

block1

block2

[64x8 1:0]

[64X8 1:0]sad

[13:0]

sad_calc64

Hnh 5.4. S khi tnh ton SAD

5.4.2. Chc nng

Tnh ton tng tr tuyt i sai khc ca khi 8x8 tham chiu ang xt vi khi

8x8 hin ti da vo hai u vo c 64 gi tr pixel.

Vi mi xung ng h, khi lm nhim v tnh tng tng cp gi tr sai

khc (c pipeline).

u ra l tng tr tuyt i sai khc gia khi qut v khi hin ti.

5.4.3. Cc cng vo ra

u vo:




o block1, block2: 64 gi tr khi 8x8 khung hnh hin ti v khung

hnh tham chiu

u ra:

o sad: Tng gi tr tuyt i sai khc


33

5.4.4. Thut ton

SUBTRACTION 64 9-BIT VALUES ABSOLUTION2 13-BIT VALUES

1 14-BIT VALUE

ADDER

64 8-BIT VALUES

64 8-BIT VALUES

64 8-BIT VALUES 32 9-BIT VALUES ADDER

Hnh 5.5. S tnh gi tr SAD theo kin trc pipeline

5.5. Khi tnh ton vector chuyn ng (mv_calc)

5.5.1. S khi

clk

rst

en

mv_calc

mv_x

mv_y

[10:0]

[9:0]

cur_x

cur_y

ref_x

ref_y

[9:0]

[8:0]

[9:0]

[8:0]

Hnh 5.6. S khi tnh ton vector chuyn ng

5.5.2. Chc nng

Mch thc hin chc nng tnh ton lch ca tng cp ta khi tham chiu

v ta khi hin ti.

mi sn ln ca xung nhp, thc hin tnh ton vector chuyn ng ng

vi mi sad tnh c khi sad_calc, v vy c thm cc thanh ghi dch

ng b thi gian u ra xut hin (xut hin cng vi tng sad tng

ng).

5.5.3. Cc cng vo ra

u vo:



34



o curr_x, curr_y: Ta ca im nh cn c gi tr khung hnh

hin ti

o ref_x, ref_y: Ta ca im nh cn c gi tr khung hnh

tham chiu

u ra:

o xv_x, mv_y: vector chuyn ng ng vi trc x v y

5.5.4. Thut ton

COORDINATE X

COORDINATE Y

SUBTRACTOR COORDINATE OFFSETSYNC. REG

Hnh 5.7. S tnh ton vector chuyn ng theo kin trc pipeline

5.6. Khi so snh (comp_unit.v)

5.6.1. S khi

clk

rst

en

next

sad

min_sad

mv_x_out

mv_y_out

comp_unit

[9:0]

[13:0]

[10:0]

[9:0]

mv_x_in

mv_y_in

[13:0]

[10:0]

Hnh 5.8. S khi so snh


35

5.6.2. Chc nng

Nhim v ca khi l so snh gia 640 480

8 8= 4800 gi tr SAD i vi mi khi

8x8 hin ti tm c gi tr SAD nh nht v a vector chuyn ng ng vi

lch ta ca khi c SAD nh nht vi khi hin ti ang xt.

C mi sn ln ca xung nhp, khi thc hin so snh gi tr sad vi gi

tr nh nht c trc tm li gi tr nh nht.

Khi c tn hiu bo xt xong ton b khung hnh tham chiu th u ra

xut hin gi tr sad nh nht v cc vector chuyn ng ca n.

5.6.3. Cc cng vo ra

u vo:




o next: Tn hiu bo kt thc vic xt c khung hnh tham chiu (tc

tm ra sad nh nht)

o sad: Tng tr tuyt i sai khc

o mv_x_in, mv_y_in: Vector chuyn ng ng vi cc sad tng ng

u ra:

o min_sad: Gi tr sad nh nht

o mv_x_out: Ta x vector chuyn ng tng ng vi khi 8x8

hin ti ang xt

o mv_y_out: Ta y vector chuyn ng tng ng vi khi 8x8

hin ti ang xt

5.6.4. Thut ton


Do

If (enable-next-current-block) then

min-sad min-temp mv-x-out mv-x-temp mv-y-out mv-y-temp Else

If (sad < min-temp) then

min-temp sad


36

mv-x-temp mv-x-in mv-y-temp mv-y-in


37

6. KIM TH CHC NNG

To th mc rtl cha file code Verilog ca thit k.

6.1. Check li code:

M ca s terminal, chn ng dn n th mc rtl, g lnh leda, ca s

giao din phn mm hin ra.

Chn new project chn OK.

Hnh 6.1. Ca s to project trong Leda

Sau khi ca s Project Creation Wizard hin ra, trong mc Project Name, c th

thay tn project c ui m rng .pro.


38

Hnh 6.2. Ca s t tn cho project

Sau khi nh tn xong, chn Next, c hnh nh sau:


39

Hnh 6.3. Chn phin bn cho Verilog

Trong tab Verilog, mc Version, chn 2001 (Verilog 2001) ri chn Next.


40

Hnh 6.4. Xc nh ng dn th vin cn dng

ca s Specify Libraries, chn Next tip:


41

Hnh 6.5. Xc nh ng dn source code

Ti ca s Specify Sources Files, chn Add... dn ng dn n th mc cha

code Verilog, chn OK ri chn Next, ca s tip theo hin ra:


42

Hnh 6.6. Ca s kt thc to project

Cui cng, chn Finish.

Chn Check Load Configuration RTL.

Chn Check Run (biu tng !) xut hin ca s:


43

Hnh 6.7. Ca s xc nh top module

Kim tra Unit name vi Library name c ging vi tn top module trong thit k

khng.

Chn tab Test clock/reset nh sau:


44

Hnh 6.8. Thit lp clock v reset

Trong mc Port names, chn thit lp clock sn ln v reset tch cc mc cao.

Chn OK.

Ca s mi s hin th cc trng thi kim tra nh sau:


45

Hnh 6.9. Ca s cui cng thng bo cc li

Nu ca s hin th trng thi cc mu xanh th code c kim tra

ng.

Nu hin th cc mu nu, bo cc cnh bo, nn c qua v c th iu

chnh.

Nu hin th cc mu , phi c tht k cc cnh bo v sa li code

tun theo lut chn.

Sau khi sa code chy li kim tra cho n khi no trn ca s khng xut hin

cc trng thi mu na.

6.2. M phng trc khi tng hp mch

Thc hin lnh sau bin dch to ra file m phng v thc hin m phng.

vcs -debug +v2k +systemverilogext+sv +incdir+src ./src/*.v

./src/sim/motion_estimation_testall.sv -o rtl_simv


46

./rtl_simv gui &

Sau khi ca s hin ra, cn chn cc tn hiu mun xem kt qu.

Hnh 6.10. Chn xem dng sng ca top module

Ca s mi hin ra, nhp thi gian m phng 500 ns ri n F5 hoc nt nh hnh sau:

Hnh 6.11. Ca s dng sng

Kt qu m phng c:


47

Hnh 6.12. Kt qu m phng dng sng

7. TNG HP

Qu trnh tng hp c thc hin bng phn mm Design Compiler ca

Synopsys, s dng cng ngh DC Ultra Topographical cho php kt qu tng hp ti

u hn v tng kh nng d on thit k cui cng. chy Design Compiler, thc

hin lnh sau:

dc_shell topo gui

Trc khi thc hin cc bc cu hnh v tng hp, tng tc x l cho phn

mm, cn thit lp s lng core ca CPU s dng.

set_host_options -max_cores 4

a) Ci t th vin

Do s dng cng ngh Topographical, ngoi th vin cell, DC i hi phi thit

lp th vin cng ngh ch to thc hin m phng xp linh kin v i dy, tnh

ton c lng tr.

Ci t th vin cell chun

Chn File > Setup thit lp th vin cho tng hp mch. Chn ng dn

thit lp th vin khi ca s Application Setup xut hin.


48

Hnh 7.1. Ca s thit lp

Trong :

Search path: l ng dn mc nh thc hin tm kim cc file th

vin, m ngun, v.v

Link library: l th vin logic chun thc hin phn tch v lin kt thit

k RTL vi cc cng logic c sn.

Target library: l th vin cell ca nh sn xut, bao gm thng tin chnh

xc ca tt c cc cell (logic, timing, power) vi cc kch thc khc nhau,

c s dng trong bc mapping v ti u thit k.

Symbol library: l th vin k hiu linh kin, dng hin th s mch

trc v sau tng hp.

Search path = /data/study/bk/vlsi/rtl/src

/data/study/bk/vlsi/rtl/lib/tcbn45gsbwp_120a/frame_only_HVH_0d5_0/tc

bn45gsbwp/LM /home/work/eda/synopsys/dc/libraries/syn

Link library = * tcbn45gsbwpbc.db

Target library = tcbn45gsbwpbc.db

Symbol library = generic.sdb


49

Hnh 7.2. Chn ng dn dn n th vin tng hp

Ci t th vin cng ngh ch to

Cng ngh DC Ultra Topographical yu cu phi ci t th vin vt l c

cung cp bi nh sn xut th vin Milkyway bao gm:

Reference Libraries: th vin Standard Cell, bao gm:

o FRAM: thng tin vt l ca cell mc tng quan (bao gm hnh

dng cell, v tr cc chn, cc vng metal b s dng khng c

i dy qua). DC-T v ICC s dng th vin ny xp linh kin v

i dy (Place & Route).

o CEL: thit k chi tit ca cell.

Technology File: nh ngha cc lp i dy, l via, lut thit k (DRC).

TLU+ File: thng tin v m hnh RC ca cng ngh ch to.

Layer Mapping File: map gia tn cc lp trong Technology File v TLU+

File.

to th vin Milkyway, chn File > Create MW Library


50

Hnh 7.3. To th vin Milkyway

New library path = /data/study/bk/vlsi/rtl/lib/

New library name = work

Technology file =

/data/study/bk/vlsi/rtl/lib/tcbn45gsbwp_120a/techfiles/HVH_0d5_0/tsm

cn45_10lm7X2ZRDL.tf

Input reference libraries =

/data/study/bk/vlsi/rtl/lib/tcbn45gsbwp_120a/frame_only_HVH_0d5_0/tc

bn45gsbwp

thit lp TLU+ File, chn File > Set TLU+


51

Hnh 7.4

Maximum TLU+ file =

/data/study/bk/vlsi/rtl/lib/tcbn45gsbwp_120a/techfiles/tluplus/cln45

gs_1p10m+alrdl_rcbest_top2.tluplus

Minimum TLU+ file =

/data/study/bk/vlsi/rtl/lib/tcbn45gsbwp_120a/techfiles/tluplus/cln45

gs_1p10m+alrdl_rcworst_top2.tluplus

Layer name mapping file between technology library and ITF file =

/data/study/bk/vlsi/rtl/lib/tcbn45gsbwp_120a/techfiles/tluplus/star.

map_10M

b) To file theo di qu trnh

Vo terminal, g lnh

set_svf top.svf

c) c cc file code thit k Verilog

Chn File > Analyze, c tt c cc file *.v tr cc file testbench.

Hnh 7.5. Thm cc file code


52

d) Elaborate

Chn File > Elaborate. Trong ca s Elaborate Designs, chn file top module.

Hnh 7.6. Chn top module

Chn biu tng nh sau trn thanh menu hin schematic. S dng phm tt I

(Zoom in) v O (Zoom out) phng to hoc thu nh, dng ln chut v Shift hoc

Ctrl ln xung hoc sang ngang.

Hnh 7.7. Xem s khi


53

Hnh 7.8. S nguyn l trc tng hp

e) Kim tra thit k

Chn Design > Check Design, thc hin kim tra thit k.

Hnh 7.9. Ca s kim tra li


54

f) To clock v thit lp cc thng s clock

Chn tn hiu clk trong s mch ri chn Attributes > Specify Clock To

clock c cc thng s:

Clock name: clk.

Period: 2 (chu k xung nhp l 2ns, tng ng vi tn s 500MHz).

Falling: 0, Rising: 1 tng ng vi duty 50%.

Hnh 7.10. To clock v thit lp cc thng s clock

Ngoi ra cn thit lp cc thng s khng l tng ca clock, bao gm

uncertainty, latency, v transition.

set_clock_uncertainty 0.01 [get_clocks clk]

set_clock_latency 0.2 [get_clocks clk]

set_input_transition 0.1 [all_inputs]


55

g) Thit lp cc rng buc thit k

Tr u vo

Chn cc tn hiu u vo tr tn hiu clock trn s thit k, chn Attributes >

Operating Environment > Input Delay

Hnh 7.11. Thit lp tr u vo

Tr u ra

Chn cc tn hiu u ra trn s thit k, chn Attributes > Operating

Environment > Output Delay


56

Hnh 7.15. Thit lp tr u ra

Thit lp thng s RC cho cng vo/ra

Gi s u vo ca thit k c iu khin bng cng o nh nht (cell yu

nht), in dung u vo ln nht l 10 cell AN2D0BWP, u ra l 30 cell.

set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports

clk]]

set_driving_cell -no_design_rule -lib_cell INVD0BWP $all_in_ex_clk

set MAX_INPUT_LOAD [expr [load_of tcbn45gsbwpbc/AN2D0BWP/A1] * 10]

set_max_capacitance $MAX_INPUT_LOAD $all_in_ex_clk

set_load [expr $MAX_INPUT_LOAD * 3] [all_outputs]

iu kin hot ng (Operating condition)

Chn Attributes > Operating Environment > Operating Conditions


57

Hnh 7.18. Chn iu kin hot ng

Design Constraints

Chn Attributes > Optimization Constraints > Design Constraints

Hnh 7.22. Thit lp thng s cho Design Constraints


58

h) Compile Ultra

Chn Design > Compile Ultra, trong bt ch Incremental mapping cho

kh nng tng hp mnh hn.

Hnh 7.26. Thit lp Compile Ultra

Sau khi tng hp, xem li s mch. C th thy cc khi nh trong thit k

c gi nguyn, cc tn hiu c fan-out ln nh enable, reset c m bng cc b

o v sinh ra nhiu tn hiu ging nhau.

Hnh 7.27. S thit k sau tng hp


59

Hnh 7.28. S thit k sau tng hp (mt phn)

i) Xut bo co

Cc yu cu v timing, cng sut, din tch c kim tra v bo co sau khi

tng hp, bao gm cc loi bo co sau:

Timing Path

Chn Timing > Report Timing Path

Hnh 7.30. Report Timing Paths


60

---------------------------------------------------

data required time 2.19

data arrival time -1.18

---------------------------------------------------

slack (MET) 1.00

Report constraints

Chn Design > Report Constraints.

Hnh 7.31. Xut constraints report

Constraint Cost

-----------------------------------------------------

max_transition 0.00 (MET)

max_capacitance 0.00 (MET)

max_delay/setup 0.00 (MET)

critical_range 0.00 (MET)

max_area 0.00 (MET)

Report Power

Chn Design > Report Power.


61

Hnh 7.34. Report Power

Cell Driven Net Tot Dynamic Cell

Internal Switching Power (mW) Leakage

Cell Power (mW) Power (mW) (% Cell/Tot) Power (nW)

--------------------------------------------------------------------------------

Netlist Power 78.1920 3.5754 8.177e+01 (96%) 1.366e+07

Estimated Clock Tree Power N/A N/A (N/A) N/A

--------------------------------------------------------------------------------

Report Design Resources

Chn Design > Report Design Resources.


62

Hnh 7.36. Report Design Resources

Report Area

Chn Design > Report Area.

Hnh 7.36. Report Area


63

Number of ports: 107

Number of nets: 1265

Number of cells: 75

Number of references: 21

Combinational area: 89209.712648

Noncombinational area: 133399.502059

Net Interconnect area: undefined (Wire load has zero net area)

Total cell area: 222609.214707

Total area: undefined

j) Xut cc file kt qu tng hp

Verilog Netlist

Netlist l file m t mc cng ca thit k bao gm cc cell chun c ni dy

vi nhau.

Chn File > Save As.

Hnh 7.38. Lu file Verilog netlist

DDC File

File DDC cha thit k mch mc cng cng vi cc thng s v rng buc

thit k, c dng lm u vo cho bc phn tch thi gian bng PrimeTime v

thit k IC bng IC Compiler.

Chn File > Save As, ri t tn c ui *.ddc.


64

Hnh 7.39. Lu file .ddc

To file SDF

File SDF l file nh ngha tr tng cng v dy dn, c s dng cho m phng

c tr. S dng lnh sau xut file SDF:

write_sdf tn_file.sdf

To file SDC

File SDC (Synopsys Design Constraints) s c s dng trong ICC a cc

rng buc thit k vo thc hin layout. S dng lnh sau xut file SDC:

write_sdc tn_file.sdc

Tt file theo di

File SVF c s dng trong qu trnh kim tra Formality. S dng lnh sau

tt file theo di qu trnh v lu li.

set_svf off

Xut file TCL

Xut file shell ny cho php lu li cc lnh thc hin trong qu trnh tng

hp, gip nhanh chng thc hin li qu trnh ny t ng m khng cn thc hin

cc bc nh trn, v c th s dng li mt s lnh cho cc bc sau.


65

Hnh 7.12. Lu lch s s dng lnh trong DC

Hnh 7.13. Lu file TCL


66

8. KIM TH SAU TNG HP

Sau khi tng hp, file netlist top_netlist.v c to ra m t mch mc cng.

Kim th sau tng hp c thc hin nhm kim tra li thit k mc cng, nhm

m bo thit k c to ra m bo hot ng ng v chnh xc theo thit k

ban u. Kim th sau tng hp bao gm 2 bc:

Kim th chc nng: thc hin m phng kim tra khng c tr nhm m

bo yu cu v mt chc nng.

Kim th thi gian: thc hin m phng kim tra c tr nhm m bo yu

cu v mt thi gian.

8.1. Kim th chc nng sau tng hp

Thc hin lnh sau bin dch to ra file m phng:

vcs -debug +v2k +systemverilogext+sv +incdir+src +delay_mode_zero

./lib/tcbn45gsbwp_120a/verilog/tcbn45gsbwp_120a/tcbn45gsbwp.v

./top_netlist.v ./src/sim/motion_estimation_testall.sv -o

postsyn_func_simv

Trong :

./lib/tcbn45gsbwp_120a/verilog/tcbn45gsbwp_120a/tcbn45gsbwp.v l

ng dn n file th vin m t tng cell trong th vin di dng code

Verilog.

./top_netlist.v l file netlist c to ra sau tng hp.

Sau khi bin dch, file postsyn_func_simv c to ra v sn sng thc thi:

./postsyn_func_simv -gui


67

Hnh 8.1. Chn tn hiu xem th sng

Hnh 8.2. th sng m phng chc nng sau tng hp

[work@VIT-PC rtl]$ ./postsyn_func_simv

Chronologic VCS simulator copyright 1991-2010

Contains Synopsys proprietary information.

Compiler version D-2010.06-SP1; Runtime version D-2010.06-SP1; May 14 21:07 2014

==================================================

Test '1pos'


68

==================================================

Wed May 14 21:07:32 ICT 2014

1000: curr_addr = 0 | mv_x = 0 | mv_y = 0 | sad = 0

Wed May 14 21:07:32 ICT 2014


Wed May 14 21:07:32 ICT 2014


Wed May 14 21:10:02 ICT 2014


Wed May 14 21:12:33 ICT 2014


Thc hin cc bc ging nh qu trnh kim th chc nng trc tng hp c

th thy mch vn hot ng chnh xc sau khi tng hp.

8.2. Kim th thi gian sau tng hp

Sau khi tng hp, cc thng s v tr c tnh ton v c lng s c kim

tra m bo mch vn t yu cu v thi gian. Lnh thc hin kim th c tr:

vcs -debug +v2k +systemverilogext+sv +incdir+src


./top_netlist.v ./src/sim/motion_estimation_testall.sv -sdf

typ:motion_estimation:top.sdf -o postsyn_timing_simv

Trong c typ:motion_estimation:top.sdf thm thng tin v tr c ly t

file top.sdf to ra t qu trnh tng hp. Thc hin tng t, qu trnh kim th cho

kt qu t yu cu.

Hnh 8.3. th sng m phng c tr sau tng hp


69

9. KIM TRA TNH TNG NG

Bc ny s dng phn mm Fomality kim tra tnh tng ng gia thit

k trc v sau tng hp. khi ng phn mm, g lnh:

fm_shell -gui

Hnh 9.1. Giao din khi ng Formality

Trong phn Guidance, bm nt Guidance thm file .svf c to ra t bc

tng hp vo phn mm. Sau khi thm Guidance file, bm Load Files np vo

phn mm.


70

Hnh 9.2. Np Guidance file

Chuyn sang phn Reference, np ton b file thit k gc bng Verilog vo phn

mm i chiu vi thit k sau tng hp. Bm nt Verilog, chn tt c cc file thit

k (tr testbench), bm Load Files np vo phn mm.

Hnh 9.3. Chn tt c cc file thit k (tr testbench)

Chuyn sang tab Set Top Design thit lp top module. Chn

motion_estimation ri bm Set Top.


71

Hnh 9.4. Thit lp top module ca thit k

Chuyn sang mc Implementation, tin hnh np file Verilog top_netlist.v

(tng t nh vi mc Reference).

Hnh 9.5. Np file thit k sau khi tng hp

Chuyn sang tab Read DB Libraries, thc hin np file th vin

tcbn45gsbwpbc.db.


72

Hnh 9.6. Np file th vin

Cc bc chun b hon thnh, tip theo chuyn sang phn Match, bm Run

Matching bt u kim tra tnh tng ng.

Hnh 9.7. Bt u kim tra tnh tng ng


73

Phn mm tn kh nhiu thi gian kim tra, do thit k c nhiu kt ni v

kch thc kh ln. Tt c cc im u khp.

Hnh 9.8. Kt qu kim tra tnh tng ng

Sau khi kim tra tnh tng ng, chuyn sang phn Verify kim tra thit k.

Bm nt Verify tin hnh kim tra. Qu trnh ny din ra kh lu.

Hnh 9.9. Verify thit k

Kt qu kim tra bao gm Falling Points (cc im b sai), Passing Points (cc

im ng), Aborted Points v Unverified Points (cc im khng c kim tra).


74

Thit k sau khi kim tra khng pht hin ra im no b sai, tt c cc im u

ng, qu trnh tng hp din ra khng gp sai st no.

Hnh 9.10. Passing Points

Tng hp kt qu ca qu trnh kim tra tnh tng ng:

***************************** Guidance Summary *****************************

Status

Command Accepted Rejected Unsupported Unprocessed Total

----------------------------------------------------------------------------

architecture_netlist: 1 0 0 0 1

boundary : 64 0 0 0 64

boundary_netlist : 1 0 0 0 1

change_names : 145 1 0 0 146

constraints : 64 0 0 0 64

datapath : 64 0 0 0 64

environment : 3 0 0 0 3

instance_map : 29 0 0 0 29

inv_push : 134 0 0 0 134

merge : 64 0 0 0 64

reg_merging : 1 0 0 0 1

replace : 129 1 0 0 130

uniquify : 66 0 0 0 66

*********************************** Matching Results

***********************************

34497 Compare points matched by name

0 Compare points matched by signature analysis

0 Compare points matched by topology

19 Matched primary inputs, black-box outputs

0(0) Unmatched reference(implementation) compare points

0(0) Unmatched reference(implementation) primary inputs, black-box outputs

10931(0) Unmatched reference(implementation) unread points


75

*************************************************************************************

***

********************************* Verification Results

*********************************

Verification SUCCEEDED

----------------------

Reference design: r:/WORK/motion_estimation

Implementation design: i:/WORK/motion_estimation

34497 Passing compare points

-------------------------------------------------------------------------------------

---

Matched Compare Points BBPin Loop BBNet Cut Port DFF LAT

TOTAL

-------------------------------------------------------------------------------------

---

Passing (equivalent) 0 0 0 0 88 34409 0

34497

Failing (not equivalent) 0 0 0 0 0 0 0

0

*************************************************************************************

***


76

10. PHN TCH THI GIAN TRC LAYOUT

Cng on ny s dng phn mm Prime Time tin hnh phn tch thi gian,

m bo thit k khng ch ng v mt chc nng m khng vi phm v mt thi

gian. chy phn mm, g lnh:

pt_shell

Ci t th vin bng cc lnh sau:

set lib_path

"./lib/tcbn45gsbwp_120a/frame_only_HVH_0d5_0/tcbn45gsbwp/LM";

set ADDITIONAL_SEARCH_PATH "$lib_path";

set TARGET_LIBRARY_FILES "tcbn45gsbwpbc.db";

set_app_var search_path "$search_path $ADDITIONAL_SEARCH_PATH";

set_app_var target_library $TARGET_LIBRARY_FILES;

set_app_var link_library "* $target_library";

c file thit k c to ra bi bc tng hp:

read_ddc ./top.ddc

Tin hnh thit lp ng h v tr u vo nh thc hin vi bc tng hp

bng cc lnh c ly t file top_syn.tcl xut ra trong bc tng hp.

create_clock -name "clk" -period 2 -waveform { 0 1 } { clk }

set_clock_uncertainty 0.01 [get_clocks clk]

set_clock_latency 0.2 [get_clocks clk]

set_input_transition 0.1 [all_inputs]

set_input_delay -clock clk -add_delay -max -rise .2 "..."

set_input_delay -clock clk -add_delay -max -fall .2 "..."

set_input_delay -clock clk -add_delay -min -rise .1 "..."

set_input_delay -clock clk -add_delay -min -fall .1 "..."

set_output_delay -clock clk -add_delay -max -rise .2 "..."

set_output_delay -clock clk -add_delay -max -fall .2 "..."

set_output_delay -clock clk -add_delay -min -rise .1 "..."

set_output_delay -clock clk -add_delay -min -fall .1 "..."

Chy giao din phn mm bng lnh:

start_gui


77

Hnh 10.1. Giao din phn mm Prime Time

xut bo co Coverage, vo menu Timing > Analysis Coverage

Hnh 10.2. Xut file coverage report


78

Bng tng kt s c lu vo file pt_coverage.txt v hin ra mn hnh.

****************************************

Report : analysis_coverage

-check_type {setup hold recovery removal min_period min_pulse_width clock_separation

max_skew clock_gating_setup clock_gating_hold out_setup out_hold nochange}

Design : motion_estimation

Version: D-2010.06-SP3-4

Date : Wed May 14 21:59:36 2014

****************************************

Type of Check Total Met Violated Untested

--------------------------------------------------------------------------------

setup 45070 45061 (100%) 0 ( 0%) 9 ( 0%)

hold 45070 45061 (100%) 0 ( 0%) 9 ( 0%)

min_pulse_width 154792 154762 (100%) 0 ( 0%) 30 ( 0%)

out_setup 88 88 (100%) 0 ( 0%) 0 ( 0%)

out_hold 88 88 (100%) 0 ( 0%) 0 ( 0%)

--------------------------------------------------------------------------------

All Checks 245108 245060 (100%) 0 ( 0%) 48 ( 0%)

xut bo co thi gian ca mch, vo menu Timing > Report Timing

Hnh 10.3. To timing report


79



------------------------------------------------------------------------------

slack (MET) 1.003

xut bo co ng c tr nh nht, thc hin vo menu Timing > Report

Timing > Edit Chn Delay Type l min. Lu bo co vo file pt_timing_min.txt.

Hnh 10.4. Xut bo co ng c tr nh nht

------------------------------------------------------------------------------



------------------------------------------------------------------------------

slack (MET) 0.034


80

11. LAYOUT

Bc layout c thc hin bng phn mm IC Compiler ca Synopsys, bao gm

cc bc:

Chun b th vin v d liu vo.

Floor Planning.

Placement: xp linh kin.

Clock Tree Synthesis: to mng clock.

Routing: i dy.

Xut kt qu.

Thc hin cc lnh sau chy IC Compiler v thit lp s core s dng:

icc_shell gui

set_host_options -max_cores 4

a) Chun b th vin v d liu vo

Ci t th vin

Qu trnh ci t th vin gn ging vi cc bc thc hin qu trnh tng

hp, ch khc l thay v to th vin vt l Milkyway, bc ny ch m th vin

c to sn trc khi tng hp.

Chn File > Open Library m th vin c to sn.

Hnh 11.1. M th vin Milkyway to sn trc khi tng hp

c file thit k

c file DDC s dng File > Import > Read DDC.


81

Hnh 11.2. c file thit k DDC

c file rng buc thit k

c file SDC s dng File > Import > Read SDC.

Hnh 11.3. c file rng buc thit k SDC.

Bt giao din layout

S dng Window > New layout window m mt ca s thit k layout. C th

thy cc cell c xp chng ln nhau mt gc giao din thit k.


82

Hnh 11.4. Giao din thit k layout

Lu kt qu

Trc khi lu kt qu cn thc hin lnh sau b thit lp l tng cho cc cng

vo ra: remove_ideal_network [get_ports]

Cui cng thc hin lnh sau lu li ton b kt qu thc hin c:

save_mw_cel -as data_setup

b) Floor Planning

To nn

Chn Floorplan > Initialize Floorplan.


83

Hnh 11.5. To nn

Sau khi to nn, cc chn c to ra v cc cell c sp xp pha ngoi IC.

Hnh 11.6. Thit k sau khi to nn


84

Hnh 11.7. Cc cell c xp pha ngoi nn to

To chn ngun (VDD) v t (VSS)

Preroute > Derive PG Connection

Hnh 11.8. To chn ngun v t


85

To cc vng y ngun v t xung quanh IC

Preroute > Create Rings.

Hnh 11.9. To vng dy VDD

Hnh 11.10. To vng dy VSS

IC sau s c cc vng dy ngun v t xung quanh.

Hnh 11.11. Cc vng dy VDD v VSS xung quanh thit k


86

Thit lp rng cc vng dy

Preroute > Create Power Straps.

Hnh 11.12. Thit lp rng vng dy VDD

Hnh 11.13. Thit lp rng vng dy VSS

To vng m

Preroute > Create Pad Rings.

Hnh 11.14. To vng m


87

Lu kt qu

Thc hin lnh lu thit k trc khi xp linh kin.

save_mw_cel -as floorplanned

c) Xp linh kin

Sau khi to ra hnh dng c bn cho IC, cc cell c sp xp vo mch. y l

mt trong nhng bc nng nht.

Xp linh kin t ng

Chn Placement > Core Placement and Optimization.

Hnh 11.15. Xp linh kin t ng

Thi gian xp linh kin kh lu do mch phc tp v c din tch ln.


88

Hnh 11.16. Mch sau khi xp linh kin

Lu kt qu

Lu li kt qu thit k sau khi xp linh kin.

save_mw_cel -as placed

d) To mng clock

Clock l tn hiu c bit, khng c thc hin HFS (High Fan-out Synthesis)

nh cc tn hiu khc (enable, reset) m qu trnh tng hp, ti u v thit k s c

thc hin ring bc layout, bng thut ton CTS Clock Tree Synthesis.

To mng clock

Chn Clock > Core CTS and Optimization.


89

Hnh 11.17. To mng clock

Sau mt khong thi gian x l, mng clock c to ra a tn hiu clock ti u

n tng cell.


90

Hnh 11.18. Mng clock c to ra

Hnh 11.19. Tn hiu clock c a ti tng cell


91

Lu kt qu

Lu li kt qu thit k sau khi to mng clock.

save_mw_cel -as ctsed

e) i dy

Sau khi sp xp linh kin v i dy tn hiu clock, cc ng tn hiu cn li

c phn mm tnh ton v thc hin i dy t ng. y l bc nng nht v tn

km ti nguyn nht.

i dy t ng

Chn Route > Core Routing and Optimization.

Hnh 11.20. i dy t ng


92

Nh thit lp s dng a li khi bt u chng trnh, phn mm s dng ti a

ti nguyn x l ca h thng, t tc rt tt, c bit l bc i dy.

Hnh 11.21. Ti nguyn x l ca h thng c tn dng ti a

Thit k hon chnh sau khi i dy xong.


93

Hnh 11.22. Thit k hon chnh sau khi i dy

Lu kt qu

Lu thit k mach sau i dy.

f) Xut kt qu

Extract RC

Chn Route > Extract RC.

Hnh 11.23. Extract RC


94

Xut cc file d liu thit k

S dng cc lnh sau:

write_sdf icc.sdf

write_sdc icc.sdc

write -format ddc -hierarchy -modified -output {icc.ddc}

write_verilog icc.v

Xut cc bo co

S dng cc lnh sau:

report_qor > icc_qor.txt

report_area > icc_area.txt

report_constraint -all_violators > icc_constraint.txt

report_port > icc_port.txt

report_power > icc_power.txt

report_timing > icc_timing.txt

report_timing -nosplit > icc_timing_nosplit.txt

report_timing -delay min > icc_timing_delay_min.txt

report_design -physical > icc_design_physical.txt


95

12. KIM TH SAU LAYOUT

Kim th sau layout c thc hin tng t kim th sau tng hp, ch khc file

netlist v file nh ngha tr.

vcs -debug +v2k +systemverilogext+sv +incdir+src


./icc.v ./src/sim/motion_estimation_testall.sv -sdf

typ:motion_estimation:icc.sdf -o postlayout_simv

Kt qu m phng sau layout t yu cu ra v c chc nng v thi gian.

[work@VIT-PC rtl]$ ./postlayout_simv

Chronologic VCS simulator copyright 1991-2010

Contains Synopsys proprietary information.

Compiler version D-2010.06-SP1; Runtime version D-2010.06-SP1; May 14 22:15 2014

==================================================

Test '1pos'

==================================================

Wed May 14 22:17:30 ICT 2014


Wed May 14 22:17:30 ICT 2014


Wed May 14 22:17:30 ICT 2014


Wed May 14 22:20:00 ICT 2014


Wed May 14 22:22:31 ICT 2014



96

13. PHN TCH THI GIAN SAU LAYOUT

Vic thc hin phn tch thi gian bng PrimeTime sau layout c thc hin

tng t nh cng on sau tng hp, ch khc file thit k by gi l icc.ddc. Cc

file bo co bao gm pt_postlayout_coverage.txt, pt_postlayout_timing.txt, v

pt_postlayout_timing_min.txt. Bo co cho thy mch m bm yu cu v mt

thi gian sau i dy.

****************************************

Report : analysis_coverage

-check_type {setup hold recovery removal min_period min_pulse_width clock_separation

max_skew clock_gating_setup clock_gating_hold out_setup out_hold nochange}



Date : Tue May 20 20:02:24 2014

****************************************

Type of Check Total Met Violated Untested

--------------------------------------------------------------------------------

setup 45070 45061 (100%) 0 ( 0%) 9 ( 0%)

hold 45070 45061 (100%) 0 ( 0%) 9 ( 0%)

min_pulse_width 154792 154762 (100%) 0 ( 0%) 30 ( 0%)

out_setup 88 88 (100%) 0 ( 0%) 0 ( 0%)

out_hold 88 88 (100%) 0 ( 0%) 0 ( 0%)

--------------------------------------------------------------------------------

All Checks 245108 245060 (100%) 0 ( 0%) 48 ( 0%)

****************************************

Report : timing

-path_type full

-delay_type max

-max_paths 1



Date : Tue May 20 20:02:59 2014

****************************************

Startpoint: en (input port clocked by clk)

Endpoint: control_unit_u0/curr_addr_reg[2]

(rising edge-triggered flip-flop clocked by clk)

Path Group: clk

Path Type: max

------------------------------------------------------------------------------



------------------------------------------------------------------------------

slack (MET) 0.877

****************************************

Report : timing

-path_type full

-delay_type min

-max_paths 1



Date : Tue May 20 20:03:24 2014

****************************************

Startpoint: control_unit_u0/curr_addr_reg[10]


Endpoint: control_unit_u0/curr_addr_reg[10]


Path Group: clk

Path Type: min


97

------------------------------------------------------------------------------



------------------------------------------------------------------------------

slack (MET) 0.035


98

14. KT LUN

14.1. Kt qu

Trong gn mt hc k tch cc hc tp v tm hiu, nhm hon thnh bi tp

ln v t c nhng kt qu sau:

Thit k thnh cng khi d on chuyn ng lin nh theo ng quy

trnh thit k ASIC, t yu cu trong c t chi tit (specification) c

a ra.

S dng b cng c thit k IC ca Synopsys mc c bn, tham kho

quy trnh trong ti liu training ca Synopsys.

Hiu v nm r nhng nguyn l c bn trong thit k ASIC.

14.2. Nhn xt

Thit k khi d on chuyn ng lin nh trong nn video l mt ti thit k

s phc tp, i hi mi thnh vin phi tch cc tm hiu, tra cu v c hiu cc ti

liu khc nhau, t code Verilog cho n s dng cc cng c ca Synopsys. Trong

qu trnh thc hin nhm gp phi rt nhiu vn trong vic s dng cng c.

Chng em xin chn thnh cm n s hng dn ch bo v gip tn tnh trong

qu trnh thc hin ca TS. Nguyn V Thng v KS. Nguyn Nam Phong nhm

c th thc hin thnh cng ti ny.


99

TI LIU THAM KHO

[1] R. Furtner, High Fanout without high stress: Synthesis and Optimization

of High-fanout Nets Using Design Compiler 2000.11, Boston: SNUG

Boston, 2001.

[2] N. H. E. Weste and D. M. Harris, CMOS VLSI Design: A Circuits and

Systems Perspective, Addison-Wesley, 2011.

[3] C. E. Cummings, ""full_case parallel_case", the Evil Twins of Verilog

Synthesis," 1999.

Li ni uMc lcDanh mc hnh nhDanh mc bng biu1. Tng quan1.1. Gii thiu tng1.2. K hoch thc hin1.2.1. Milestones1.2.2. Phn chia cng vic

2. c t chi tit2.1. Cc khi nim2.1.1. To im v to khi2.1.2. Tng tr tuyt i sai khc2.1.3. Vector chuyn ng

2.2. Chc nng ca mch2.2.1. Cc tham s ca mch2.2.2. Cc tn hiua) Cc tn hiu ng bb) Cc tn hiu giao tip b nhc) Cc tn hiu kt qu tnh ton

2.3. Cc yu cu phi chc nng

3. Thit k kim th3.1. Kim th h thng3.1.1. Thit k b testa) Cu trc b testb) Phn loi b testc) Cc b test

3.1.2. Kim th t ng

3.2. Kim th tng khi

4. Thit k thut ton v kin trc4.1. tng thut ton4.2. Thit k thut ton4.2.1. Thut ton qut khung hnh hin ti:4.2.2. Thut ton qut khung hnh tham chiu

4.3. Thit k kin trc

5. Thit k RTL5.1. Khi iu khin (control_unit)5.1.1. S khi5.1.2. Chc nng5.1.3. Cc cng vo ra5.1.4. Thut ton

5.2. Khi b m khung hnh hin ti (curr_mem)5.2.1. S khi5.2.2. Chc nng5.2.3. Cc cng vo ra5.2.4. Thut ton

5.3. Khi b m khung hnh tham chiu (ref_mem)5.3.1. S khi5.3.2. Chc nng5.3.3. Cc cng vo ra5.3.4. Thut ton

5.4. Khi tnh ton tng tr tuyt i sai khc SAD (sad_calc64)5.4.1. S khi5.4.2. Chc nng5.4.3. Cc cng vo ra5.4.4. Thut ton

5.5. Khi tnh ton vector chuyn ng (mv_calc)5.5.1. S khi5.5.2. Chc nng5.5.3. Cc cng vo ra5.5.4. Thut ton

5.6. Khi so snh (comp_unit.v)5.6.1. S khi5.6.2. Chc nng5.6.3. Cc cng vo ra5.6.4. Thut ton

6. Kim th chc nng6.1. Check li code:6.2. M phng trc khi tng hp mch

7. Tng hpa) Ci t th vinCi t th vin cell chunCi t th vin cng ngh ch to

b) To file theo di qu trnhc) c cc file code thit k Verilogd) Elaboratee) Kim tra thit kf) To clock v thit lp cc thng s clockg) Thit lp cc rng buc thit kTr u voTr u raThit lp thng s RC cho cng vo/raiu kin hot ng (Operating condition)Design Constraints

h) Compile Ultrai) Xut bo coTiming PathReport constraintsReport PowerReport Design ResourcesReport Area

j) Xut cc file kt qu tng hpVerilog NetlistDDC FileTo file SDFTo file SDCTt file theo diXut file TCL

8. Kim th sau tng hp8.1. Kim th chc nng sau tng hp8.2. Kim th thi gian sau tng hp

9. Kim tra tnh tng ng10. Phn tch thi gian trc layout11. Layouta) Chun b th vin v d liu voCi t th vinc file thit kc file rng buc thit kBt giao din layoutLu kt qu

b) Floor PlanningTo nnTo chn ngun (VDD) v t (VSS)To cc vng y ngun v t xung quanh ICThit lp rng cc vng dyTo vng mLu kt qu

c) Xp linh kinXp linh kin t ngLu kt qu

d) To mng clockTo mng clockLu kt qu

e) i dyi dy t ngLu kt qu

f) Xut kt quExtract RCXut cc file d liu thit kXut cc bo co

12. Kim th sau layout13. Phn tch thi gian sau layout14. Kt lun14.1. Kt qu14.2. Nhn xt

Ti liu tham kho

Documents

Thesis.pdf