물리 전자/김삼동 1

Thin Film Transistors (TFT)

- Inverted staggered structure with bottom-gate

scheme.

- i-α-Si forms a channel.

- n+-α-Si forms source and drain.

- Nitride is used for etch-stop layer for patterning the

n+-α-Si.

- Carrier mobility is very low: < 1cm2/V-s

• a-Si TFT - α-Si:H (Hydrogenated amorphous Si) deposited with

a PECVD system (low temp. process) replaces the

single crystal Si substrate.

물리 전자/김삼동 2

Thin Film Transistors (TFT)

- Subthreshold characteristics 3 µm MOSFET a-Si TFT

물리 전자/김삼동 3

Thin Film Transistors (TFT)

- Top-gate structure scheme.

- self-aligned implantation for S/D

- LPCVD poly-Si : High temp. process (> 600 oC)

- Expensive quartz substrate.

← laser recrystallization process is used by

depositing a-Si on the glass.

• poly-Si TFT - Higher carrier mobility: 10 ~ 1000cm2/V-s

⇒ Better drive capability (ID ↑, gm ↑)

물리 전자/김삼동 4

Thin Film Transistors (TFT)

• TFT Process Buffer Oxide

LPCVD α-Si (500Å)

ELC (RT, 400℃)

Gate Oxide (1000Å)

Gate (Al 3000Å)

Ion Doping (n-, n+, p+)

Laser Activation

Insulator (SiO2)

Contact and Metal (Al)

Gate

Channel Glass

S/D S/D

Glass

SiO2 a-Si

Glass Poly-Si

Gate Oxide

Gate

LDD Glass

S/D S/D

물리 전자/김삼동 5

Thin Film Transistors (TFT)

• TFT LCD one pixel

300 ㎛

Common Electrode One Pixel

Data Line

Pixel Electrode

Gate Line

)

) CF Substrate

TFT Substrate TFT

signal electrodes

control

electrodes pixel

electrode

G

S D

pixel

electrode

pixel

electrode

pixel

electrode

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Thin Film Transistors (TFT)

• Liquid Crystal

Off (Dark)

ON (Bright)

LC Layer

Incident Light

물리 전자/김삼동 7

Memory Devices

• DRAM - Write cycle: MOSFET is turned on (bias the word

line) so that the “logic state” of the bit line is

transferred to the storage capacitor.

- Refresh: Data need to be refreshed periodically

within an interval (2~50 ms) because the small but

non-negligible currents are leaking from the

capacitors.

1T-1C cell

물리 전자/김삼동 8

Memory Devices

- Charge conservation law and charge sharing

WL

BL CBL

CS

vC

vBL

vP

node1 node2

node1 vBL

node2 vC

CS CBL

Before switch (Transistor) on node1= vBL, node2 = vC After switch on node1 = node2 = v by charge conservation law

(v v ) v ( )vS C P BL BL S BLC C C C− + = +

v (v v ) vS BLC P BLS BL S BL

C CC C C C

∴ = − ++ +

물리 전자/김삼동 9

Memory Devices

- Vertical structure for typical stack cell

WL

BL

gate

STI

ILD1

BL ILD2

BL cont.

SN cont. landing pad

ILD3

P-sub

P-well STI FEOL

MEOL

BEOL

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Memory Devices

- Vertical structure for DRAM cells

3.00 ㎛

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Memory Devices

- Parasitic bit line capacitance

CS

Total Parasitic bit line capacitance where N is the number of cells/BL Components of parasitic BL capacitance Junction capacitance between BL and Sub = CBL,SUB Interlayer capacitance between BL and WL = CBL,WL Interlayer capacitance between BL and SN = CBL,SN Interlayer capacitance between BL and PN = CBL,PN Interlayer capacitance between BL and BL = CBL,BL

)(* ,∑= iBLBL CNC

물리 전자/김삼동 12

Memory Devices

- Sensing signal voltage

vS = ½ (vH - vL)

v = vH when vC = Vcc (data1 storage)

v = vL when vC= 0 (data0 storage)

v v ( v ) v ( (0 v ) v )S SBL BLH L CC P BL P BLS BL S BL S BL S BL

SCC

S BL

C CC CVC C C C C C C C

C VC C

− = − + − − ++ + + +

=+

1v 2 1

CCS

BL

S

VC

C

∴ =+

- only dependent on supply voltage(Vcc) and ratio of BL cap./cell cap.(CBL/CS)

물리 전자/김삼동 13

Memory Devices

- Change of the voltages of storage node and bit line before and after switch on

CS CBL

node1 vBL= 1/2 VCC

node2 vC

CS CBL

v

vC vBL v

Before switch on After switch on

Voltage at storage node Precharge voltage at BL Voltage after charge sharing

1v2 1

CCS

BL

S

VC

C

= +

vs

vH(Vcc)

vL(0)

½ Vcc

물리 전자/김삼동 14

Memory Devices

• SRAM Flip-flop: Two cross-coupled CMOS inverters → The

output of the inverter is connected to the input of the

other inverter.

No refresh is required and the operation of the SRAM

is static since the logic state is sustained as long as

the power is applied.

PMOS PMOS

NMOS NMOS

NMOS NMOS

물리 전자/김삼동 15

Memory Devices

• Non-volatile MOS devices

- EPROM (Erasable Programmable ROM)

: Erasing is accomplished by UV

- EEPROM (Electrically Erasable Programmable ROM) : : Erasing is accomplished electrically.

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