Transformer Fault Msg Ind

8/22/2019 Transformer Fault Msg Ind

1/60

Transformer Fault message Indicator.

In our project we are connecting two transformer assumed that it is

connected in different areas. In secondary out put we set a AC

voltage and it is connected to rectifiers section the rectifier out put

voltage is connected to the multiplexer. As well as the second area

transformer is connect to the same .If we give the address to

multiplexer by using micro controller the transformer secondary

voltage signal goes to ADC section. This digital signal is compared

with software section. If the transformer voltage signal is vary with

programmed value immediately we assumed that transformer is not

working and the micro controller output will display the particular area

transformer is failed and message will display by using LCD display.

.


2/60

in this transformer secondary section we are increase or decrease

the out put voltage value by using preset ( variable resistance).. This

value is a analog value so that we change digital format by using

ADC section. This analog signals are not able to connect the ADC

0804 chip because the ADC 0804 allows connecting only one analog

signal. So these all signals are connect to multiplexer IC 4051.The

output of the multiplexer is connect to the ADC section. By using

micro controller we give the address of the multiplexer and it allows

the signal (current value, voltage value and temperature value)

depends upon the address. The micro controller will select one by

one by using multiplexer and it goes to the ADC section. Again the

micro controller to select the ADC chip and it gives the read write

signal immediately the corresponding Digital values receives. These

digital values compared with stored values (Min value 80 and max

value is 240. If the vales exceeds then immediately the Area

transformer Fault message will display by using LCD display.


3/60

Power supply:

To give the supply voltage in all the section from power supply

section

Micro controller:

We are using micro controller Atmel 89c51 or 89c52 and we are

storing our project program in Assembly Language Program (ALP)

The CPU section is formed by employing a single 89C51 micro

controller chip and inbuilt EPROM IC for preloading the necessary

software to work successfully. The 89C51 micro controller will have

total four ports input and output ports. The output from the ADC is

connected to input Port . When any high logic signal is sensed, then

the necessary action will take place in the CPU as per the software

preloaded in the 89C51 controller IC. The output ports are connected

to the output section i.e., relay driver circuit. Then the program from

the 89C51 starts to execute and the output to the relay driver drives

the relay to switch ON/OFF the Generator.


4/60

ADC 0804 DETAILS

This section will explore interfacing ADC (analog to digital Converter) chips and

temperature sensors to the 89C51. first, we describe ADC chips,then show how

to interface an ADC to the 89C51. Then we examine the characteristics of the

LM35 temperature sensor and show how to interface it to the 89C51.

ADC DEVICES:

Analog to digital converters are among the most widely used devices for data

acquisition. Digital computers use binary (discrete) values,but in the physical

world everything is analog (continuous). Temperature,pressure (wind or liquid),

humidity and velocity are a few examples of physical qunatities that we deal with

every day. A physical quntity is converted to electrical (voltage,current) signals

using a device called a transducer. Transducers are also referred to as sensors.

Although there are sensors for temperature, velocity, pressure, light, and many

other natural quantities, they produce an output that is voltage(or cuttent).

Therefore, we need an analog to digital converter to translate the analog signals

to digital numbers so that the microcontroller can read them. A widely used ADC

chipis the ADC 0804.


5/60

ADC0804 CHIP:

The ADC0804 IC is an analog to digital converter in the family of the ADC800

series from National Semiconductor. It is also available from many other

manufacturers. It works with +5 volts and has a resolution of 8 bits. In addition

to resolution,conversion time is another major factor in judging an ADC.

Conversional binary number. In the ADC0804, the conversion time varies

depending on the clocking signals applied to the CLK R and CLK IN pins, but it

cannot be faster than 110ms. The ADC0804 pin descriptions follow.

CS:

Chip select is an active low input used to activate the ADC804 chip. To access

the ADC804,this pin must be low.

RD(READ):

This is an input signal and is active low. The ADC converts the analog input ot

its binary equivalent and holds it in an internal register. RD is used to get the

converted data out of the ADC804 chip. When CS=0,if a high to low pulse is

applied to the RD pin, the 8-bit digital output shows up at the D0-D7 data pins.

The RD pin is also referred to as output enable.

WR(Write;a better name might be start conversion):

This is an active low input used to inform the ADC804 to start the conversion

process. If CS=0 when WR makes a low to high transition,the ADC804 starts

converting the analog input value of Vin to an 8-bit digital number. The amount of

time it takes to convert varies depending on the CLK IN and CLK R values


6/60

explained below. When the data conversion is complete, the INTR pin is forced

low by the ADC804.

CLK IN AND CLK R:

CLK IN is an input pin connected to an external clock source when an external

clock is used for timing. However the 804 has an internal clock generator. To

use the internal clock generator (also called self-clocking) of the ADC804, the

CLK IN and CLK R pins are connected to a capacitor and a resistor, as shown in

fig. In that case the clock frequency is determined by the equation:

f= 1/1.1 RC

Typical values are R= 10K ohms and C= 150 pf. Susstituting in the above

equation, we get f=606khz. In that case,the conversion time is 110 micro sec.

INTR(Interrupt;abetter name might be :end of conversion)

This is an output pin and is active low. It is a normally high pin and when the

conversion is finished,it goes low to signal the CPU that the converted data is

ready to be picked up. After INTR goes low,we makes CS=0 and send a high to

low pulse to the RD pin to get the data out of the ADC804 chip.

Vin(+) and Vin(-)

These are the differential analog inputs where Vin= Vin (+)-Vin (-_ Often the

Vin(-) pin is connected to ground and the Vin(+) pin is used as the analog input to

be converted to digital.

VCC:


7/60

This the +5 Volt power supply. it is also used as a reference voltage when the

Vref/2 input(pin 9) is open (not connected). This is discussed next.

Vref/2:

pin 9 is an input voltage used for the reference voltage. If this pin is open (not

connected), the analog input voltage for the ADC804 is in the range of 0 to 5

volts (the same as the Vcc pin). However,there are many applications where the

analog input applied to Vin needs to be other than the 0 to +5V range. Vref/2 is

used to implement analog input voltage other then 0-5V. for example,if the

analog input range needs to be 0 to 4 volts,Vref/2 is connected to 2 volts. Table

12-5 shows the Vin range for various Vref/2 inputs.

D0 - D7 :

D0-D7 (When D7 is the MSB,D0 the LSB) are the digital data output pins. These

are tri-state buffered and the converted data is accessed only when CS=0 and

RD is forced low. To calculate the output voltage,use the following fomula.

Dout = Vin/step size

Where Dout = digital data output (in decimal), Vin= analog input voltage, and

step size (resolution) is the smallest change, which is (2*Vref/2)/256 for an 8-bit

ADC.

ANALOG GROUND AND DIGITAL GROUND:

These are the input pins providing the ground for both the analog singnal and

digital singnal. Analog ground is connected to the ground of the analog Vin while

digital ground is connected to the ground of the Vcc pin. The reason that we

have two tround pins is to isolate the analog Vin signal from transient voltages


8/60

caused by digital switching of the output D0-D7 such isolation contributes to the

accuracy of the digital data output. In our discussion, both are connected to the

same ground; however, in the real world of data acquisition the analog and digital

grounds are handled separately.From this discussion we conclude that the

following steps must be followed for data conversion by the ADC804 chip.

.

POWER SUPPLY

The power supply section is an important one. It should delivery

constant output regulated supply for sucessuful working of the

project. A 12V-0-12V / 1 Amp transformer is used for our purpose, the

primary of this transformer is connected to the mains supply through

a ON/OFF switch and a fuse holder for protecting from overload and

short circuit protection. The secondary side is connected to diodes to

convert from 12V ac to 12V dc voltage. Here the diodes are formed

as two Half-wave rectifier, one is for delivering +12V to +15V for the

operation of the relay & a Capacitor of 2200mfd/25V is used for

filtering purpose and another side +12V to +15V is fed to the input of

the 7805 regulator IC for getting constant output voltages for the

operation of Digital ICs, & a Capacitor of 1000mfd/25V is used for

filtering purpose to get pure dc voltage.


9/60

Low power IC regulators of the 78 series offer the advantages

ofgood regulation, current limiting and short circuit protection at 100

mA and thermal shutdown in the event of excessive power

dissipation. In fact virtually the only way in which these regulators can

be damaged is by incorrect polarity or by an excessive input voltage.

Regulators in the 78 series up to the 8v type will withstand input

voltages up to about 35V. Normally, of course, the regulators would

not be operated with such a large input-output differential as this

would lead to excessive power dissipation. A choice of 5V output

voltages is offered inthe 78 series of regulators, as shown below.

Uin Uout Type Imax C1

35V 5 V 7805 100 mA 1000 mfd/25V

All the regulators in the 78 series will deliver a maximum

current of 100 mA provided the input-output voltage differential does

not exceed 7V, otherwise excessive power dissipation will result and

the thermal shutdown will operate. This occurs at a dissipation of

about 700 mW.


10/60

A regulator circuit using the 78 is shown in fig. together with

the layout of a suitable printed circuit board. To obtain the rated

output voltages at a current up to 100 mA are given in table 1,

together with suitable values for the reservoir capacitor, C1. The

capacitance/voltage product of

these capacitors is choosen so that any one of them will fit the

printed circuit board without difficulty.

The microcomputer is making great impact on every activity of

the mankind and is playing and expected to play very important role

in the daily functioning of the developed and developing societies. In

the early years of powerful computers. Larger computers were

designed to solve complex scientific and industrial problems and

handle records of large corporations and Govt. organisations. Only

big industies and institutions were able to purchase large computers.

A trend started in the middle of 60s to design smaller computers for

smaller organisations and institutions. This situation gave the birth

minicomputer in the late 60s which pave the way for smaller

institutions, organisations, offices etc to use computers.


11/60

The microcomputer outcome of the trend towards smaller

computers which started in the middle of 60s. With the rapid

advancement in the semiconductor technology it became possible to

fabricate the whole CPU of a digital computer on a single chip using

LSI and VLSI technology. The LSI technology refers to packing as

many as 1,000 to 10,000

transistors on a single chip. A CPU built into a single LSI or

VLSI chip is called a microprocessor. A digital computer having

microprocessor as the CPU along with memory and I/O devices is

called microcomputer. The prefix micro refers to its physical size, but

not its computing powers. As far as its computing power is

concerned, the latest 32-bit microcomputers are as powerful as a

traditional mainframe computer. Presently it is possible to construct a

microcomputer having most of the features of 3rd generation

mainframe computers using just handful of ICs.


12/60

The number of bits that a digital computer can process in

parallel at a time is called its word length. It is a measure of the

computing power of a computer. The microcomputers have word

lengths of a 4-32 bits whereas large computers have 32-64 bits. 4-bit

microprocessors are used for applications in domestic appliances

control, calculators, video games, toys etc. A calculator is not a

computer as because it is not a programmable device. The user

does not prepare any program for his calculations. He performs

calculations using step by step method. As far as calculators

internal systems is concerned, it is a single chip microcomputer which

contains 4-bit microprocessor as its CPU, semiconductor memory

and I/O devices. The manufacturers have stored permanent

program in on-chip semiconductor memory for making calculations.

The data entered by the user are stored in the memory and utilised

by the processor while making calculations. The manufacturers have

not made any provision for users to enter programs.

A single chip microcomputer is also called a microcontroller.

A single chip microcomputer contains all essential elements of a


13/60

microcomputer on a single chip. It contains the CPU, ROM/EPROM,

RAM, I/O ports, timer, counters, decoder, interrupts, ADC etc.

Previously microcomputers were designed using number of chips,

each one meant for different functions. A microcontroller is designed

for a dedicated application and hence it is called dedicated

microcontroller.

Intel introduced 8048 series of single chip microcomputers in

1976. It is popularly known as MCS-48. It contains a 8-bit CPU,

1/2/4K ROM/EMPROM, 64/128/256 byte RAM, timer/counter, parallel

I/O ports and 8-bit ADC.

In the year 1980, Intel introduced a more powerful

microcontroller series 8051 in the form of a single chip

microcomputer. It has 8-bit CPU, 4/8K ROM/EPROM, 128/256 byte

RAM, timer/counter, parallel I/O ports, serial I/o ports etc. It has

provisions to increase its memory size using external EPROMs and

RAMs.


14/60

In 1983, Intel introduced a 16-bit single chip microcomputer

series as MCS-96. It contains 16-bit CPU, 8K ROM, 232 byte RAM,

timer/counter, parallel I/O ports, serial I/O ports, serial I/O ports, 10-

bit ADC, high speed I/O, pulse width modulated output, watch dog

timer etc. It is used in sophisticated missile guidance control to

complex instrumentation system.

All the standard features of a microcomputer embeded on a

single chip with its performance equal to that of a multiple chip

devices. The integration of all the basic blocks of a microcomputer

system into one circuit brings about some architectural advantages.

When the device is used as a standard one controller, it need

interface only with its I/O peripherals. This means that the execution

speed of the processing is limited only by the speed of the chip,

because there is no slowdown form transfering data between memory

and CPU as in multi chip design. The inclusion of data and program


15/60

memories simplifies the users hardware interface problem and

system implementation.

Examples of single chip microcomputers are Intel 8048,8051

and 8096 series. Motorolas M6801 series, Texas instrument

TMS1000, Atmel 89C51,89C52 and Zilog Z-80. The 16-bit

microcontroller family is 8094/8095/8096/8097 and

8394/8395/8396/8397.

The AT89C51 is a low power, high performance CMOS 8-bit

microcomputer with 4K bytes of flash programmable and erasable

read only memory(PEROM). The device is manufactured using

Atmels high-density nonvolatile memory technology and is

compatible with the industry-standard MCS-51 instruction set and

pinout. The on-chip flash allows the program memory to be

reprogrammed in-system or by a conventional nonvolatile memory

programmer. By combining a versatile 8-bit CPU with flash on a


16/60

monolithic chip, the AtmelAT89C51 is a powerful microcomputer

which provides a highly-flexible and cost-effective solution to many

embedded control applications.

The AT89C51 provides the following standard features: 4K

bytes of flash, 128 bytes of RAM, 32 I/O lines, two 16bit

timer/couters, a five vector two-level interrupt architecture, a full

duplexserial port, on-chip oscillator and clock circuitry. In addition, the

AT89C51 is designed with static logic for operation down to zero

frequency and supports two software selectable power saving modes.

The Idle mode stops the CPU while allowing the RAM,

timer/counters,serial port and interrupt system to continue functioning

. The Power down mode saves the RAM contents but freezes the

oscillator disabling all other chip functions until the next hardware

reset.

PROGRAMMING THE FLASH

The AT89C51 is normally shipped with the on-chip flash

memory array in the erased state (that is, contents=FFH) and ready

to be programmed. The programming interface accepts either a high-

voltage (12volt) or a low voltage(Vcc) program enable signal. The low


17/60

voltage programming mode provides a convenient way to program

the AT89C51 inside the users system, while the high-voltage

programming mode is compatible with conventional third- party flash

or EPROM programmers.

The AT89C51 is shipped with either the high-voltage or low-

voltage programming mode is enabled. The respective top-side

marking and device signature codes are listed below.

Vpp = 12V Vpp = 5V

Top-side mark AT89C51 AT89C51

xxxx xxxx-5

yyww yyww

Signature (030H)= 1EH (030H)=1EH

(031H)= 51H (031H)=51H

(032H)= FFH (032H)=05H

The AT89C51 code memory array is programmed byte-by-byte

in either programming mode. To program any nonblank byte in the

onchip flash memory, the entire memory must be erased using the

Chip erase mode.


18/60

Programming Algorithm:

Before programming the AT89C51, the address, data and

control signals should be set up according to the Flash programming

mode table . To program the AT89C51, take the following steps.

1. Input the desired memory location on the address lines.

2. Input the appropriate data byte on the data lines.

3. Activate the correct combination of control signals.

4. Raise EA/Vpp to 12V for the high-voltage programming

mode.

5. Pulse ALE/PROG once to program a byte in the Flash array

or the lock bits. The byte-write cycle is self-timed and typically takes

no more than 1.5ms. Repeat steps 1 through 5, changing the address

and data for the entire array or until the end of the object file is

reached.

Data polling:

The AT89C51 features Data polling to indicate the end of a

write cycle. During a write cycle, an attempted read ofthe last byte

written will result inthe complement of the written datum on P0.7 .


19/60

Once the write cycle has been completed, true data are valid on all

outputs, and the nextcycle may begin. Data polliing may begin any

time after a write cycle has been initiated.

Ready/Busy:

The progress of byte programming can also be monitored by

the RDY/BSY output signal. P3.4 is pulled low after ALE goes high

during programming to indicate busy. P.3.4 is pulled high again when

programming is done to indicate READY.

Program Verify: If lock bits LB1 and LB2 have not been

programmed, the programmed data codes can be read back via the

addresss and data lines for verification. The lock bits cannot be

verified directly. Verification of the lock bits is achieved by observing

that their features are enabled.

Chip Erase:

The entire flash array is erased electrically by using the proper

combination of control signals and by holding ALE/PROG low for

10ms. The code array is written with all1"s. The chip erase operation

must be executed before the code memory can be re-programmed.


20/60

Reading the Signature Bytes:

The signature bytes are read by the same procedure as a

normal verification of locations 030H, 031H, and 032H, exept that

P3.6 and P3.7 must be pulled to a logic low. The values returned are

as follows.

(030H) = 1EH indicates manufactured by Atmel

(031H) = 51H indicates 89C51

(032H) = FFH indicates 12V programming

(032H) = 05H indicates 5V programming.

Programming Interface

Every code byte in the Flash array can be written and the entire

array can be erased by using the appropriate combination of control

signals. The write operation cycle is selftimed and once initiated, will

automatically time itself to completion.

All major programming vendors offer worldwide support for the

Atmel microcontroller series.

Vss > Circuit ground potential


21/60

Vcc > Supply voltage during programming, verification and

normal operation.

I/O port pins and their functions

> Port-0 is an 8-bit port .It can be used for input or output. To

use the pins of port 0 as both input or output ports, each pin must be

connected to externally to 10K ohm pull-up resistor. This is due to the

fact that P0 is an open drain, unlike P1,P2 and P3. Open drain is a

term used for MOS chips in the same way the open collector is used

forTTL chips. In IN 89C51 we connect port 0 to pullup resistors.With

external pull up resistor upon reset, port 0 is configureds as an output

port . For example the following codes will continuosly send out port 0

the alternating values 55H and AAH.

MOV A, #55H

BACK: MOV P0,A

ACALL DELAY

CPL A

SJMP BACK

Port 0 as input:

With resistors connected to port 0, in order to make it an input,

the port must be programmed by writing 1 to all the bits. In the


22/60

following code, port 0 is configured as an input port by writing 1s to it,

and then data is received from that port and send to p1.

MOV A, #0FFH

MOV P0, A

BACK: MOV A, P0

MOV P1,A

SJMP BACK

Dual role of port 0

Port 0 is also designated as AD0 - AD7, allowing it to be used

for both address and data. When connecting 8951 to external

memory , port0 provides both address and data. The 8951

multiplexes address and data through port 0 to save pins .ALE

indicates if P0 has address or data . When ALE=0, it provides data

D0- D7 , but when ALE =1 it has address A0- A7. Therefore ALE is

used to demultiplexing address and data with

the help of a 74LS373 latch.

Port1:

Port1 occupies a total of 8 pins. It can be used as input or

output. In contrast to port0, this does not need any pull up resistor


23/60

since it is already has pull-up resistors internally. Upon reset, port1

configured as output port.

For example, the following codes will continuosly send out to

port 1 the alternating values 55H and AAh.

MOV A, #55HBACK: MOV P1,A ACALL DELAY CPL

A SJMP BACK

Port1 as input

To make port 1 as an input port, it must be programmed as

such by writing 1 to all its bits. In the following code port 1 is

configured first as input port by writing 1s to it, then data is received

from the port and saved in R7,R6 and R5.

MOV A,#0FFH MOV P1,A MOV A,P1

MOV R7,A

ACALL DELAY MOV A,P1

MOV R6,A

ACALL DELAY


24/60

MOV A,P1 MOV R5,A

Port 2:

Port 2 occupies a totalof 8 pins. It can be used as input or

output. Just like P1, port2 does not need pull-up resistors since it has

pullup resistors internally. Upon reset,port 2 configured as an output

port . For example the following code will send out continuosly to port

2 the alternating values 55H and AAH. That is ,all the bits of P2

toggle continuosly.

MOV A, #55H

BACK: MOV P2,A

ACALL DELAY

CPL A

SJMP BACK

Port 2 as input

To make port 2 an input , it must be programmed as such by

writing 1 to all its bits. In the following code, port2 is configured as an

input port by writing 1s to it .Then data is received from that port and

is send P1 continuosly.

MOV A,#0FFH

MOV P2,A


25/60

BACK: MOV A,P2

MOV P1,A

SJMP BACK

Dual role of port 2

In systems based on the 8751, 89C51, P2 is used as simple

I/O. However, in 8031 based systems port2 must be used along with

P0 to provide 16bit address for the external memory. Port 2 is also

designated as A8- A15, indicating its dual function.Since an 8031 is

capable of accessing 64K bytes for external memory, it needs a path

for the 16 bit address . While the P0 provides 8 bit via A0-A7 it is the

job of P2 to provide bits A8-A15 of the address.

Port 3:

Port 3 occupies a total of 8 pins ,pins 10 through 17. It can be

used as input or output.P3 does not need any pull up resistors, the

same as P1 and P2 did not. Although port 3 is configured as an

output port upon reset, this is not the way it is most commonly used.


26/60

Port 3 has the additional function of providing some extremely

important signals such as interrupts.

P3.0 and P3.1 is used for the RxD and TxD serial

communication signals.P3.2 and P3.3 is used to provide external

interrupts.Bits P3.4 and P3.5 for timers and finally P3.6 and p3.7 are

used for WR and RD signals.

Port-3 can sink/source four LS TTL inputs.

RST > While the oscillator is running a high on this pin for

two machine cycles resets the device. A small external pulldown

resistor (8.2k) from RST to Vss permits power ON reset when a

capacitor (10F) is also connected from this pin to Vcc.

____

ALE/PROG > Address Latch Enable output for latching the

low byte of the address during access to external memory. ALE is

activated at a constant rate of 1/6 the oscillator frequency except

during an external data memory access at which time one ALE pulse

is skipped. ALE can sink/source 8LS

____TTL inputs. This pin is also the program pulse input (PROG)

____


27/60

during EPROM programming. PSEN > Program Store Enable

Output is the read strobe to external program memory. PSEN is

activated twice each machine cycle during fetches from external

program memory. (However, when executing out of external program

Memory two activations of PSEN are skipped

____during each access to external data memory) PSEN is not

____activated during fetches from internal program memory. PSEN

can sink/source 8-LS TTL inputs.

EA/Vpp> When External Access Enable (EA) is held high,the

8751H execute out of internal program memory (unless the program

counter exceeds OFF(H) when EA is held low,the 875(H) executes

only out of external program memory. This pin also receives the 21V

programming supply voltage (Vpp) during EPROM progrmming This

pin should not be floated during normal operation.

XTAL1 ->Inputs to the inverting amplifier that forms the

oscillator XTAL should be grounded when an external oscillator is

used.


28/60

XTAL2-> ouptput of the inverting amplifier that forms the

oscillator,and input to the internal clock generator,receives the

external osciillator signal when an external oscillator is used.

OBSOLUTE MAXIMUM RATINGS:

Ambient temperature Emiter Bias 0. C to 70.C

Storage Temperature -65.C to +150.C

Voltage on any Pin to Vss(Except Vpp) 0.5V to + 7V

Voltage from Vpp to Vss 21.5V

Power Dissipation 2W

Note:

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this


29/60

specification is not implied. Exposure to absolute maximum rating

conditions for extended

periods may affect device reliability.

8951H Architecture: .

Architecture of 8951H can be given in brief as follows.

Accumalator:

ACC is the Accumalator register. The mnemonics for

accumulator-specific instructions,however,refer to the accumulator

simply as A.

B-Register:

The B-register is used during multiply and divide operations.

For other instructions it can be treated as another scratch pad

register.

Program Status Word:


30/60

The PSW register containts program status information. The

Program STatus Word(PSW) Contains several status bits that reflect

the current state of the CPU. The PSW, shown in fig. resides up

SFR space. It contains the Carry bit,the Auxilary Carry (for BCD

operations), the two register bank select bits,the Overflow flag,a

Parity bit and two user definable status flags.

C>Carry Flag receives carry out from bit-1 of ALU

operation.

AC>Auxilary Carry Flag receives carry out from bit-1

of Addition operands. F0> General purpose status flag RS1>

Register bank select bit-1

RS0>Register bank select bit-0

OV>Overflow flag set by arthmetic operation

>User definable flag

P>Parity of accumulator by hardware to 1 if it contains an

odd number of 1s,otherwise set to 0.


31/60

The Carry bit other than seving the funcitons of a carry bit in

arithmetic operations, also seves as the Accumulator for a number

of Boolean operations. The bits RS0 and RS1 are

used to select one of the four register bans shown in fig. A

number of instructions refer to these RAM Locations as R-0 througth

R-7 The selection of which of the four bank is being referred to is

made on the basis of the bits RS0 and RS1 at execution time.

The lower 32B are grouped into 4-banks of 8-registers.

Program instruction call out these reisters as R0 throuhg R7 2-bits ub

tge PSW select which register bank is in use.

The Parity bit reflects the number of 1s in the

Accumumulator:P=1 if the Accumulator contains an odd numbner of

1s in the Accumulator plus P is always even.

TWo bits in the PSW are uncommitted and may be used as

general purpose status flags.


32/60

Stack Pointer:

The stack pointer register is 8-bits wide. It is incremented

before data stored during pPUSH and CALL execution while the

stack may reside anywhere in on-chip RAM. The stack pointer is

intialized to 07(H) after a reset. This causes the stack to bigin at

location 08(H).

Data Pointer:

The data pointer (DPTR) consists of a high byte (DPH and a

low byte (DPL). Its intended function is to hold a 16-bit address. It

may be manipulated as a 15-bit register or as two independent 8-bit

registers.

Ports-0 to 3->P0,P1,P2,and P3 are the SFR latches of Ports-

0,1,2 and 3 respectively.

Serial Data Buffer:

The Serial Data Buffer is actually two separate registers:a

transmit buffer and a receive buffer register. When data is moved to


33/60

SBUF,it goes to the transmit buffer where it is held for serial transmit

buffer where it is held for serial transmission/ (Moving a byte tp

SBUF is what initiates the transmission). When datas is moved from

SBUF,it comes from the receive buffer.

Timer Registers:

Register pairs (THO,TLO),(TH1,TL1),AND (TH2,TL2) are the

16-bit counting registers for Timer/Counters0,1 and 2 respectively.

Capture Registers:

The register pair (RCAP2H,RCAP2L) are the Capture registers

for the Timer2 capture mode. In this mode,in response to a

transition at the 8051s T2EX pin,TH2 and TL2 are copied into

RCAP2H and RCAP2L. Timer-s also has a 16-bit auto-reload mode,

and RCAP2H and RCAP2L hold the reload value for this mode.

Control Registers:

Special Function Register IP,IE,TMOD,T2CON,SCON,and

PCON contains control and status bits for the interrupt system,the

timer counters,and the serial port.

(1)ACALL - Absolute CAll


34/60

Description: This instruction unconditionally calls a subroutine

located at the indicated address. The instruction increments the PC

twice to obtain the address of the following instruction,then pushes

16-bit result into the stack(low-order byte first ) and increments the

SP twice. The destination address is obtained by successively

concatenating the five high-order bits of the incremented PC, opcode

bits 7-5, and the second byte of the program memory as the frist byte

of the insruction following ACALL. No flags are affected.

(2)ADD A,:Add(ACC),(Source-byte)

Description: This is a simple Add instruction which adds the

byte variable indicated to the Accumulator,leaving the result in the

Accumulator. The Carry and auxiliary-carry flags are set,respectively,

if there is a carry-out from bit-7 or bit-3,and cleared otherwise. When

adding unsigned integers,the carry flag indicates that overflow

occurred.


35/60

0V is set if there is a carry-out of bit-6 but not out of bit-7,or a

carry-out of bit-7 but not bit-6;otherwise 0V is cleared.

When adding signed integers,0V indicates a negative number

produced as the sum of two positive operands,or a positive sum from

two negative operands.

Four source operand addressing modes are allowed:

register,

direct,

rgister-indirect,or

immediate.

(3)ADDC A,:Add with Carry

Description: This instruction adds simultaneously the byte

variable indicated, the carry flag and the Accumulator

contents,leaving the result in the Accumulator. The carry and

auxilary-carry flags are set respectively,if there is a carry-out from bit-

7 or bit-3 and cleard otherwise. When adding unsigned integers, the


36/60

carry flag indicates an overflow occurred 0V is set if there is a carry-

out of bit-6 but not of bit-7,or a carry-out ofbit-7 but not out of bit-

6,otherwise oV is cleared. When adding signed integers,0V indicates

a negative number produced as the sum of two positive operands or

a positive sum from two negative operands.

Four source operand addressing modes are allowed:

register

direct,

register-indirect or

immediate.

(4)AJMP addr: Absolute Jump:

Description: This instruction transfers program execution to the

indicated address, which is formed at run-time by concatenating the

high -order five bits of the PC (after incrementing PC twice),opcode

bits7-5, and the second byte of the instruction. The destination must


37/60

therefore be within the same 2K block of program memory as the first

byte of the instruction following AJMP.

(5)ANL,:Logical AND for byte variables

Describtion: This instruction performs the bitwise logical-AND

operation between the variables indicated and stores the results in

the destination variable. No flags are affected.

The two operands allow six addressing mode combinations.

when the destination is the Accumulator,the source can use

register,dirct,register direct address,the source an be the

Accumulator or immediate data.

NOTE:When this instructionb is used to modify an output

port,the value used as the original port data will be read from the

output data latch,not the input pins.

(6)ANL C,:Logical AND for bit variables

Description: If the Boolean value of the source bit is a logical-0

then clear the carry flag;otherwise leave the carry flag in its current


38/60

state. A slash(/) preceding the operand in the assembly language

indicates that the logical complement of the addressed bit is used as

the source value,but the source bit itself is not affected. No other

flags are affected. Only direct addresing is allowed for the source

operand.

(7)CJNE,,rel:Compare and Jump if Not

Equal.

Description: CJNE compares the magnitudes of the first two

operands. and branches if their values are not equal. The branch

destination is computed by adding the signed relative-displacement in

the last instruction byte to the PC, after incrementing the PC to the

start of the next instruction. The carry flag is set if the unsigned

integer value of is less than the unsigned integer value of

;otherwise the carry is cleared. Neither operand is

affected.

The first two operands allow four addressing mode

combinations:the Accumulator may be compared with any directly


39/60

addressed byte or immediate data,and any indirect RAM location or

workng register can be compared with an immediate constant.

(8) CLR A - Clear Accumulator:

Description :The accumulator is cleared (all bits set on zero).

No flags are affected. (A)


40/60

(C)


41/60

If the carry flag is now set, or if the four high-order bits now

exceed incremented by six,producing the proper BCD digit in the

high-order nibble. Again, this would set the carry flag if there was a

carry-out of the high-order bits,but wouldnt clear the carry. The carry

flag thus indicates if the sum of the original two BCD variables is

greater than 100, allowing multiple precision decimal addition. 0V is

not affected.

All of this occurs during the one instruction cycle.Essentially,this

instruction performs the decimal conversion by adding

00(H),06(H),60(H),or66(H) to the Accumuator and PSW conditions.

NOTE:DAA cannot simply convert a hexadecimal number in the

Accumulator to BCD notation, nor does DAA apply to decimal

subtraction.

(12)DEC byte :Decrement

Description;The variable indicated is decremented by 1.An

original value of 00(H) will underflow to OFF(H). No flags are

affected. Four operand addressing modes are allowed:

accumulater, register,

direct, or register-indirect.


42/60

(13)DIV AB :Divide Description: DIV AB divides the unsigned

eight-bit integer in the Accumulator by the unsigned eight-bit integer

in register B. The Accumulater recieves the

register the integer part of the quotient,register recieves the

integer remainder. The carry and OV flags will be cleared.

(14) DJNZ,:Decrement and jump if Not Zero

Description: This instruction decrements the location indicated by 1,

and branches to the address indicated by the second operand if the

resulting value is not zero. An original value of 00(H)will underflow to

OFF(H).No flags are affected. The branch destination would be

computed by adding the signed relative-displacement value in the last

instruction byte to the PC, after incrementing the PC to the first byte

of the following instruction. The location decremented may be a

register or directly addressed byte.


43/60

(15) INC : Increment Description: INC increments the

indicated variable by 1. An original value of OFF(H)will overflow to

00(H). No flags are affected. Three addressing modes are

allowed:register,direct, or register-indirect.

NOTE: When ths instruction is used to modify an output port

data latch,not the input pins.

(16)INC DPTR:Increment Data Pointer by 1.A 16-bit increment

(modula 216) is performed; an overflow of the low-order byte of the

data pointer (DPL) from 0FF(H) to 00(H) will increament the high-

order byte (DPH). NO flags are affected.

(17) JB bit,rel : Jump if Bit set

Description: If the indicated bit is a one, jump to the address

indicated otherwise proceed with the next instruction. The branch


the third instruction byte to the PC, after incrementing the PC to the

first byte of the next instruction. The bit tested is not modified. No

flags are affected.


44/60

(18) JBC bit,rel : Jump if Bit is set and Clear bit

Description : If the indicated bit is one, branch to the address

indicated, otherwise proceed with the next instruction. The bit will not

be cleared if it already a zero. The branch destination is computed by

adding the signed relative-displacement in the third instruction byte to

the PC, after incrementing the PC to the first byte of the next

instruction. No flags are affected.

(19) JC rel : Jump if Carry is set

Description : If the carry flag is set, branch to the address

indicated, otherwise proceed with the next instruction. The branch


the second instruction byte to the PC, after incrementing the PC

twice. No flags are affected.

(20) JMP @A + DPTR : Jump Indirect

Description : Add the eight-bit unsigned contents of the

Accumulator with the sixteen-bit data pointer, and load the resulting

sum to the program counter. This will be the address for subsequent

instruction fetches. 16-bit addition


45/60

is performed (modulo 216): a carry-out from the low-order 8-bits

propagates through the higher-order bits. Neither the Accumulator

nor the Data Pointer is altered. No flags are affected.

(21) JNB bit,rel : Jump if Bit Not set

Description : If the indicated bit is a zero, branch to the

indicated address; otherwise proceed with the next instruction. The

branch destination is completed by adding the signed relative

displacement in the third instruction byte to the PC, after incrementing

the PC to the first byte of the next instruction. The bit tested is not

modified. No flags are affected.

(22) JNC rel-Jump if Carry not set

Description : If the carry flag is zero, branch to the address

indicated; otherwise proceed with the next instruction. The branch

destination is computed by adding

the signed relative-displacement in the second instruction byte

to the PC, after incrementing the PC twice to point to the next

instruction. The carry flag is not modified.


46/60

(23) JNZ rel: Jump if Accumulator Not Zero

Description : If any bit of the Accumulator is a one, branch to

the indicated address; otherwise proceed with the next instruction.

The branch destination is computed by adding the signed relative-

displacement in the second instruction byte to the PC, after

incrementing the PC twice. The Accumulator is not modified. No

flags are affected. (24) JZ rel : Jump if Accumulator Zero

Description : If all bits of the Accumulator are zero, branch to

the address indicated; otherwise proceed with the next instruction.

The branch destination is computed by adding signed relative-

displacement in the second instruction byte to the PC, after

incrementing the PC twice. The Accumulator is not modified. No

flags are affected.

(25) LCALL addr16 : Long call

Description : LCALL calls a subroutine located at the indicated

addres. The instruction adds three to the program counter to

generate the address of the next instruction and then pushes the 16-

bit result onto the stack (low byte

first), incrementing the Stack Pointer by two. The high-


47/60

order and low-order bytes of the PC are then loaded,

respectively, with the second and third bytes of the LCALL instruction.

Program execution continues with the instruction at this address. The

subroutine may therefore begin anywhere in the full 64K byte

program memory address space. No flags are affected.

(26) LJMP addr16 : Long Jump

Description : LJMP causes an unconditional branch to the

indicated address, by loading the high-order and low-order bytes of

the PC (respectively) with the second and third instruction bytes. The

destination may therefore by anywhere in the full 64K program

memory address space. No flags are affected.

(27) MOV , : Move byte variable

Description : The byte variable indicated by the second operand

is copied into the location specified by the first operand. The source

byte is not affected. No other register or flag is affected. This is by

far the most flexible operation. Fifteen combinations of source and

destination addressing modes are allowed.


48/60

(28) MOV , : Move bit data

Description : The Boolean variable indicated by the second

operand is copied into the location specified by the first operand.

One of the operands must be the carry flag, the other may be any

directly addressable bit. No other register or flag is affected.

(29) MOV DPTR,#data 16: Load DPTR with a 16-bit constant

Description : The Data pointer is loaded with the 16-bit constant

indicated. The 16-bit constant is loaded into the second and third

bytes of the instruction. The second byte (DPH) is the high-order

byte, while the third byte (DPL) holds the low-order byte. No flags are

affected. This is the only instruction which moves 16-bits of data at

once.

(30) MOVC A,@A + : Move Code byte

Description : The MOVC instruction loads the Accumulator with

a code byte, or constant from program memory. The address of the

byte fetched is the sum of the original unsigned eight-bit Accumulator

contents and the contents of a sixteen-bit


49/60

base register, which may be either the Data Pointer or the PC.

In the later case, the PC is incremented to the address of the

following instruction before being added with the Accumulator,

otherwise the base register is not altered. Sixteen-bit addition is

performed so a carry-out from the low-order eight bits may propagate

through higher-order bits. No flags are affected.

(31) MOVX , : Move External

Description : The MOVX instructions transfer data between the

Accumulator and a byte of external data memory, hence the X

appended to MOV. There are two types of instructions, differing in

whether they provide an eight-bit or sixteen-bit indirect address to the

external data RAM. In the first type, the contents of R0 or R1 in

the current register bank provide an eight-bit address multiplexed with

data on P0. Eight bits are sufficient for external I/O expansion

decoding or for a relatively small RAM array. For somewhat larger

arrays, any output port pins can be used to output higher-order

address bits. These pins would be controlled by an output instruction

preceding the MOVX.


50/60

In the second type of MOVX instruction, the Data Pointer

generates a sixteen-bit address. P2 outputs the high-order 8-address

bits(the contents of DPH) while P0 multiplexes the low-order 8

bits(DPL) with data. The P2 special Function Register retains its

previous contents while the P2 output buffers are emitting the

contents of DPH . This form is faster and more effecient when

accessing very large data arrays (up to 64K bytes),since no additional

instructions are needed to set up the output ports. It is possible in

some situations to mix the two MOVX types. A large RAM array with

its high-order address lines driven by P2 can be addressed via the

DPTR or with code to output high-order address bits to P2 formed by

a MOVX instruction using R0 or R1.

(32)MULAB:Multiply

Description: MUL AB multiplies the unsigned 8-bit integers in

the Accumulator and registerB. The low-order byte of the sixteen-bit

product is left in the Accumulator,and the high-order byte in B. If the

product is greater than 255 {OFF(H)} the overflow flag is

set,otherwise it is cleared. The carry flag is always cleared


51/60

(A)7-0


52/60

complement of the addressed bit is used as the source value,but the

source bit itself is not affected. No flags are affected.

(a) ORL C,bit

(C)


53/60

(38)RET: Return from subroutine

Descrition: RET pops the high and low-order bytes of the PC

successively from the stack,decrementing the SP by two. Program

execution continues at the resulting address, generally the instruction

imediately following an ACALL or LCALL. No flags are affected.

(PC15-8)


54/60

is generally the instruction immediately after the point at which the

interrupt request was detected. If a lower-or

same-level interrupt had been pending when the RET1

instruction is executed, that one instruction will be executed before

the pending interrupt is processed.

(PC 15-8)


55/60

Description:: The eight bits in the Accumulator and the carry

flag are together rotated one bit to the left. Bit-7 moves into the carry

flag; the original state of the carry flag moves into the bit-0 position.

No other flags are affected.

(An+1)


56/60

(An)


57/60

multiple indicates that a borrow was needed for the previous

step in a multiple indicates that a borrow was needed for the previous

step in a multiple precision subtraction, so the carry is substracted

from the Accumulator along with the source operand). AC is set if a

borrow is needed for bit-3 and cleard otherwise. 0V is set if a borrow

is needed into bit-6,but not into bit-7,or into bit-7,but not bit-6.

When subtracting signed integers 0V indicates a negative

number produced when a negative value is subtracted from a positive

value, or a positive result when a positive number is subtracted from

a negative number,. The source operand allows four addressing

modes:register, direct,register-indirect,or immediate.

(47)SWAP A: Swap nibbles within the Accumulator

Description: SWAP A interchanges the low-and high-order

bibbles ($-bit fields) of the Accumulator (bits3-0 and bits7-

4). The operation can also be thought of as a four-bit rotate

insturction. No flags are affected.

(48)XCH A,:Exchange Accumulator with byte variable


58/60

Description XCH loads the Accumulator with the contents of the

indicated variable, at the same time writing the original Accumulator

contents to the indicated variable. The source\destination operand

can be use register,direct,or register-indirect addressing.

(49)XCHD A,@ R: Exchange Digit Description: XCHD

exchanges the low-order nibble of the Accumulator (bits3-0),generally

representing a hexadecimal or BCD digit, with that of the internal

RAM location indirectly addressed by the specified register. The

high-order nibbles (bits7-4) of each register are not affected. No flags

are affected.

(A3-0)


59/60

operation between the indicate variables, storing the results in

the destination. No flags are affected. The two operands allow six

addressing mode combinations.

When the destination is the Accumulator, the source can use

register, direct, register-indirect, or immediate addressing; when the

destination is a direct address, the source can be the Accumulator or

immediate data.

BIBLIOGRAPHY.

1. Introduction to microprocessor for Engineers and Scientists.

- P.K.GHOSH & P.K.SRIDHAR.

2. Microprocessor & Programmed logic.

- KENNETH L.SHORT.

3. Fundamentals of Microprocessors & microcomputer.


60/60

- B.RAM

4. Microprocessor & Microcomputer based System Design.

- MOHAMMED RAFIQUZZAMAN.

5. Microcontroller Applications.

- B.P.Singh.

6. Microcontroller Architecture, programming & application.

- A. Kenneth Ayala

7. Electronics for You- Volume 9.

Documents

Transformer Fault Msg Ind