Transistors and Layout 1dkao/chap02b.pdf · 2020-03-03 · VLSI Design : Chapter 5-1 1 Schedule 04. 03/27/20 Chapter 2 (Processing) 05. 04/03/20 兒童節補假一天 06. 04/10/20

VLSI Design : Chapter 5-1 1

Schedule

04. 03/27/20 Chapter 2 (Processing)

05. 04/03/20 兒童節補假一天

06. 04/10/20 Quiz 1, Chapter 2 (Transistors)

07. 04/17/20 Chapter 2 (Cross-section , latch up)

08. 04/24/20 Midterm Examination

09. 05/01/20 Review; Chapter 2 (Layout, Reverse Engineering)

10. 05/08/20Chapter 2 (Electro-Migration, RC & CMP, Design Rule)


N-P Type

Si

Si

Si

N

Si Si

Si

Si

Si

Si

Si

Si

P

Si Si

Si

Si

Si

HoleExtra electron

N type P type

BP


Diode

PN


Search for the “VLSI manufacture”NXP

https://www.youtube.com/watch?v=gBAKXvsaEiw

GF

https://www.youtube.com/watch?v=UvluuAIiA50

TSMC

https://www.youtube.com/watch?v=4Q_n4vdyZzc

https://www.youtube.com/watch?v=gBAKXvsaEiw


Process steps

First place tubs to provide properly-doped

substrate for n-type, p-type transistors:

p-tub (p-well) n-tub (n-well)

Substrate (p--)

Substrate (p--)

Cross-section


Process steps, cont’d.

Pattern polysilicon before diffusion regions:

Self-alignment

p-tub n-tub

poly polygate oxide

Substrate (p--)


Process steps, cont’d

Add diffusions, performing self-masking:

p-tub n-tub

poly poly

n+n+ p+ p+

All the PMOS and NMOS have been built now!!

Substrate (p--)


Process steps, cont’d

Start adding metal layers:

p-tub n-tub

poly poly

n+n+ p+ p+

metal 1 metal 1

contact via

Substrate (p--)

VLSI Design 9

Quick Look Again (1)

p+

p-epi (a) Base material: p+ substrate with p-epi layer

p+

(c) After plasma etch of insulatingtrenches using the inverse of the active area mask

p+

p-epiSiO

2

3SiN

4

(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)

Design Layout Masks Photolithographic

ProcessWaferPackage

Chips

VLSI Design 10


SiO2

(d) After trench filling, CMPplanarization, and removal of sacrificial nitride

(e) After n-well and V

Tpadjust implants

n

(f) After p-well andV

Tnadjust implants

p


ProcessWaferPackage

Chips

VLSI Design 11


(g) After polysilicon depositionand etch

poly(silicon)

(h) After n+ source/drain andp+source/drain implants. These

p+n+

steps also dope the polysilicon.

(i) After deposition of SiO2insulator and contact hole etch.

SiO2


ProcessWaferPackage

Chips

VLSI Design 12


(g) After polysilicon depositionand etch

poly(silicon)

(h) After n+ source/drain andp+source/drain implants. These

p+n+

steps also dope the polysilicon.

(i) After deposition of SiO2insulator and contact hole etch.

SiO2


ProcessWaferPackage

Chips

Self-alignment again!!

VLSI Design 13


(j) After deposition and patterning of first Al layer.

Al

(k) After deposition of SiO2insulator, etching of via’s,

deposition and patterning ofsecond layer of Al.

AlSiO

2


ProcessWaferPackage

Chips

VLSI Design 14

VLSI Design 15

VLSI Design 16

VLSI Design 17

VLSI Design 18

VLSI Design 19

VLSI Design 20

VLSI Design 21

Real Device VS Layout


ProcessWaferPackage

Chips

VLSI Design 22

Transistor Layout


ProcessWaferPackage

Chips

VLSI Design 23

Two Transistors Layout


ProcessWaferPackage

Chips

VLSI Design 24

Layout


ProcessWaferPackage

Chips

VLSI Design 25

CMOS Inverter

A A

np-substrate Field

Oxidep+

n+

In

Out

GND VDD

(a) Layout

(b) Cross-Section along A-A

A A


ProcessWaferPackage

Chips

np-substrate

Layout

Cross-section

Cutting line

On

Layout

Cross-section

VLSI Design 26

An Inverter

VLSI Design 27

An Inverter-2

VLSI Design 28

IC Cross Section and 3D View

VLSI Design 29

A Real Cross-section

Page 29

VLSI Design 30

Examples

Wp

Wn

VLSI Design 31

Wafer Representation of

Layout Polygons

Input

VDD

GND

Output

PMOS

NMOS

0.25 um

Aerial or Layout ViewWafer Cross-sectional View

VLSI Design 32

Example-2

VLSI Design 33

Layout


ProcessWaferPackage

Chips

VLSI Design 34

Stick diagrams

A stick diagram is a cartoon of a layout.

Does show all components/vias (except

possibly tub ties), relative placement.

Does not show exact placement, transistor

sizes, wire lengths, wire widths, tub

boundaries.


ProcessWaferPackage

Chips

VLSI Design 35

Stick layers

metal 3

metal 2

metal 1

poly

ndiff

pdiff

VLSI Design 36

Dynamic latch stick diagram

VDD

in

VSSff’

out

Metal

P diff

N diffpoly

contact

VLSI Design 37

Latch-up

CMOS ICs have parasitic silicon-controlled

rectifiers (SCRs).

When powered up, SCRs can turn on, creating

low-resistance path from power to ground.

Current can destroy chip.

Early CMOS problem. Can be solved with

proper circuit/layout structures.

VLSI Design 38

Latch-up

p-well n-well

poly poly

n+n+ p+ p+

Vss Vdd

P-

VLSI Design 39

Latch-up

Equivalent circuitIVdd

VLSI Design 40

Parasitic SCR structure

Silicon Controlled Rectifier

VLSI Design 41

Solution to latch-up

Use well contacts (tub ties) to connect wells to

power rail. Use enough to create low-

voltage connections.

VLSI Design 42

Schedule (1)

04. 03/27/20 Chapter 2 (Processing)

05. 04/03/20 兒童節補假一天

06. 04/10/20 Quiz 1, Chapter 2 (Transistors)

07. 04/17/20 Chapter 2 (Cross-section , latch up)

08. 04/24/20 Midterm Examination

09. 05/01/20 Review; Chapter 2 (Layout, Reverse Engineering)

10. 05/08/20Chapter 2 (Electro-Migration, RC & CMP, Design Rule)

VLSI Design 43

Midterm!! Next Week!!

35%

Covered From Chapter 1 to today’s material

Please bring your photo ID and color pens

Seat will be assigned

VLSI Design 44

VLSI Design 45

Solution to latch-up

p-well n-well

poly poly

n+n+ p+ p+

Vss Vdd

P-

P+

N+

Reverse bias

VLSI Design 46

What is Latch-up?

Latch-up: CMOS中形成一個雜散的PNPN結構的SCR. 當元件通過的電流,促使SCR導通,產生足以破壞CMOS的大電流.

避免方法: 增加雜散元件距離 (Layout)

使用guard ring (Layout)

降低substrate阻值(ex:epi) (Process)

SOI (Process)

Retrograde well (Process)

Trench isolation (Process)

VLSI Design 47

Three Latch-up Must Conditions

(1) The pnpn path must exit.

(2) The triggering resource must be large enough

to make the SCR turn on. (βnpnxβpnp>1)

(3) Power supply voltage must be larger than the

SCR holding voltage(Vh).

VLSI Design 48

Latch-up Types

Internal Latch up

– Applied in the core parts

– There are no guard rings

– Latch-up resistant method: forbid triggering source larger than Vt

– Parasitic device have low Vh.

External Latch up

– Applied in the I/O parts

– There are double guard rings.

– Parasitic devices have high Vh.

– Latch up resistant method: power<Vh

VLSI Design 49

JEDEC EIA/JESD78D 電子工業協會(2011.11)

AEC-Q100-011-B 汽車電子協會

Mil-883F = JESD78(A) 美國軍標等同JESD78(A)

Latch up Standards

VLSI Design 50

I trigger: for IO pins

Latch up Test Methodology

VLSI Design 51

Over Volatge test(V trigger): for Power pins

Latch up Test Methodology

VLSI Design 52

Well Contact (Tub tie) layout

metal (VSS)

p-well

p+

Well contact (Tub Tie)

VLSI Design 53

Well Contact

metal (VDD)

n-well

n+

Well contact (Tub Tie)

VLSI Design 54

Threshold voltage

Components of threshold voltage Vt = Vt0 + DVt

Vt0 = Vfb + fs + Qb/Cox + VII

Vfb = flatband voltage

= fgs - Qf/Cox

fgs : depends on difference work function between

gate and substrate

Qf : trapped surface charge

VLSI Design 55

Threshold voltage

fs = surface potential

Voltage on parallel plate capacitor. (function

of doping concentration)

VII : Additional ion implantation

VLSI Design 56

Threshold voltage (Body effect)

Reorganize threshold voltage equation:

Vt = Vt0 + DVt

DVt = gn (sqrt(fs + Vsb ) - sqrt (fs ) )

Vsb : source/substrate voltage Vsb.

gn : the body effect factor

= (sqrt(2q esiNa))/Cox

VLSI Design 57

Gate voltage and the channel

gate

drain (n+)sourcecurrent

Id

Vds < Vgs -Vt

gate

drainsourcecurrent

Id

Vds = Vgs -Vt

gate

drainsource

Id

Vds > Vgs -Vt

V+GND

Pinch-off

VLSI Design 58

Sub-threshold current

Sub-threshold current is an exponential

function of gate voltage:

VLSI Design 59

Leakage currents

Flow from source or drain to the substrate due

to diode formed by junction.

General form of leakage current is given by

diode law:

Il = Il0(eqVd/kt - 1)

VLSI Design 60

Oxide Defects

VLSI Design 61

Home works assignment

Chapter 1:

None

Chapter 2:

2-1, 2-9

VLSI Design 62

Circuit Design

Layout

Process

VLSI Design 63

Gate voltage and the channel

gate

drain (n+)sourcecurrent

Id

Vds < Vgs -Vt

gate

drainsourcecurrent

Id

Vds = Vgs -Vt

gate

drainsource

Id

Vds > Vgs -Vt

V+GND

Pinch-off

VLSI Design 64

The modern MOSFET

Features of deep submicron MOSFETs:

epitaxial layer for heavily-doped channel;

reduced area source/drain contacts for lower

capacitance;

lightly-doped drains to reduce hot electron

effects;

silicided poly, diffusion to reduce resistance.

VLSI Design 65

SPICE MOSFET models

Simulation Program with Integrated Circuit Emphasis, SPICE 1975

Level 1: basic transistor equations of Section 2.2; not very accurate.

Level 2: more accurate model (effective channel length, etc.).

Level 3: empirical model.

Level 4 (BSIM): efficient empirical model.

New models: level 28 (BSIM2), level 53 (BSIM3)…… 56 , 63

VLSI Design 66

SPICE Simulators

SPICE free simulator

OrCad PSPICE, HSPICE, I-SPICE, ……. SPICE2

Fast SPICE (Piece-wise linear)

HSIM, NANOSIM (Synopssy),

UltraSIM (Cadence) ,

ADiT (Mentor)

VLSI Design 67

Some Spice model parameters

L, W: transistor length, width.

AS, AD: source/drain areas.

(Refer to page 62 or any SPICE menu for more details)

VLSI Design 68

Devices in the Design

MOS (provided by the foundry’s PDK)

Diode (provided by the foundry’s PDK)

Wire

R

C

L

VLSI Design 69

Chapter 2 Transistors, Layout, and

Reverse

Transistor structures

Basic transistor behavior

VLSI Design 70

MOS

2

3

2

32

6Transistor

VLSI Design 71

Design –抽象主義

Layout –現實主義 (其實還是抽象)

將 RD 抽象的功能符號 -轉化為具體可實行量產的工藝製具步驟, 是為 Layout 的主要工作, Layout 工作的好壞, 攸關量產品的成本及良率.

Layout (佈局) 的工作?

VLSI Design 72

Transmission gate circuit

Gate level

MOS level

VLSI Design 73

Transmission gate layout (CMOS)

Nw

pimp

Diff Ploy

Cont

Nimp

Metal

VLSI Design 74

Layout Guideline

VLSI Design 75

Layout Guideline

Symmetric!!

對稱!!

VLSI Design 76

Device的方向性一致

S D S S D S D

D

VLSI Design 77

MOS 對稱性

A B B A A B A

Common axis of symmetry

One-dimensional layout

VLSI Design 78

A B A B B A

B A B A A B

Common-centroid layout

VLSI Design 79

Isothermal

power devicesbetter

Noise

bad

VLSI Design 80

Layout of Resistor

R = Rs ( L/W ) ohms + 2Rcontact

W

L

VLSI Design 81

Layout of Resistor-2

VLSI Design 82

Resistor Type

Sheet Resistance Parameters (0.5um 5V 2P3M)

Type of layer Min. Typ. Max. Unit

N-well 600 724 850 ohm/sq

N+ 45 65 85 ohm/sq

P+ 115 165 215 ohm/sq

Poly1 45 55 65 ohm/sq

Poly2 -- 30 50 ohm/sq

17~18%

30~31%

30~31%

18~19%

66%

variation

VLSI Design 83

Poly N-well P+

VLSI Design 84

Common Centroid Layout of Resistors

1 2 2 1

2 1 1 2

dum

my

dum

my

dum

my

dum

my

VLSI Design 85

VLSI Design 86

Layout of Capacitors

No fringing effect

Cox

VLSI Design 87

Capacitors

VLSI Design 88

Fringe of Capacitance

Substrate

MIM

PIP

MOS CAP

VLSI Design 89

Vertical Native CAPacitor (VNCAP)

no added processing cost

1.8 fF/mm2 in 130nm

2.0 fF/mm2 in 90nm

MIM Capacitors

Goal: High density with high

reliability and low cost

Dielectrics: Oxide Nitride Hi-K

Structure: VNCAP

VLSI Design 90

Capacitor Type

Double poly (PIP)A

B

n+ n+

N-well

Psub

poly2

poly1

VLSI Design 91

MOS_Cap

Poly

p+ n+ n+ p+

N-well

Psub

A

B

VLSI Design 92

Sandwich

n+ n+

N-well

Psub

M1

poly

M2

M3

M4

A

B

VLSI Design 93

Capacitor 對稱性

Common-Centroid Layout of Capacitor

C5 C5 C4 C5

C4 C3 C2 C5

C5 C1 C3 C4

C5 C4 C5 C5

利用common centroid來確保capacitor ratio.

單位電容的 corner cut 45o及dummy cap.目的是為減少製程的偏差.

VLSI Design 94

VLSI Design 95

Boundary Condition

VLSI Design 96

bad

better

VLSI Design 97

Inductors

Goal: Maximum Q

and inductance

density with

minimal process

addition

Lower series

resistance by

using thick top

metals

Increase dielectric

thickness to

reduce SX loss

Faraday shield to

reduce SX loss

4um

3um

3um

L = 0.7 nH

VLSI Design 98

IC floor Plan

Power

clamp

Power

clamp

Power

clamp

Power

clamp

Power

clamp

Power

clamp

Power

clamp

* Power clamp uniform put in related of IO PAD.

VLSI Design 99

IO Cell

Guard Rings

VLSI Design 100

Guard Rings

IO Cell

VLSI Design 101

Lathup at internal due to trigger at IO cells

Guard Rings

Additional guard ring between IO and internal can significantly increase latch-up immunity.

VLSI Design 102

IO to internal

Guard Rings

VLSI Design 103

Layout verification

DRC – Design Rule Checking (layout 是否能投產)

ERC – Electrical Rule Checking (主要檢查電位)

LVS – Layout V.S. Schematic (layout 與設計一致)

LPE – Layout Parameter Extraction (RC Extraction

將layout 的 RCL計算出來做擬真驗證)

Design Rule provided by foundry;

Command file provide by foundry and modified in

design house cad team which layout/rd is using for

the verification (but with errors……)

VLSI Design 104

Layout verification

LVS

VLSI Design 105

Midterm!! Next Week!!

35%

Covered From Chapter 1 to next week’s material

Please bring your photo ID and

color pens

Seat will be assigned

Documents

Transistors and Layout 1dkao/chap02b.pdf · 2020-03-03 · VLSI Design : Chapter 5-1 1 Schedule 04. 03/27/20 Chapter 2 (Processing) 05. 04/03/20 兒童節補假一天 06. 04/10/20