640 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 39, NO. 3. MARCH 1992

Ultra-Fast (0.5-pm) CMOS Circuits in Fully Depleted SO1 Films

Avid Kamgar, Member, IEEE, Steven J . Hillenius, Member, IEEE, Hong-Ih L. Cong, Member, IEEE, R. L. Field, W. Stewart Lindenberger, George K . Celler, Member, IEEE,

Lee E . Trimble, and T . T . Sheng

Abstract-CMOS dual-modulus, divide by 128/129, pre- scaler circuits were built in thin Si films on SIMOX (Separation by IMplantation of Oxygen) wafers. They operated at 6.2 GHz, the highest speed ever reported for a digital CMOS circuit, and 50% faster than the control circuits built in bulk Si. We made detailed electrical characterization of individual n- and p-chan- ne1 transistors. The capacitances of the n and p diodes were also measured. Using these data in circuit simulations we de- termined that the gain in speed was primarily due to the de- crease in the parasitic capacitances, in particular that of the source/drain junctions. We also measured ring-oscillator delay times, with minimum delay per stage of 34 ps.

I . INTRODUCTION NE OF the most appealing aspects of the silicon on 0 insulator (SOI) technology is that processing on SO1

wafers fits directly into typical semiconductor fabrication lines. It requires no unique material or equipment, and introduces no cross contamination. It is particularly com- patible with CMOS technology, and is simpler than the bulk CMOS process.

Although originally the driving force behind this tech- nique was to produce a new radiation-hardened material to replace silicon on sapphire (SOS), the SO1 geometry also dielectrically isolates the circuit components making the fabrication of smaller, denser, and faster circuits pos- sible without the parasitic effects which cause latch-up be- tween devices or add to device and circuit capacitances. Transistors fabricated in thin, fully depleted, SO1 promise higher performance [ 11. Such devices can compete with bipolar or other high-speed devices while maintaining the high packing density of MOS circuits.

By taking advantage of the compatibility of SO1 and CMOS technologies, we processed several CMOS cir- cuits on SIMOX wafers using a bulk CMOS process, and achieved improved circuit performance when compared to a similar bulk circuit. The symmetric CMOS bulk tech- nology has been designed for low supply voltage and high performance [2]. It simultaneously optimizes the charac-

Manuscript received January 29, 1990; revised June 19, 1991. The re- view of this paper was arranged by Associate Editor P. Cottrell.

A. Kamgar, S. .I. Hillenius, H. I. Cong, R. L. Field, W. S. Lindenber- ger, G . K. Celler, and L. E. Trimble are with AT&T Bell Laboratories, Murray Hill, NJ 07974.

T. T. Sheng was with AT&T Bell Laboratories, Murray Hill, NJ 07974. He is now with ERSO/ITRI, Hsinchu, Taiwan 31015, ROC.

IEEE Log Number 9105347.

teristics of the n- and p-channel transistors by making them symmetric in threshold voltages, junction depths, and sheet resistivities. This technology was recently used to fabricate a low-power CMOS dual-modulus (divide-by- 1281 129) prescaler IC on bulk Si with a toggle rate of 4.2 GHz [ 3 ] . Benefitting from the reduction in several para- sitic capacitances, by merely using the SO1 structure, we achieved toggle rates above 6 GHz in similar prescalers which we have recently reported [4]. Dual-modulus pre- scalers have application in frequency synthesizers which are used in radio receivers with low power dissipation. Low-power Si bipolar and GaAs IC technologies have in the past been used to fabricate similar prescalers with maximum frequencies between 1 .0 and 2.5 GHz [5]-[7].

The success of this experiment is largely due to the high quality of the SO1 material obtained by SIMOX technol- ogy, and the high temperature (1405°C) post-implant an- neal, using incoherent radiation.

In the following we describe the wafer preparation and the device processing. We then give a detailed account of the 1- V characteristics of the individual transistors, along with measurements on junction capacitances, and present the circuit results.

11. EXPERIMENT The starting material for the 4-in SIMOX wafers was

n-type (100) Si with 8 - 1 2 4 . cm resistivity. The oxygen implantation was carried out at IBIS TECHNOLOGY using 615°C substrate temperature and a beam current of 44 mA. The single implant energy and dose were 200 keV and 1.7 X 10" cmp2, respectively.

Annealing was performed at 1405°C in a special lamp furnace, with the wafers suspended between a bank of high-intensity lamps and a water-cooled base. The back side of each wafer was held exactly at the melt tempera- ture of silicon T, = 1412"C, and the implanted side was 7 "C cooler because of the temperature gradient imposed by the heating configuration. The temperature stability is due to the change in optical properties of silicon upon melting. This ensures that the surface exposed to the pho- ton flux will remain at T, without any risk of overmelting [8]. It should be pointed out that the wafer flatness is not affected by processing at these higher than usual temper- atures. High temperature per se does not cause wafer

0018-9383/92$03.00 0 1992 IEEE

bowing. Distortions and slip lines result from nonunifornm heating, which is avoided in the lamp system.

After the anneal. Rutherford backscattering and cross- sectional transmission electron microscopy (TEM) were done on two wafers to determine the thickness of the su- perficial Si and the buried oxide layers. The best estimates for the Si film and oxide layer thickness were 2350 S O A , and 3350 f S O A . respectively. In order to achieve fully depleted device conditions. the Si film was thinned down by an oxidationistrip process. The final film thick- ness after the complet? device processing was determined by TEM to be 1340 A .

Lateral isolation was achieved by local oxidation (LOCOS) through the Si film thickness using high-pres- sure oxidation. The process was aimed at growing 5000 A of oxide which was -30% overoxidation. This re- sulted in a slight increase in the buried oxide thickness in areas under the field oxide. The n and p regions were formed by P (55 keV, I X I O " c n ~ ' ) and B (30 keV. 1 x IO" cn - ' ) implantation. respectively.

The remainder of the process was identical to the bulk process 121. Gate oxide was grown to a thickness of 130 A. Undoped polyyystalline silicon was deposited to a thickness of 5000 A . I t was subsequently doped with As (100 keV, 1 x IO" cm- ' ) . or BF, (SO keV. 6 x 10" cm - ) . and patterned, to result in n c gates on n-channel and p c gates on p-channel transistors.

The source-drain junction formation was done after the sidewall formation, by depositing 200 A of CO and sin- tering at 450°C. which resulted in a CoSi, layer of about 700 A thickness. The CoSi, was then implanted with P (30 keV. S x 10'' cni-') or BF2 (40 keV. 8 x I O " ctii I) to dope the source-drain areas. Note that the implants were done into the CoSi,. They were then driven out of the CoSi, into the junction area by annealing at 800°C for 40 min. This anneal cycle was performed after glass de- position and it served as the densification process for the PTEOS as well. Single-level metallization using a com- posite of CVD W and AI completed the process.

The final device structure can be seen in the TEM mi- crograph shown in Fig. l . The details of the buried SiO?, Si film. CoSi, junctions, and the gate structure are clearly visible in this figure. N o defects were observed in the Si film. and the interfaces were atomically sharp. Si inclu- sions were seen in the substrate side of the buried oxide. Fig. 2 is another TEM micrograph showing the field oxide area. The birds beak, an artifact of the LOCOS process. is observed. The oxidation of the entire Si film along with a slight increase in the thjckness of the buried oxide under the field oxide are also clearly apparent. There seems to be also a slight reduction in the size of the Si inclusions in the buried S i 0 2 .

- 7

111. RMLILTS A N I ) D I S C I J ~ ~ I O N S Extensive measurements were performed on individual

devices of both n- and p-type. and comparisons with bulk devices were made. The threshold voltages ( V 7 ) of the

0.5 pm + Fig. 1 . Tran\nii~\ioii elcctron iiiici-ograph 0 1 ii dc \ I C C \ h o w ing thc hurled

o x i d e . SI film. S-D contract. a n d thc y a k \tructurc.

.I 1t"m * Fig. 2 . Tran\~nis\ion elcctron iiiicrograph of thc lield oxide (FOX) rcgion

bulk transistors processed along with the SO1 wafers. as discussed below. were substantially higher than those of the SO1 transistors. The V , value has a strong impact on circuit performance. Hence. to make a inore meaningful comparison between the circuits built on SO1 and bulk wafers we have, in addition. considered one other set of bulk wafers. These wafers used the same processing steps but slightly different gate oxide and channel dopings. Ta- ble I lists several characteristic parameters of transistors built on SO1 wafers. bulk wafers processed along with the SO1 wafers (bulk I ) , and bulk wafers processed separately (bulk 11).

The results of device characteriration. as well as the tneasurenients carried out on ring oscillators and prescal- ers are presented in the following sections.

A . TraiiJiAtor Par(iim2ter.s The individual transistors were 20 pni wide. with sev-

eral different channel lengths varying from 0.37 to S ptn.

Due to a IJC& of conttasi Dcfween rex: and bdtkgiound. fhJs page did not reproduce well

~

642 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 39. NO. 3. MARCH 1992

TABLE I THE I-V PARAMETERS OF SO1 A N D BULK TRANSISTORS WHICH IMPACT T H E PRESCALER SPFFD

(cm'/V . 3 ) I,,, (mA)

Gate Oxide V , V,, = 1 0 V V<, = 3.0 V (A) ( V ) n Channel p Channel V<,> = 3 0 vc,> = 3

so1 n-chann 2.0 6.6 VSG = -5 v 130 +0.25 450 IO0 p-chann 0.44 2.9

n-cham 0.2 4.3 Bulk I 130 k0.70 400 100 p-chann 0.05 1.5

n-cham 2.0 9.0 Bulk I1 IO0 k0.25 350 100 p-chann 0.50 3 . 2

The channel doping in bulk transistors was 8 X 1OI6 cm3. It was somewhat lower in the SO1 devices ( - 6 X 10l6 cm'). The correspondi!g depletion width in the SOI, therefore, was - 1400 A , slightly larger than the Si-film thickness. Hence, although our transistors were in the fully depleted mode, they were not in the very-thin-film regime [ 11.

I) Breakdown Voltage: Current-voltage characteris- tics of both n- and p-channel transistors for design gate length of 0.62 pm, and effective channel length of 0.42 pm, are shown in Fig. 3 . The kink effect, typical of thick SOS and SO1 structures, is absent because the thin Si film is fully depleted. These traces were obtained using a back- gate bias VBG of -5 V.

The n-channel devices showed onset of the source-drain breakdown, due to impact ionization, at around Vd = 5 V. The p-channel transistors, however, showed only a slight increase in the drain current at about V, = 9 V. This difference is primarily due to the lower lifetime of carriers in the p-channel devices compared with the n-channel transistors [9].

2) Effective Channel Length and Series Resistance: The difference between the design and the effective chan- nel lengths ( A L) was estimated from extrapolation of the inverse low-field transconductance of six transistors (with design channel lengths 0.5, 0.62, 0.75, 1 , 2 , and 5 pm) to zero channel length. A L in SO1 devices was -0.2 pm, somewhat larger than in bulk transistors where A L was -0.1 pm. This difference could be partially due to the lower channel doping level in the SO1 devices. This ex- trapolation also yields series resistance (R,) values. We found R, = 20 and 70 fl in n- and p-channel transistors, respectively. These values were very similar in SO1 and bulk devices.

3) Mobility: Values for low-field mobilities were ob- tained by using a drain voltage of f 0 . 1 V. The n-channel mobility varied depending on the back-gate bias condi- tions as shown in Fig. 4. It shows a slight decrease with decreasing back-gate bias from positive to negative values in correlation with an increase in interface scattering as the electrons are pushed closer to the front interface. At larger negative values of VBG the p value is the same as in the bulk, i.e., 400 cm2/V s. p-channel devices showed a similar behavior as indicated in Fig. 4. In this

' - 1 N - CHANNEL

6 6 P-CHANNEL

v, = -4v 2:p 2

1

0 -1 -2 -3 - 4 -5

DRAIN VOLTAGE (VI

Fig. 3 . Current-voltage characteriatics of the n - and p-channel transistors with effective channel length of 0.42 pm using a back-gate bias of -5 V.

6oo I

HOLES

0 -12 -10 -8 - 6 - 4 - 2 0 2 4 6

BACK-GATE B IAS ( V o l t s )

Fig. 4. Electron and hole mobility in SO1 devices as a function of the back- gate bias.

case the value of mobility bottomed at - 100 cm2/V * s nearly identical to the bulk transistors.

4) Threshold Voltage: Threshold voltages (V,) were measured for different channel lengths as a function of the back-gate voltage, at a drain voltage of f O . l V. The magnitude of the V + s in bulk devices were around f 0 . 7 V for n- and p-channel transistors, respectively. In the SO1 devices, in particular for the n channel, they were much lower as indicated in Fig. 5 . The depletio! width for a channel doping of 6 X 10l6 cm3 is - 1400 A , only

KAMGAR et al.: ULTRA-FAST CMOS CIRCUITS 643

n

!? ~ P-CHANNEL

w I L -

- 0 2 - ! ~ p

":Lo n a 0 Gax'8

8 H - 0 4 -

- 0 6 I ' I ' ' ' ' I I ' I ' LLL

I

O I

> 0 1 2 3 4 5

0 BULK P - CHANNEL

: - 0 2

; l 1 L -10 0 4 2 3 4 5

DESIGN CHANNEL LENGTH (pm)

Fig. 5. Threshold voltages of n- and p-channel transistors, in bulk and SO1 wafers, as a function of the design channel length.

s!ightly larger than the Si-film thickness which is - 1340 A . Devices which are processed in very thin SO1 films have much lower V+s compared with similar bulk tran- sistors because less charge needs to be supported by the gate to deplete the film. However, in our case this effect is relatively small, because the film thickness is only slightly less than the depletion width. Some of the reduc- tion in VT could be due to a lower channel doping in the SO1 devices. We do not have an explanation for such a large difference.

In Fig. 5 we have plotted the VT for the SO1 devices

Fig. 6.

N - CHANNEL

devices

-8V4, 1 i when the back channel is in the accumulation mode, namely, at VBG = f5 V for n and p channels, respec- tively, to avoid the effect of V , modulation by VBG when -40 P - CHANNEL

comparing with bulk values. Fig. 6 shows the dependence 1 0 -1 -2 -3 of V , on the back-gate bias for n and p transistors with GATE VOLTAGE ( V )

0.5-, 0.62-, and 2.0-pm nominal channel lengths. AS ex- pected, V, in both cases shows a saturation when the back gate is accumulated, and its surface potential is virtually

Fig. 7. Subthreshold characteristics of n- and p-channel devices for sev- eral back-gate biases.

pinned at zero. On the other hand, when the back gate is in the deple-

tion mode VT changes linearly with V E G . The magnitude of the measured threshold modulation AVT/AVBG = 0.03 is in close agreement with the calculated value of 0.034 obtained from [ l ]

- I av, - I c,,, ( l + 2) where C,,,, C,, and Csi are the capacitances of the buried oxide, the gate oxide, and the depleted Si film.

5) Subthreshold Characteristics: Fig. 7 shows the de- pendence of the subthreshold current of n- and p-channel transistors with Leff = 0.42 pm on the back-gate bias. The anomalous low-level component of the subthreshold cur- rent is removed by accumulation of the back interface in n-channel devices. In p-channel devices, on the other

hand, we can turn the leakage on by applying a negative V E G . The bulk devices did not show this "leakage" cur- rent. The source of this extra current could be a finite leakage at the back channel, either due to the channel in- version in the entire area, or only a conduction along the edges of the transistor due to a slightly different doping under the birds beak since we did not use a field implant. We measured this leakage current in an n-channel transis- tor with Leff = 0.42 pm by grounding the front gate, and using a drain voltage of 0.1 V. The results are shown in Fig. 8.

The magnitudes of the subthreshold swing (S) for n- channel devices with two different channel lengths are plotted in Fig. 9, as a function of the back-gate bias. When the leakage current is off, i.e., at VBG < -4 V the mag- nitude of S is around or below 80 mV/decade. It is inter- esting to note that the prescaler circuits, which are de-

-.

644 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 39. NO. 3, MARCH 1992

10-4 0

0

-4 BACK-GATE VOLTAGE ( V )

10-81 ' ' ' ' ' ' ' I -8

0 5 075 10 I 2 5 DESIGN CHANNEL LENGTH l a m )

60 p4 -8 -4

BACK-GATE BIAS ( V )

Fig. 9. The magnitude of subthreshold swing for n-channel devices as a function of Vsc. The anomalously high S values for VBG > -4 V is a manifestation of the finite leakage current at the back channel.

scribed later, were operational only by applying VBG of less (more negative) than -4 V.

B. Junction Capacitance We measured area and peripheral capacitances of p+-n

and n+-p diodes on SO1 and bulk wafers. Table I1 lists the average measured values for 30 diodes across a wafer. These results show that the junction capacitances on the SO1 wafers are reduced to 20% of their bulk values.

C. Ring Oscillators Forty-nine-stage ring oscillators were fabricated with

several different channel lengths. The oscillator delays per stage for both SO1 and bulk monitors are shown in Fig. 10. The delays in the circuits on SO1 are about 50% lower than bulk I for all channel lengths. Some of this reduction, however, is due to the lower Vr values in SO1 transistors. Compared with bulk 11, which has transistor characteris- tics more similar to that of SOI, the gain in speed is about 30%.

The minimum delays as a function of VDD between 1.5 and 5 V are shown in Fig. 11 for SO1 and bulk I ring oscillators. Note that even at a small VDD of 2 V the delay time in SO1 is only 50 ps, while in bulk the delay time increases dramatically at small drain voltages. The ring- oscillator delays did not show any significant dependence on VBG in the SO1 wafers.

D. Prescalers The prescalers, designed as dual modulus divide-by-

128 or 129 counters, consisted of a high-speed divide-by- 415 counter, and a lower speed divide-by-32 counter [3].

250 . 200 BULK

0 so1

o o o o o o o o o o o o o - 1 o ~ " ' " " " " " ' ' " " '

DRAIN VOLTAGE ( V )

Fig. 11. Minimum ring-oscillator delay time as a function of Vo0.

TABLE I1 AREA AND PERIPHERAL JUNCTION CAPACITANCES, C,,, AND C,,,,

TABLE I ) RESPECTIVELY, OF pi-" A N D "+-p DIODES I N so1 WAFERS A N D BULK 1 (SEE

p+-n n+-p

c1I+/,,n., c, fr / cm1 cm l P " l ~ 1 Cl IF/rml

so1 0.08 0.11 0.09 0.08 Bulk I 0.72 0.36 0.60 0.36

The block diagram of the prescaler is shown in Fig. 12. The speed of this prescaler is determined by the divide- by-415 counter, which uses two NAND gates and three edge-triggered D-type flip-flops clocked synchronously by the high-frequency input signal, To reduce the capacitive loading, 0.75-pm-wide aluminum lines and 0.5-pm-wide metal salicide interconnects were used.

The front channel threshold voltage was modulated by the back-gate voltage, and was made nearly symmetric in the range VBG = -4 to -6 V. Application of this VBG also helped turn off the finite leakage at the back channel of the n-channel transistors (see Figs. 6 and 7). Meeting these two conditions helped the operation of the prescal- ers .

The best SO1 prescaler was found to function at 6.2 GHz (Fig. 13) consuming 210 mW of power at VDD of 3.5 V. The effective gate length of the transistors is approxi- mately 0.4 pm. Back-gate bias between -4 and -6.5 V with respect to the V,,T was applied so that a threshold volt- age of about 0.2 V was obtained for both p- and n-channel transistors.

KAMGAR et a l . : ULTRA-FAST CMOS CIRCUITS 645

r , , 1

FF-C FF-B FF-A

4 . .. -. . FREQ. INPUT

,I I I

M = 1 DIY-BY-129 0 DIVW-128

M

Fig. 12. CMOS prescaler functional block diagram.

Fig. 13. Oscilloscope traces for the input and output signals for prescaler: upper trace divide-by-128, lower trace divide-by-129. gate voltage of -6 V was applied.

the SO1 A back-

The bulk prescalers functioned at considerably lower speed. The prescalers in bulk I toggled at 1.5 GHz. This low speed is presumably due to the high V , of the bulk I transistors. Bulk I1 prescalers, which had transistor pa- rameters very similar to SO1 had a toggle rate of 4.2 GHz, i.e., nearly 50% slower than the SO1 prescalers. Circuit simulations were carried out in order to explain the dif- ference in the speed of SO1 and the bulk I1 parescalers.

In the simulations the measured 1- V characteristics and junction capacitances were utilized. The gate and junction overlap was assumed to be 0.025 pm. As indicated in Ta- ble I , the r,,, values for SO1 and bulk I1 were nearly iden-

1- 4 1.5 2 2.5 3 3.5

Vdd ( V )

Fig. 14. Maximum operation frequency of the SO1 prescaler as a function of the supply voltage.

On the other hand, with the SO1 structure the total par- asitic capacitances at the timing-critical circuit nodes are reduced by approximately 50%. Given the above param- eters, the simulations showed a 50% increase in the speed of SO1 prescalers, indicating that the speed enhancement in the SO1 prescalers is entirely due to the reduction in the junction capacitances.

Maximum operation frequency was dependent upon the supply voltage (VDo), and varied by about 1.6 GHz/V of V D D (see Fig. 14). One partially operational prescaler (di- vided by 64) had a toggle frequency of 7 GHz.

It is noteworthy that the prescaler is still functional at 2 GHz with the supply voltage as low as 1.4 V dissipating only 11 mW of power. The speed of this SO1 prescaler at 6.2 GHz is 2.5 times higher than the similar prescaler circuits fabricated with GaAs or Si bipolar + 128/129 counters [5]-[7].

IV. SUMMARY A N D CONCLUSIONS By taking advantage of the compatibility of CMOS and

SO1 technologies, we fabricated devices and relatively small but high-performance circuits in thin SO1 films, using 0.5-pm symmetric CMOS processing.

The circuits were prescalers designed as dual-modulus divide-by-128 or -129 counters and consisted of around 200 transistors. The SO1 prescalers operated at 6.2 GHz, while those fabricated on bulk wafers toggled at 4.2 GHz.

In order to explain this large difference in speed I-V characteristics of individual n- and p-channel transistors, as well as, the capacitances of n and p diodes, on both SO1 and bulk wafers were measured. The transistor char- acteristics in the operational range of the prescalers were nearly identical in SO1 and bulk wafers. However, the junction diode capacitances were reduced by more than 80% in SO1 wafers.

The measured transistor characteristics and diode ca- pacitances were used in circuit simulations, which showed that the increase in the speed was entirely due to the re- duction in the capacitance of the junctions.

._

tical at low VRs, while at high V,,,, Z,,, is about 30% higher in bulk 11. However, due to the fast switching speed of the parescalers the pull-down transistors never reach the full saturation current values. The relevant Isat values de- termining the speed are hence those corresponding to the low Vg, which are comparable in bulk I1 and SOI.

ACKNOWLEDGMENT The authors wish to thank F . A. Baiocchi for the Ruth-

erford backscattering, J . Kearney for the ring oscillator measurements, and P. F. Bechtold for the capacitance measurements. They also wish to thank J. C. Sturm from

646 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 39, NO. 3. MARCH 1992

Princeton University, and M. Haond from CNET, France, for helpful discussions.

REFERENCES

[I ] J. P. Collinge, “Thin-film SO1 devices: A perspective,” Microelec- tron. Eng., vol. 8 , p. 127, 1988.

[2] S . J. Hillenius, H-I. Cong, J. Lebowitz, J . M. Andrews, R. L. Field, L. Manchanda, W. S . Lindenberger, D. M. Boulin, and W. T. Lynch, “A self aligned CoSiz sourceldrainlgate multi-gigahertz symmetric CMOS technology,” in ULSI Science and Technology 1989, C. M. Osborn and J. M. Andrews, Eds., vol. 89, no. 9, p. 51, 1989.

[3] H-I. Cong, J. M. Andrews, D. M. Boulin, S . C. Fang, S . J . Hillen- ius, and J. A. Michejda, “Multigigahertz CMOS dual-modulus pre- scaler IC,” IEEE J. Solid-State Circuits, vol. 23, p. 1189, 1988.

[4] A. Kamgar, S. J. Hillenius, H-I. Cong, R. L. Field, W. S . Linden- berger, G. K. Celler, L. E. Trimble, and J . C. Sturm, “Ultra-high speed CMOS circuits on thin SIMOX films,” in IEDM Tech. Dig., 1989, p. 829.

[5] H. Suzuki, T. Akiuyama, and K. Ueno, “A 1.6 GHz low power sil- icon dual modulus prescaler IC,” in IEDM Tech. Dig., 1984, p. 682.

[6] S. Saito, T. Takada, and N. Kato, “A 5-mA I-GHz GaAs dual-mod- ulus prescalar IC,” IEEEJ. Solid-state Circuits, vol. SC-21, p. 538. 1986.

171 A. E. Geissberger et al., “A monolithic L-band limiting amplifier and dual modulus prescaler GaAs integrated circuit,” in IEEE MTT- S In?. Microwave Symp. Dig., 1988, p. 569.

[8) G. K . Celler, “Silicon-on-insulator films by oxygen implantation and lamp annealing,” Solid Srate Technol., p. 93, Mar. 1987.

[9] J . B. McKitterick, “Source-drain breakdown in thin SO1 transis- tors,” in 1989 IEEE SOS/SOI Technology Con$ Proc., p. 17.

Avid Kamgar (M’90) received the B.S. degree in physics from the University of Tehran, Tehran, Iran, and the Ph.D. degree from the University of Maryland, College Park.

She was an Assocsiate Professor at the Tech- nical University of Munich, Germany (1973- 1976), where she carried out research on the sub- band spectroscopy of the quantized levels in Si space-charge layers. In 1976 she joined AT&T- Bell Laboratories, Murray Hill, NJ, where she has been involved in research on a wide range of top-

Hong-ih L. Cong (M’89) received the B.S. de- gree in physics from National Tsing-Hua Univer- sity, Taiwan, Republic of China, in 1969, and the M.A., M.Ph., and Ph.D. degrees in physics from Columbia University, New York, NY, in 1972, 1974, and 1977, respectively.

From 1977 to 1980 he was NRC Research As- sociate at the NASA Goddard Institute for Space Studies in New York, where he was engaged in the construction of low-noise 1 IS-GHz receivers, and radio astronomy research on the molecular

distribution of the Milky Way. In 1980 he joined the Microprocessor De- sign Department at Bell Laboratories, Murray Hill, NJ. Between 1980 and 1985 he worked on the circuit design, testing, and reliability of CMOS microprocessor and controller chips. Since 1985 he has been associated with the VLSI Device Department and has been involved in high-speed digital circuit designs. His current interest is in the areas of high-perfor- mance digital circuits and systems.

Dr. Cong is a member of the American Physical Society and the IEEE Computer Society.

R. L. Field, photograph and biography not available at the time of publi- cation.

ics in Si material and device characteristics such as: spectroscopiand pho- toconductivity of Si MOSFET’s, low-temperature properties of Si devices and circuits, formation of silicon on insulators (ZMR) by radiation melting of Si films, developing models for the subboundary formation, and rapid thermal processing of Si material and devices. Currently she is engaged in VLSI technology development. She has published over 40 articles and was awarded five patents.

processes

Steven J. Hillenius (M’81) received the B.S. de- gree from the University of Delaware, Newark, in 1973, and the Ph.D. degree from the University of Virginia, Charlottesville. in 1978, both in physics.

He was an Assistant Professor of Physics at the University of Virginia from 1978 to 1981 where his research involved low temperature solid state physics. In 1981 he joined AT&T Bell Laborato- ries, Allentown, PA, where he has been primarily interested in silicon device development involving

high-speed bipolar and MOS integrated circuits. His contributions have been in the area of bipolar process development, VLSI technology-device modeling, and MOS device scaling and development. He currently super- vises a group responsible for VLSI technology development.

Dr. Hillenius is a member of the American Physical Society and the American Association for the Advancement of Science.

W. Stewart Lindenberger received the B.S. de- gree in chemistry from Guilford College, Guil- ford, NC, in 1964. He did graduate work in inorganic chemistry at Clarkson College of Tech- nology, Potsdam, NY.

In 1966, he joined Bell Laboratories, Murray Hill, NJ. Since then, he has worked on various materials and processing problems in semicon- ductor electronics. He is presently a Member of the Technical Staff there, involved in electrical and physical characterization of VLSI materials and

George K. Celler (M’86) received the M.Sc. de- gree in physics from the University of Warsaw, Poland, in 1969, and the Ph.D. degree in solid state physics from Purdue University, West La- fayette, IN, in 1976.

During 1970 he was a research scientist at the University of Vienna and at the International Atomic Energy Agency, both in Vienna, Austria. From 1976 to 1979 he was a Member of Research Staff at Western Electric Engineering Research Center in Princeton. NJ. and since 1979 he has

worked at AT&T Bell Laboratories in Murray Hill, NJ. He is now super- visor in Advanced Lithography Research Department. He has investigated interactions of intense light beams with materials, laser annealing, and rapid thermal processing of semiconductors, formation of silicon-on-insulator structures, and diffusion phenomena in Si and Si02 . Presently he is inves- tigating new materials and processes for X-ray lithography masks. He has published over 140 articles, edited three books, and was issued 12 patents.

Dr. Celler is a fellow of the American Physical Society, a member of the Materials Research Society, and the Electrochemical Society, where he is chairman of its ULSI Science and Technology Subcommittee.

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Lee E. Trimhle received the B.S. degree in ce- ramic engineering from the Pennsylvania State University, University Park, and the M.S. degree in materials science and engineering from the Ste- vens Institute of Technology, Hoboken, NJ.

He has spent 19 years in research and devel- opment relating to the semiconductor industry, in areas such as rapid thermal annealing, silicon-on- insulator devices, and proximity X-ray lithogra- phy. He has published over 35 papers and holds five patents.

T. T. Sheng received the B.S. degree from the National Taiwan University in 1952 and the M.S. degree from the University of Texas in 1962, both in electrical engineering.

He worked for the Electron Microscope Laboratory of the University of Texas from 1962 to 1964, and with the Electron Microscope Laboratory of the Materials Science Center at Comell University from 1964 to 1968. He joined AT&T-Bell Laboratories in Murray Hill, N.J., and was there until 1990 when he joined ERSO. He is a Senior Technical Consultant at ERSO/ ITRI. He has authored and coauthored over 60 publications and has won numerous awards for his work in the field of transmission electron micros- copy (TEM). He is the co-author of the well known book-Transmission Electron Microscopy of Silicon VLSI Circuits and Structures, with R. B. Marcus.