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Verilog HDL
Verilog HDL
Introduzida em 1985 pela Gateway Design System Corporation
Após 1990, passou a ser de domínio público, e em 1995 passou a ser padrão IEEE
Verilog HDL vs. VHDL Verilog HDL é mais próxima a C
VHDL é mais próxima a ADA
Considerada mais fácil de aprendizado, pois necessita de menos código para especificar projeto
Níveis de Especificação High level
RTL
Gate level
Switch level
module simple;reg [0:7] A, B;reg C;initial begin: stop_at #20; $stop; endinitial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C);endalways begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; endendmodule
module simple;reg [0:7] A, B;reg C;initial begin: stop_at #20; $stop; endinitial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C);endalways begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; endendmodule
0 1 2 3 … 20
$stop
module simple;reg [0:7] A, B;reg C;initial begin: stop_at #20; $stop; endinitial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C);endalways begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; endendmodule
0 1 2 3 … 20
$stopA=0
$display
$monitor
module simple;reg [0:7] A, B;reg C;initial begin: stop_at #20; $stop; endinitial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C);endalways begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; endendmodule
0 1 2 3 … 20
$stopA=A+1
$monitor
module simple;reg [0:7] A, B;reg C;initial begin: stop_at #20; $stop; endinitial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C);endalways begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; endendmodule
0 1 2 3 … 20
$stopB[0:3] = …
$monitor
module simple;reg [0:7] A, B;reg C;initial begin: stop_at #20; $stop; endinitial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C);endalways begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; endendmodule
0 1 2 3 … 20
$stopC = &A[6:7]
$monitor
module simple;reg [0:7] A, B;reg C;initial begin: stop_at #20; $stop; endinitial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C);endalways begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; endendmodule
3 4 5 6 … 20
$stopA=A+1
…
$monitor
module simple;reg [0:7] A, B;reg C;initial begin: stop_at #20; $stop; endinitial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C);endalways begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; endendmodule
3 4 5 6 … 20
$stopB[0:3] = …
…
$monitor
module simple;reg [0:7] A, B;reg C;initial begin: stop_at #20; $stop; endinitial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C);endalways begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; endendmodule
… 3 4 5 6 … 20
$stopC = &A[6:7]
$monitor
module simple;reg [0:7] A, B;reg C;initial begin: stop_at #20; $stop; endinitial begin: Init A = 0; $display("Time A B C"); $monitor(" %0d %b %b %b", $time, A, B, C);endalways begin: main_process #1 A = A + 1; #1 B[0:3] = ~A[4:7]; #1 C = &A[6:7]; endendmodule
… 20
$stop
Resultado do Primeiro ExemploTime A B C 0 00000000 xxxxxxxx x 1 00000001 xxxxxxxx x 2 00000001 1110xxxx x 3 00000001 1110xxxx 0 4 00000010 1110xxxx 0 5 00000010 1101xxxx 0 7 00000011 1101xxxx 0 8 00000011 1100xxxx 0 9 00000011 1100xxxx 1 10 00000100 1100xxxx 1 11 00000100 1011xxxx 1 12 00000100 1011xxxx 0 13 00000101 1011xxxx 0 14 00000101 1010xxxx 0 16 00000110 1010xxxx 0 17 00000110 1001xxxx 0 19 00000111 1001xxxx 0Stop at simulation time 20
Números e Comentários 549 // decimal number 'h 8FF // hex number 'o765 // octal number 4'b11 // 4-bit binary number 0011 3'b10x // 3-bit binary number with least
/* significant bit unknown */ 5'd3 // 5-bit decimal number -4'b11 // 4-bit two's complement of 0011
Descrição em Verilog HDL
module <module name> (<port list>); <declares> <module items>endmodule
inputs
outputs
inouts
Descrição em Verilog HDL
module <module name> (<port list>); <declares> <module items>endmodule
regs + wires
memories
functions + tasks
initial + always
assinalamentos contínuos
instâncias de módulos
Descrição em Verilog HDL
module <module name> (<port list>); <declares> <module items>endmodule
Exemplos
module NAND(in1, in2, out);
input in1, in2; output out; // continuous assign statement assign out = ~(in1 & in2);
endmodule
Exemplos
module AND(in1, in2, out);// Structural model of AND gate from two NANDS input in1, in2; output out; wire w1; // two instantiations of the module NAND NAND NAND1(in1, in2, w1); NAND NAND2(w1, w1, out);
endmodule
Exemplosmodule test_AND; reg a, b; wire out1, out2; initial begin // Test data a = 0; b = 0; #1 a = 1; #1 b = 1; #1 a = 0; end initial begin $monitor("Time=%0d a=%b b=%b out1=%b out2=%b", $time, a, b, out1, out2); end AND gate1(a, b, out2); NAND gate2(a, b, out1);endmodule
Referências e Concatenações
initial begin: int1 A = 8'b01011010; B = {A[0:3] | A[4:7], 4'b0000};end
C = {2{4'b1011}}; //C = 8'b10111011C = {{4{A[4]}}, A[4:7]}; // first 4 bits are sign extended
Memórias
reg [31:0] Mem [0:1023];
A = Mem[0];B = A[3:1];
Memória de 1024 posições de 32 bits
Operações Operações similares a C
~ Bitwise negation& Bitwise AND| Bitwise OR^ Bitwise XOR~& Bitwise NAND~| Bitwise NOR~^ or ^~ Equivalence Bitwise NOT XOR
Operações Unárias
& AND | OR reduction^ XOR reduction~& NAND reduction~| NOR reduction~^ XNOR reduction
Operações
Fluxo de Controle
if (A == 4) begin B = 2; endelse begin B = 4; end
case(address) 0 : $display ("It is 11:40PM"); 1 : $display ("I am feeling sleepy"); 2 : $display ("Let me skip this tutorial"); default : $display ("Need to complete");endcase
Fluxo de Controlefor(i = 0; i < 10; i = i + 1)begin $display("i= %0d", i);end
i = 0;while(i < 10)begin $display("i= %0d", i); i = i + 1;end
repeat (5)begin $display("i= %0d", i); i = i + 1;end
Controle de Tempo Delay
#10 a = 3;
Ocorrência de eventos
@ (posedge clock2) A = B&C;
@ (A or B or C) D = A + B + C;
Projeto RTLRegister Transfer Level
Componentes básicos
Blocos lógicos combinacionais Unidades funcionais MUXes
Memórias
Registradores
Projeto RTLBlocos Lógicos Combinacionais
always @(a or b or c)begin
case (a)2’b00: d = b + c;
2’b01: d = b – c;2’b10: d = b * c;2’b11: d = b / c;endcase
end
00
01
10
11
d+bc-bc*cb
cb /
Projeto RTLRegistradores
always @ (posedge clk) d = a;
D Qclk
da
Projeto RTLRegistradores
always @ (posedge clk) begin
case (a)2’b00: d = b + c;
2’b01: d = b – c;2’b10: d = b * c;2’b11: d = 0;endcase
end
00
01
10
11
+bc-bc*cb
0
D Q
clk
d
Projeto RTLMemória
reg [15:0] R [0:7];
AD[3:0]
DI[15:0]
WR
DO[15:0]
module uRISC;reg [15:0] PC;reg IF, ID, EX, WB, CLK;always @ (posedge CLK) {IF,ID,EX,WB} = {WB,IF,ID,EX};always @ (posedge CLK) PC = (IF)?PC+1:PC;initial begin IF = 1; ID = 0; EX = 0; WB = 0; PC = 0; CLK = 0; $display("%10d: CLK=%d IF=%d ID=%d ...", $time,CLK,IF,ID,EX,WB,PC); forever begin #10 CLK = 1; # 0 $display("%10d: CLK=%d IF=%d ID=%d ...", $time,CLK,IF,ID,EX,WB,PC); #10 CLK = 0; # 0$display("%10d: CLK=%d IF=%d ID=%d ...", $time,CLK,IF,ID,EX,WB,PC); if ($time > 100) $finish; endendendmodule
http://www.asic-world.com/verilog/veritut.html
Referências