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Circuit design using VHDL 1

VHDL 1

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VHDL 1

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Circuit design

using VHDL

1

Tools required

8/28/2015

Footer Text

2

Number representation

in VHDL

8/28/2015

Footer Text

3

Integers Binary Values

Unsigned Values

Signed Values

Fundamental VHDL Units Library

declarations,

•LIBRARY ieee;

•USE ieee.std_logic_1164.all;

ENTITY

•ENTITY comp_add IS

•PORT (a, b: IN INTEGER RANGE 0 TO 7;

•comp: OUT STD_LOGIC;

• sum: OUT INTEGER RANGE 0 TO 15);

•END ENTITY;

ARCHITECTURE.

•ARCHITECTURE circuit OF comp_add IS

•BEGIN

•comp <= '1' WHEN a>b ELSE '0';

•sum <= a + b;

•END ARCHITECTURE;

8/28/2015

Footer Text

4

Truth tables

Implement the 4x1 using only logical

operators.

Half adder

Page 10: VHDL 1

Full adder

S = a xor b xor cin

Cout = (a AND b) OR (a AND cin) OR (b AND cin)

Page 11: VHDL 1

Excrcies1

Page 12: VHDL 1

Excrcies2

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