Vi Dieu Khien AVR - ATmega128 -© Le Trung Thang 2010.pdf

7/23/2019 Vi Dieu Khien AVR - ATmega128 - Le Trung Thang 2010.pdf

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L Trung Thng

Copyright 2008, 2010 L Trung Thn

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VI IU KHIN AVR ATmega 128 L Trung Thng

http://www.letrungthang.blogspot.com/ 1

Con ngi nh c m m v i

. Ti liuny trc y l seminar mn hc ca ti v vi iu khin AVRvokhong cui nm 2007, lc u cng ch ghi chp nh mt cun s tay ghi nh, n

lc xong ci seminar th thy con AVR ny cng rt th v, nn ti chnh sa li bn ghichp son thnhti liu ny. C l l do quen vi h 8051do Atmel sn xut, nn khichuyn sang AVR s cm thy quen thuc hn.

Mc ch chnh m ti vit ti liu ny l chia s vi cc bn c cng s thch vvi iu khin AVR, qua chng ta c th to ra mt cng ng pht trin da trn AVRtht ng o v si ni. Mt cng ng AVR ng o l rt c ch cho chnh ti v chocc bn,v nh th chng ta s c nhiu c hi trao i v hc hi nhau hn.

Ti liu ny ti cng mun gi tng em traiL Trung Thng, hy vng em c th bsung cho anh nhng phn cn thiu ca ti liu ny.

Tonb ti liu ny ch yu c dch ra t datasheet ca con Atmega128, nhng

do khng c nhiu thi gian nnti liucn thiu rt nhiuphn, nn hi vng cc bn noc kinh nghim v AVR s tip tc b sung, chnh sa chng ta c mt ti liu honchnh hn.

Si Gn, 08-2008.

L Trung Thng.

H Khoa Hc T Nhin TP. H Ch Minh - K2002.


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Mc Lc:

Chng I ------------------------------------TNG QUAN.Chng II -----------------------------------CU TRC B NH V CNG VO - RA.Chng III ----------------------------------B NH THI CA ATmega128.Chng IV ----------------------------------CU TRC NGT CA ATmega128.Chng V -----------------------------------CC B PHN NGOI VI KHC.Chng VI -----------H THNG XUNG CLOCK V LP TRNH B NH ON-CHIP.Chng VII --------------------------------- LP TRNH AVR BNG NGN NG C.Chng VIII--------------------------------TNG QUAN V REAL TIME OS.


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Chng ITNG QUAN

Nhng Tnh Nng Chnh Ca ATmega128: ROM : 128 Kbytes SRAM: 4Kbytes

EEPROM : 4Kbytes 64 thanh ghi I/O

160 thanh ghi vo ra m rng 32 thanh ghi a mc ch. 2 b nh thi 8 bit (0,2).

2 b nh thi 16 bit (1,3). B nh thi watchdog B dao ng ni RC tn s 1MHz, 2 MHz, 4 MHz, 8 MHz

ADC 8 knh vi phn gii 10 bit ( dng Xmega ln ti 12 bit ) 2 knh PWM 8 bit

6 knh PWM c th lp trnh thay i phn gii t 2 ti 16 bit B so snh tng t c th la chn ng vo Hai khi USART lp trnh c Khi truyn nhn ni tip SPI Khi giao tip ni tip 2 dy TWI H tr boot loader 6 ch tit kim nng lng La chn tn s hot ng bng phn mm

ng gi 64 chn kiu TQFP. Tn s ti a 16MHz

in th :4.5v - 5.5vv.v

Vi iu khin AVR do hng Atmel ( Hoa K ) sn xut c gi thiu ln u nm1996. AVR c rt nhiu dng khc nhau bao gm dng Tiny AVR ( nh AT tiny 13, ATtiny 22) c kch thc b nh nh, t b phn ngoi vi, ri n dng AVR ( chn hnAT90S8535, AT90S8515,) c kch thc b nh vo loi trung bnh v mnh hn ldng Mega ( nh ATmega32, ATmega128,) vi b nh c kch thc vi Kbyte n vi

trm KB cng vi cc b ngoi vi a dng c tch hp trn chip, cng c dng tch hpc b LCD trn chip( dng LCD AVR ). Tc ca dng Mega cng cao hn so vi ccdng khc. S khc nhau c bn gia cc dng chnh l cu trc ngoi vi, cn nhn th vnnh nhau, Hnh 1.1. t bit, nm 2008, Atmel li tip tc cho ra i dng AVR mi l

XmegaAVR, vi nhng tnh nng mnh m cha tng c cc dng AVR trc . C thni XmegaAVR l dng MCU 8 bit mnh m nht hin nay.


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Hnh1.1 Cc dng AVR khc nhau: Tiny, AVR v Mega

Cu trc c bn ca vi iu khin AVR c th hin hnh 1.2.

Hnh 1.2. Cu trc ca Vi iu khin AVR


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Chng IICU TRC B NH V CNG VO - RA

I. CU TRC B NH

Gii Thiu:B nh vi iu khin AVR c cu trc Harvard l cu trc c ng Bus ring cho

b nh chng trnh v b nh d liu. B nh AVR c chia lm 2 phn chnh: B nhchng trnh ( program memory ) v b nh d liu ( Data memory ).

B Nh Chng Trnh: B nh chng trnh ca AVR l b nh Flash cdung lng 128 K bytes. B nh chng trnh c rng bus l 16 bit. Nhnga ch u tin ca b nh chng trnh c dng cho bng vc t ngt ( xem

chi tit v bng vc t ngt chng 4 ). Cn l vi iu khinATmega128 b nh chng trnh cn c th c chia lm 2 phn : phn bootloader ( Boot loader program section ) v phn ng dng ( Application programsection ).

Phn boot loader cha chng trnh boot loader. Chng trnh Bootloader l mt phn mm nh np trong vi iu khin v c chy lc khing. Phn mm ny c th ti vo trong vi iu khin chng trnh ca ngis dng v sau thc thi chng trnh ny. Mi khi reset vi iu khin CPU snhy ti thc thi chng trnh boot loader trc, chng trnh boot loader s dxem c chng trnh no cn np vo vi iu khin hay khng, nu c chng

trnh cn np, boot loader s np chng trnh vo vng nh ng dng(Application program section ), ri thc thi chng trnh ny. Ngc li, bootloader s chuyn ti chng trnh ng dng c sn trong vng nh ng dng thc thi chng trnh ny.

Phn ng dng (Application program section ) l vng nh cha chngtrnh ng dng ca ngi dng. Kch thc ca phn boot loader v phn ngdng c th ty chn. Hnh 2.1th hin cu trc b nhchng trnh c s dngv khng s dng boot loader, khi s dng phn boot loader ta thy 4 word utin thay v ch th cho CPU chuyn ti chng trnh ng dng ca ngi dng(l chng trnh c nhn start ) th ch th CPU nhy ti phn chng trnh bootloader thc hin trc, ri mi quay tr li thc hin chng trnh ng dng.


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Hnh 2.1 Bnh chng trnh c v khng c s dng boot loader

B Nh D Liu : B nh d liu ca AVR chia lm 2 phn chnh l b nhSRAM v b nh EEPROM. Tuy cng l b nh d liu nhng hai b nh ny li tch bitnhau v c nh a ch ring.

B nh SRAM c dng lng 4 K bytes, B nh SRAM c hai ch hot ngl ch thng thng v ch tng thch vi ATmega103, mun thit lp b nhSRAM hot ng theo ch no ta s dng bit cu ch M103C ( M103C fuse bit(9)).

B nh SRAM ch bnh thng: ch bnh thng b nh SRAM cchia thnh 5 phn:Phn ul 32 thanh ghi chc nng chung (General Purpose Register )R0 n R31 c a ch t $0000 ti $001F. Phn th 2 l khng gian nh vo ra vi 64thanh ghi vo ra ( I/O Register ) c a ch t $0020 ti $005F.Phn th 3 dng cho vngnh dnh cho cc thanh ghi vo ra m rng ( Extended I/O Registers ) c a ch t $0060ti $00FF. Phn th 4 l vng SRAM ni vi 4096 byte c a ch t $0100 ti $10FF.

Phn th 5l vng nh SRAM ngoi ( External SRAM ) bt u t a ch $1100, vngSRAM m rng ny c th m rng ln n 64 K byte. Khi ni b nh SRAM c dung


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lng 4 K byte l ni ti phn th 4 ( SRAM ni ). Nu tnh c cc thanh ghi th b nhSRAM trong ch bnh thng s l 4.25 K byte = 4352 byte.

B nh SRAM ch tng thch ATmega103 : ch ny b nh SRAM cbn cng ging ch bnh thng, ngoi tr phn th 3 l vng nh dnh cho cc thanh

ghi vo ra m rng khng tn ti, ngoi ra kch thc ca phn SRAM ni ( internalSRAM ) ch c 4000 byte so vi 4096 byte ch bnh thng. Hnh 2.2 th hin s b nh d liu c hai ch : Bnh thngv tng thch ATmega103. T hnh 2.2tathy nu cu hnh b nh SRAM hot ng ch tng thch ATmega103 th ta s

b mt i 160 thanh ghi vo ra m rng ( extended I/O Register ), l nhng thanh ghi ngvai tr quan trng trong cc ch hotng ca vi iu khin.

Hnh 2.2 Bn b nh d liu

A: Ch bnh thngB: Ch tng thch ATmega103

Trong vng nh vo ra m rng ( $0060 - $00FF ) ch c 6 lnh sau l c th cs dng, l : ST / STS / STD v LD / LDS / LDD.


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Lnh CBI v SBI ch c th lm vic vi 32 thanh ghi thp hn trong vng nh vora , tc cc thanh ghi I/O c a ch t $20 ti $3F ( a ch SRAM ).

64 thanh ghi vo ra trong vng nh vo ra ( phn s 2 ) c 2 kiu chn a ch : Nuxem chng l vng nh vo ra th a ch s l $00 - $3F, khi s dng cc lnh in, out ta

phi s dng a ch ny. Nu xem chng nh l mt phn ca b nh SRAM th s c ach l $0020 - $005F, khi ta dng cc lnh nh LD, ST ta phi s dng kiu a ch ny.(hnh 2.3). Trong ti liu ny cc a ch c s dng s c hiu nh l a ch SRAMnu khng c gii thch g thm. l 160 thanh ghi vo ra m rng ( $0060 - $00FF )khng c 2 kiu chn a ch nh trn, a ch ca chng chnh lcc a ch SRAM .

Hnh 2.3 Vng nh 64 thanh ghi vo ra c 2 cch chn a ch

Chi tit v 64 thanh ghi vo ra v 160 thanh ghi vo ra m rng c th tm thy datasheet ca vi iu khin ATmega128.

Tip ghanh ghi ( register file ) : Tip 32 thanh ghi a chc nng ( $0000 - $001F ) c ni trn, ngoi chc nng l cc thanh ghi a chc nng, th cc thanh ghi t R26ti R31 tng i mt to thnh cc thanh ghi 16 bit X, Y, Z c dng lm con tr tr ti

b nh chng trnh v b nh d liu ( Hnh 2.4). Thanh ghi con tr X, Y c th dnglm con tr tr ti b nh d liu, cn thanh ghi Z c th dng lm con tr tr ti b nh


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chng trnh.Cc trnh bin dch C thng dng cc thanh ghi con tr ny qun l Datastackca chngtrnh C.

Hnh 2.4. Chc nng con tr ca cc thanh ghi R26 R31

B nh EEPROM: y l b nh d liu c th ghi xa ngay trong lc vi iukhin ang hot ng v khng b mt d liu khi ngun in cung cp b ct. C th v bnh d liu EEPROM ging nh l cng ( Hard disk ) ca my vi tnh. Vi vi iu khin

ATmega128, b nh EEPROM c kch thc l 4 Kbyte. EEPROM c xem nh l mtb nh vo ra c nh a ch c lp vi SRAM, iu ny c ngha l ta cn s dngcc lnh in, out khi mun truy xut ti EEPROM. iu khin vo ra d liu viEEPROM ta s dng 3 thanh ghi sau :

1. Thanh Ghi EEAR ( EEARH v EEARL )


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EEAR l thanh ghi 16 bit lu gi a ch ca cc nh ca EEPROM, thanh ghiEEAR c kt hp t 2 thanh ghi 8 bit l EEARH v thanh ghi EEARL. V b nhEEPROM ca ATmega128 c dung lng 4 Kbyte = 4096 byte = 212byte nn ta ch cn 12

bit ca thanh ghi EEAR , 4 bit t 15 -12 c d tr, ta nn ghi 0 vo cc bit d tr ny.

2. Thanh Ghi EEDR

y l thanh ghi d liu ca EEPROM, l ni cha d liu ta nh ghi vo hay lyra t EEPROM.

3. Thanh Ghi EECR

yl thanh ghi iu khin EEPROM, ta ch s dng 4 bit u ca thanh ghi ny, 4bit cui l d tr, ta nn ghi 0 vo cc bit d tr. Sau y ta xt chc nng ca tng bit.

Bit 3 EERIE: EEPROM Ready Interrupt Enable : y l bit cho phpEEPROM ngt CPU, khi bit ny c set thnh 1 v ngt ton cc c cho php ( bng


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cch set bit I trong thanh ghi SREG ln 1 ) th EEPROM s to ra mt ngt vi CPU khi bitEEWE c xa, iu ny c ngha l khi cc ngt c cho php ( bit I trong thanh ghiSREG v bit EERIE trong thanh ghi EECR c set thnh 1 ) v qu trnh ghi vo ROMva xong th s to ra mt ngt vi CPU, chng trnh s nhy ti vc t ngt c a ch l

$002C thc thi chng trnh phc v ngt ( ISR ). Khi bit EERIE l 0 th ngt khngc cho php. Bit 2 EEMWE: EEPROM Master Write Enable : Khi bit EEMWE v bit

EEWE l 1 s ra lnh cho CPU ghi d liu t thanh ghi EEDR vo EEPROM, a ch ca nh cn ghi trong EEPROM c lu trong thanh ghi EEAR . Khi bit ny l 0 th khngcho php ghi vo EEPROM. Bit EEMWE s c xa bi phn cng sau 4 chu k my.

Bit 1EEWE: EEPROM Write Enable : Bit ny va ng vai tr nh mt bitc, va l bit iu khin vic ghi d liu vo EEPROM. vai tr ca mt bit iu khinnu bit EEMWE c set ln 1 th khi ta set bit EEWE ln 1 s bt u qu trnh ghi dliu vo EEPROM. Trong sut qu trnh ghi d liu vo EEPROM bit EEWE lun gi l 1.

vai tr ca mt bit c khi qu trnh ghi d liu vo EEPROM hon tt, phn cng s tng xa bit ny v 0. Trc khi ghi d liu vo EEPROM ta cn phi bit chc l khngc qu trnh ghi EEPROM no khc ang xy ra, bit c iu ny ta cn kim tra bitEEWE. Nu bit EEWE l 1 tc l EEPROM ang c ghi, ta phi ch cho cho qu trnhghi vo EEPROM hon tt th mi ghi tip. Nu bit EEWE l 0 tc l khng c qu trnhghi EEPROM no ang din ra, lc ny ta c th bt u ghi d liu vo EEPROM. Khi bitEEWE c set ln 1 ( bt u ghi vo EEPROM ) CPU s tm ngh trong 2 chu k mytrc khi thc hin lnh k tip.

Bit 0 EERE: EEPROM Read Enable : Khi bit ny l 1, s cho php c dliu t EEPROM, d liu t EEPROM c a ch lu trong thanh ghi EEAR lp tc cchuyn vo thanh ghi EEDR. Khi bit EERE l 0 th khng cho php c EEPROM. Trckhi c d liu t EEPROM ta cn bit chc l khng din ra qu trnh ghi EEPROM bngcch kim tra bit EEWE. l sau khi qu trnh c EEPROM hon tt, bit EERE sc t ng xo bi phn cng. Nu EEPROM ang c ghi th ta khng th c cd liu t EEPROM. Khi bt u qu trnh c d liu t EEPROM, CPU s tm ngh 4chu k my trc khi thc hin lnh k tip.

Tm li ghi vo EEPROM ta cn thc hin cc bc sau:1. Ch cho bit EEWE v 0.2. Cm tt c cc ngt.3. Ghi a ch vo thanh ghi EEAR.4. Ghi d liu m ta cn ghi vo EEPROM vo thanh ghi EEDR.5. Set bit EEMWE thnh 1.6. Set bit EEWE thnh 1 .7. Cho php cc ngt tr li.

Nu mt ngt xy ra gia bc 5 v 6 s lm hng qu trnh ghi vo EEPROM biv bit EEMWE sau khi set ln 1 ch c gi trong 4 chu k my, chng trnh ngt s lmht thi gian ( time out ) duy tr bit ny mc 1.


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Mt ngt xut hin cui bc 4 cng c th lm cho a ch v d liu cn ghi voEEPROM tr nn khng chnh xc nu trong chng trnh phc v ngt c chnh sa licc thanh ghi EEAR v EEDR. l l do ta cn cm cc ngt trc khi thc hin tip cc

bc 3, 4, 5, 6.

Qu trnh ghi d liu vo EEPROM cng c th khng an ton nu in th ngunnui ( Vcc ) qu thp.on chng trnh sau thc hin qu trnh ghi d liu vo EEPROM.

EEPROM_write:; ch cho bit EEWE v 0

sbic EECR,EEWE

rjmp EEPROM_write;cm cc ngtcli

;ghi a ch vo thanh ghi EEARout EEARH, r18out EEARL, r17

; Ghi d liu vo thanh ghi EEDRout EEDR,r16

; set bit EEMWE thnh 1

sbi EECR,EEMWE; Set bit EEWE ln 1 bt u ghi vo EEPROM

sbi EECR,EEWE; cho php cc ngt hot ng tr li

seiret

c d liu t EEPROM:

Vic c d liu t EEPROM n gin hn ghi d liu vo EEPROM, c dliu t EEPROM ta thc hin cc bc sau:

1.

Ch cho bit EEWE v 0.2. Ghi a ch vo thanh ghi EEAR.3. Set bit EERE ln 1.on chng trnh sau thc hin qu trnh c d liu t EEPROM.


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EEPROM_read:; ch cho bit EEWE v 0

sbicEECR,EEWErjmpEEPROM_read

; a a ch vo thanh ghi EEAR outEEARH, r18outEEARL, r17

; Set bit EERE bt u c EEPROMsbiEECR,EERE

; a d liu vo thanh ghi R16inr16,EEDR

ret

Tm tc: Bn b nh bn trong ca ATmega128 c th tm tc li nh sau:

Hnh 2.5. Tm tc bn b nh ATmega128


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II. CNG VO RA

II.1. GIITHIU

Cng vo ra l mt trong s cc phng tin vi iu khin giao tip vi ccthit b ngoi vi. ATmega128 c c thy 7 cng ( port ) vo ra 8 bit l : PortA, PortB,PortC, PortD, PortE, PortF, PortG, tng ng vi 56 ng vo ra. Cc cng vo ra caAVR l cng vo ra hai chiu c th nh hng, tc c th chn hng ca cng l hngvo (input ) hay hng ra (output ). Tt cc cc cng vo ra ca AVR iu c tnh nngc Chnh sa Ghi ( ReadModifywrite ) khi s dng chng nh l cc cng vo ras thng thng. iu ny c ngha l khi ta thay i hng ca mt chn no th nkhng lm nh hng ti hng ca cc chn khc. Tt c cc chn ca cc cng ( port )iu c in tr ko ln ( pull-up ) ring, ta c th cho php hay khng cho php in trko ln ny hot ng.

in tr ko ln l mt in tr c dng khi thit k cc mch in t logic. Nc mt u cni vi ngun in p dng (thng l Vcc hoc Vdd) v u cn lic ni vi tn hiu li vo/raca mt mch logic chc nng.in tr ko ln c thc lp t ti cc li voca cc khi mch logic thit lp mc logic livo ca khimch khi khng c thit b ngoi ni vi li vo. in tr ko ln cng c th c lp tti cc giao din gia hai khi mch logickhng cng loi logic, c bit l khi hai khimch

ny c cp ngun khc nhau. Ngoi ra, in tr ko ln cn c lp t ti li raca khi mch

khi li ra khng th ni ngun to dng, v d cc linh kin logic TTL ccc gp h.

i vi h logic lng cc vi ngun nui 5 Vdc th gi tr ca in tr koln thng nm trongkhong 1000 n 5000 Ohm, ty theo yu cu cp dng trn ton

gii hot ng ca mch. Vi lgc

CMOS v lgc MOS chng ta c th s dng cc intr c gi tr ln hn nhiu, thng t vi

ngn nmt triu Ohm do dng r r cn thit li vo l rt nh.Trong vic thit k cc vi mch ng dng, nu mt IC c ng ra loi ccthu h giao tip vi

nhiu IC khc th gi tr ca in tr ko ln s tng i nh(khong vi trm Ohm). Bi v lc nyh s fanout ln dn n dng ng ra ca IC philn cung cp cho cc ng vo ca cc IC

khc, nu khng vi mch s hot ng chpchn hoc c th khng hot ng.

II.2. CCH HOTNG:

Khi kho st cc cng nh l cc cng vo ra s thng thng th tnh cht ca cccng ( PortA, PortB,PortG ) l tng t nhau, nn ta ch cn kho st mt cng no trong s 7 cng ca vi iu khin l .

Mi mt cng vo ra ca vi iu khin c lin kt vi 3 thanh ghi : PORTx,DDRx, PINx. ( y x l thay th cho A, B,G ). Ba thanh ghi ny s c phi hp


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vi nhau iu khin hot ng ca cng, chn hn thit lp cng thnh li vo c sdng in tr pull-up, ..v.v.. . Sau y l din t c th vai tr ca 3 thanh ghi trn.

a. Thanh Ghi DDRx.

yl thanh ghi 8 bit ( c th c ghi ) c chc nng iu khin hng ca cng(l li ra hay li vo ). Khi mt bit ca thanh ghi ny c set ln 1 th chn tng ng vin c cu hnh thnh ng ra. Ngc li, nu bit ca thanh ghi DDRx l 0 th chn tngng vi n c thit lp thnh ng vo. Ly v d: Khi ta set tt c 8 bit ca thanh ghiDDRA u l 1, th 8 chn tng ng ca portA l PA1, PA2, PA7 ( tng ng vi ccchn s 50, 49, 44 ca vi iu khin ) c thit lp thnh ng ra.

Thanh ghi DDRA

b. Thanh Ghi PORTx.PORTx l thanh ghi 8 bit c th c ghi. y l thanh ghi d liu ca PORTx, Nu

thanh ghi DDRx thit lp cng l li ra, khi gi tr ca thanh ghi PORTx cng l gi trca cc chn tng ng ca PORTx, ni cch khc, khi ta ghi mt gi tr logic ln 1 bit cathanh ghi ny th chn tng ng vi bit cng c cng mc logic. Khi thanh ghi DDRxthit lp cng thnh li vo th thanh ghi PORTx ng vai tr nh mt thanh ghi iu khin

cng. C th , nu mt bit ca thanh ghi ny c ghi thnh 1 th in tr treo ( pull-upresistor ) chn tng ng vi n s c kch hot, ngc li nu bit c ghi thnh 0 thin tr treo chn tng ng s khng c kch hot, cng trng thi cao tr ( Hi-Z ).

Thanh ghi PORTA

c. Thanh Ghi PINx.PINx khng phi l mt thanh ghithc s, y l a ch trong b nh I/O kt ni

trc tip ti cc chn ca cng. Khi ta c PORTx tc ta c d liu c cht trongPORTx, cn khi c PINx th gi tr logic hin thi chn ca cng tng ng c c.


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V th i vi thanh ghi PINx ta ch c th c m khng th ghi. Bng 25 th hin cc ccthit lp cch hot c th c ca cng.

Thanh ghi PINA

DDRxn PORTxn PUD ( Trongthanh ghi SFIOR

I/O Pull-up Ch thch

0 0 x Ng vo khng Cao tr0 1 0 Ng vo c Nh mt ngun dng0 1 1 Ng vo khng Cao tr1 0 x Ng ra khng Ng ra thp1 1 x Ng ra khng Ng ra cao

Bng 25. Cu hnh cho cc chn cngDDRxn l bit th n ca thanh ghi DDRxPORTxn l bit th n ca thanh ghi PORTxDu x ct th 3 ch gi tr logic l ty


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Hnh 30. S mt cng vo raHnh 30th hin s ca mt chn ca cng vo ra. s trn ta thy ngoi 2

bit ca cc thanh ghi DDRx v PORTx tham gia iu khin in tr treo (pull-up resistor ),cn c mt tn hiu na iu khin in tr treo, l tn hiu PUD, y l bit nm trongthanh ghi SFIOR, khi set bit ny thnh 1 th in tr ko ln s khng c cho php btk cc thit lp ca cc thanh ghi DDRx v PORTx. Khi bit ny l 0 th in tr ko lnc cho php nu { DDRxn, PORTxn } = { 0, 1 } .

Thanh ghi SFIOR


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I. B NH THI 1.S khi b nh thi 1 (3):

B nh thi 1 v 3 l b nh thi 16 bit, b nh thi 1 s dng 13 thanh ghi linquan, cn b nh thi 3 s dng 11 thanh ghi lin quan vi nhiu ch thc thi khcnhau.V b nh thi 1 v 3 hot ng ging nhau nn y ch trnh by b nh thi 1.Mt m cn l trong cc thanh ghi lin quan ti b nh thi 1 v 3 th c nhiuthanh ghi c chia s cho c hai b nh thi, chn hn thanh ghi ETIPR c bt cui l


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OCF1C c dng cho b nh thi 1, cc bit cn li l dng cho b nh thi 3.Thm ch c nhng thanh ghi chia s cho b nh thi 0 hoc 2, chn hn thanh ghiTIMSK c hai bit cui dng cho b nh thi 2, hai bit udng cho b nh thi 0, cc

bit cn li dng cho b nh thi 1.Cc thanh ghi lin quan ti b nh thi 3 cng c

lit k ra m khng cn gii thch chi tit, tuy vy cng c vi khc bit nh gia b nhthi 1 v 3 c ch thch cho tng trng hp c th trong mc B nh Thi 3. tmhiu v b nh thi1 (3) ta cn nm vng cc thanh ghi lin quan ti b nh thi 1(3) vcc ch hot ng ca b nh thi. CC NH NGHA:

Cc nh ngha sau s c s dng cho b nh thi 1 v 3 :BOTTOM B m t ti gi tr BOTTOM khi n c gi tr 0000hMAX B m t ti gi tr MAX khi n bng FFFFhTOP B m t gi tr TOP khi n bng vi gi tr cao nht trong chui

m, gi trcao nht trong chui m khng nht thit l FFFFh m c th l bt kh gi tr

no c qui nh trong thanh ghi OCRnX (X=A,B,C) hay ICRn, ty theo ch thc thi.

CC THANH GHI B NH THI 1.

1. Thanh ghi TCCR1A (Timer/Counter1 Control Register)

Bit 7:6COMnA1:0: Compare Output Mode for Channel A Bit 5:4COMnB1:0: Compare Output Mode for Channel B Bit 3:2COMnC1:0: Compare Output Mode for Channel C Bit 1:0 WGMn1:0: Waveform Generation Mode

Bit 7:2COMnX1:0 (X=A, B, C): Compare Output Mode for Channel X:iu khin cch hot ng ca ng ra so snh (compare output) ca ln lt cc chnOCnA, OCnB v OCnC. Nu mt hay c hai bit COMnA1:0 c set ln 1 th ng ra

OCnA su tin hn chc nng port I/O thng thng m n kt ni ti . Nu mt hay chai bit COMnB1:0 c set ln 1 th ng ra OCnB su tin hn chc nng port I/Othng thng m n kt ni ti . Nu mt hay chai bit COMnC1:0 c set ln 1 th ngra OCnC su tin hn chc nng port I/O thng thng m n kt ni ti, iu ny cngha l mi mt chn ca vi iu khin c ththc hin nhiu chc nng khc nhau, bnhthng cc chn OCnA, OCnB, OCnC hot ng nh cc chn vo ra thng thng, nhng


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khi bnh thi ang hot ng cc ch c s dng ti chc nng so snh khp(compare match) nh cc chCTC, PWM,ca bnh thi th hnh vi ca chnng ra OCnA, OCnB, OCnC s do bnh thi iu khin. Tuy nhin ch l bit cathanh ghi DDR tng ng vi cc chn OCnA,OCnB, OCnC phi c set cho php

ng ra. Khi OCnA, OCnB, OCnC c kt ni ti chn th tc dng ca cc bitCOMnX1:0 cn phthuc vo la chn ca cc bit WGM3:0, nghal khi ta set mt haychai Bit COMn1:0 ln 1 th chc nng ng ra so snh c u tin, tuy nhin cch hotng ng ra OCnX nh th no th cn ph thuc vo vic la chn ca cc bitWGMn3:0, c thhin trong cc bng di (Bng 58, 59, 60).Trong cc chPWM, khi gi trcc thanh ghi dng so snh(OCRnX, ICRn) c gitrbng vi TOP, th skin so snh khp (compare match) bbqua. Tuy vy cc chnOCnX vn bset hay xa (ty vo cc bit COMnX 1:0) BOTTOM.

Bng 58. Hnh vi ca cc chn OCnX (X=A, B, C; n=1, 3) phthuc vo cc thit lpca cc bit COMnA1:0, COMnB1:0, COMnC1:0 trong chnon-PWM


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Bng 59. Hnh vi ca cc chn OCnX (X=A, B, C; n=1, 3) phthuc vo cc thit lpca cc bit COMnA1:0, COMnB1:0, COMnC1:0 tromg chFast-PWM

Bng 60.Hnh vi ca cc chn OCnX (X=A, B, C; n=1, 3) ph thuc vo ccthit lp ca cc bit COMnA1:0, COMnB1:0, COMnC1:0 tromg ch PWM hiuchnh pha v tn s


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Bit 1:0 WGMn1:0: Waveform Generation Mode : Kt hp vi cc bitWGMn3:2 tm trong thanh ghi TCCRnB , nhng bit ny cho php ta la chn chthcthi ca bnh thi, nh c thiu khin vic m tun tca bm. Gi tr b mln nht l TOP v dng sng to ra chn OCnX (X=A, B, C; n=1, 3) c sdng cho

nhiu mc ch khc nhau (bng 61). Cc ch thc thi c h tr bi khiTimer/counter l : Normal mode ( counter ), Clear Timer on Compare match (CTC) mode ,PWM mode. l vi bnh thi 1 th c 4 bit WGM l: WGM13, WGM12,WGM11v WGM10.

Bng 61.La chn cc chthc thi ca bnh thi 1(3)

2. Thanh ghi TCCR1B

Bit 7 ICNCn: Input Capture Noise Canceler Bit 6 ICESn: Input Capture Edge Select Bit 5 Reserved Bit


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Bit 4:3 WGMn3:2: Waveform Generation Mode Bit 2:0 CSn2:0: Clock Select

Bit 7 ICNCn: Input Capture Noise Canceler(vit tt: ICNC): Vic set bit ny ti

1 skch hot chc nng chng nhiu ca bchng nhiu li vo ( ICNC ). Khi chcnng ICNC c kch hot th ng vo tchn ICPn sc lc. Chc nng lc i hi 4mu c gi trbng nhau lin tip chn ICPn cho sthay i ng ra ca n ( xem chi titvkhi Input Capture).

Bit 6 ICESn: Input Capture Edge Select: Bit ny la chn cnh chn InputCapture Pin (ICPn) dng bt s kin trigger( Trigger event (10)). Khi bit ICESn cthit lp thnh 0 th mt cnh dng xung (falling (3) ) c dng nh mt trigger ( tnhiu ny). Ngc li, khi bit ny c set thnh 1 th mt cnh m ln (rising (4) ) cdng nh mt trigger.Khi xy ra s kin Input capture(2)(theo thit lp ca bit ICESn l 1hay 0) th gi tr ca b mc ghi vo thanh ghi Input Capture Register ICRn (n=1, 3),

v khi c ICFn (Input CaptureFlag) c set.iu ny s to ra mt ngt Input capturenu ngt ny c cho php.Khi thanh ghi ICRn c s dng nh mt gi tr TOP thchn ICPn khng c kt ni v v th chc nngInput capture khng c cho php.

Bit 5 : D tr. Bit 4:3 WGMn3:2: Waveform Generation Mode: ni phn thanh ghi

TCCR1A. Bit 2:0 CSn2:0: Clock Select : Dng la chn tc xung clock (xem bng

62). cm b nh thi hot ng tach cn cho {CSn2, CSn1, CSn0} = {0, 0, 0}.

Bng 62.La chn tc xung clock


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3. Thanh ghi TCCR1C

Bit 7FOCnA: Force Output Compare for Channel A Bit 6FOCnB: Force Output Compare for Channel B Bit 5FOCnC: Force Output Compare for Channel C Bit 4:0Reserved Bits

Cc bit FOCnA/FOCnB/FOCnC ch hot ng khi cc bit WGMn3:0 ch nh ch Non-PWM. Khi cc bit FOCnA/FFOCnB/FOCnC c set thnh1 th ngay lp tc mt skin So snh khpcng ch (Forced Compare Match (1) ) xy ra trong b to sng.Ng ra OCnA/OCnB/OCnC c thay i theo thit lp ca ccbit COMnX 1:0 (n=1, 3;

X=A, B, C), ngha l bnh thng s kin so snh khp ch xy ra khi khi gi tr b nhthi (thanh ghi TCNTn (n=1, 3) ) bng vi gi tr thanh ghi OCRnX( n=1,3; X=A,B,C),nhng khi cc bit FOCnX( n=1, 3; X=A, B, C) c set thnh 1 th s kin so snhkhp s xy ra mc d gi tr ca b nh thi khng bng vi gi tr ca thanh ghiOCRnX( n=1,3; X=A,B,C). Ch l cc bit FOCnA/FOCnB/FOCnC cng hot ng nhl nhngque d (strobe), v th n l gi trhin thi ca cc bit COMnX1:0 xc nh tcng ca so snh cng ch (forced compare). Cc que d FOCnA/FOCnB/FOCnCkhng to ra bt k ngt no v cng khng xa b nh thi trong ch CTC s dngthanh ghi OCRnA nh l gi tr TOP.Cc bit FOCnA/FOCnB/FOCnC ch c th ghi, khic cc bit ny ta lun nhn c gi tr 0.

Bit 4:0 d tr ,phi ghi thnh 0 khi ghi vo thanh ghi TCCRnC.

4.Thanh GhiTimer/Counter1TCNT1H and TCNT1L

Thanh ghi b nh thi TCNT1 l thanh ghi 16 bit c kt hp t hai thanh ghiTCNT1H v thanh ghi TCNT1L. Thanh ghi TCNT1 c th c hay ghi. c 2 byte caTCNT 1 c c hay ghi ng thi ngi ta dng mt thanh ghi tm 8 bit byte cao 8-bitTemporary High Byte Register (TEMP). Thanh ghi TEMP c chia s cho tt c ccthanh ghi 16 bit khc. Khng nn chnh sa thanh ghi TCNTn (n=1,3) khi n ang m trnh b hng CompareMatch gia TCNTn v mt trong nhng thanh ghi OCRnX(n=1,3.X=A,B,C).


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5. Thanh Ghi Output Compare Register 1 AOCR1AH and OCR1AL

6. Thanh Ghi Output Compare Register 1 BOCR1BH and OCR1BL

7. Thanh Ghi Output Compare Register 1 COCR1CH and OCR1CL

Thanh ghi output compare register (OCR1A/OCR1B/OCR1C) l thanh ghi 16 bit,

gi tr can c lin tc so snh vi b m (TCNT1).Khi c s bng nhau ca haithanh ghi ny sto ra mt ngt so snh hay mt dng sng chn ng ra so snh OCnX(X=A,B,C). Ging nh thanh ghi TCNT1 , thanh ghi OCRnX (X=A,B,C) cng l thanh ghi16 bit nn c hai byte cao v thp ca thanh ghi c ghi hay c ng thi khi CPUcn truy xut thanh ghi ny, ngi ta dng thanh ghi tm byte cao (TEMP), thanh ghiTEMP lun lu gi byte caoca cc thanh ghi 16 bit khi cc thanh ghi ny cn dng ti n(xem hnh 3.1). Ch l khi ghi mt gi tr vo thanh ghi OCRnX trong lc b m angchy, th gi tr ca thanh ghi OCRnX c th cp nht tc thi, nhng cng c th ch ccp nht khi b m t ti mt gi tr no (bng 61), chn hn, gi tr TOP,BOTTOM


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Hnh 3.1. Thanh ghi TEMP

8. Thanh Ghi Input Capture Register 1ICR1H and ICR1L

Thanh ghi Input capture (ICR1n) s cp nht gi tr ca b m TCNTn mi khi xyra s kin chn ICPn.Ngoi ra thanh ghi ny cn c s dng nh ngha gi tr TOPca b m.Ngi ta cng s dng thanh ghi TEMP khi cn truy xut thanh ghi ICRn(n=1, 3).

9. Thanh GhiTimer/Counter Interrupt Mask RegisterTIMSK (Interrupt forTimer/counter 1)

Bit 5 TICIE1: Timer/Counter1, Input Capture Interrupt Enable Bit 4 OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable Bit 3 OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable Bit 2 TOIE1: Timer/Counter1, Overflow Interrupt Enable


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Bit 5TICIE1: Timer/Counter1, Input Capture Interrupt Enable: Khi bit nyc set thnh 1 v ngt ton cc (global interrupt) c cho php th ngt bt mu ngvo b Timer/couter1 (Timer/Counter1 Input Capture interrupt) c cho php. Vector

ngt tng ng s c thc thi khi c ICF1 trong thanh ghi TIFR c set.Bit 4 OCIE1A: Timer/Counter1, Output Compare A Match Interrupt

Enable:Khi bit ny c setthnh 1 v ngt ton cc (global interrupt) c cho php thngt so snh ng ra 1A (Timer/Counter1 Output Compare A Match Interrupt) c chophp. Vector ngt tng ng s c thc thi khi c OCF1A trong thanh ghi TIFR cset.

Bit 3 OCIE1B: Timer/Counter1, Output Compare B Match InterruptEnable: Khi bit ny c setthnh 1 v ngt ton cc (global interrupt) c cho php thngt so snh ng ra 1B (Timer/Counter1 Output Compare B Match Interrupt) c cho

php. Vector ngt tng ng s c thc thi khi c OCF1B trong thanh ghi TIFR c

set. Bit 2 TOIE1: Timer/Counter1, Overflow Interrupt Enable:Khi bit ny cset thnh 1 v ngt ton cc (global interrupt) c cho php th ngt c trn b nh thi 1(Timer/Counter1 overflow interrupt) c cho php. Vector ngt tng ng s c thcthi khi c TOV1trong thanh ghi TIFR c set.

10. Thanh GhiExtended Timer/Counter Interrupt Mask RegisterETIMSK(Interrupt for Timer/counter 3)

Bit 7:6 Reserved Bits Bit 5 TICIE3: Timer/Counter3, Input Capture Interrupt Enable Bit 4 OCIE3A: Timer/Counter3, Output Compare A Match Interrupt Enable Bit 3 OCIE3B: Timer/Counter3, Output Compare B Match Interrupt Enable Bit 2 TOIE3: Timer/Counter3, Overflow Interrupt Enable Bit 1 OCIE3C: Timer/Counter3, Output Compare C Match Interrupt Enable Bit 0 OCIE1C: Timer/Counter1, Output Compare C Match Interrupt Enable

Thanh ghi ETIMSK lin quan n c hai b nh thi 1 v 3. Bit 7:6 Reserved Bits: D tr ,phi ghi cc bit ny thnh 0 khi ghi vo thanh

ghi ETIMSK Bit 5 TICIE3: Timer/Counter3, Input Capture Interrupt Enable:Khi bit ny

c set thnh 1 v ngt ton cc (global interrupt) c cho php th ngt bt mu ng


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Bit 5 ICF1: Timer/Counter1, Input Capture Flag: C ny c set khi xy ras kin bt mu ng vo (Input Capture) ca chn ICP1. Khi thanh ghi ICR1 (InputCapture Register) c thit lp bi cc bit WGMn3:0 s dng nh mt gi tr TOP thc ICF1 s c set khi b m t ti gi tr TOP.C ICF1 s t ng xa khi ngt tng

ng c thc thi,hoc c th xa hay setbng cch ghi mt gi tr logic vo v tr ca n. Bit 4 OCF1A: Timer/Counter1, Output Compare A Match Flag: C nyc set ngay sau khi gi tr b m (TCNT1) bng vi gi tr thanh ghi OCR1A (OutputCompare Register A). Ch l mt so snh cng bc (FOC1A) s khng set c ny. COCF1A s t ng xa khi ngt tng ng c thc thi,hoc c th xa hay set bngcch ghi mt gi tr logic vo v tr ca n.

Bit 3 OCF1B: Timer/Counter1, Output Compare B Match Flag: C nyc set ngay sau khi gi tr b m (TCNT1) bng vi gi tr thanh ghi OCR1B (OutputCompare Register B). Ch l mt so snh cng bc (FOC1B) s khng set c ny.COCF1B s t ng xa khi ngt tng ng c thc thi,hoc c th xa hay set bng

cch ghi mt gi tr logic vo v tr ca n. Bit 2 TOV1: Timer/Counter1, Overflow Flag: Vic thit lp c ny ph thucvo thit lp ca ccbit WGMn3:0, trong ch bnh thng v CTC c TOV1 c setkhi b nh thi trn.Xem libng 61 v mc Cc ch thc thi bit cc trnghp khc.

12. Thanh Ghi Extended Timer/Counter Interrupt Flag RegisterETIFR

Bit 7:6 Reserved Bits Bit 5 ICF3: Timer/Counter3, Input Capture Flag Bit 4 OCF3A: Timer/Counter3, Output Compare A Match Flag Bit 3 OCF3B: Timer/Counter3, Output Compare B Match Flag Bit 2 TOV3: Timer/Counter3, Overflow Flag Bit 1 OCF3C: Timer/Counter3, Output Compare C Match Flag Bit 0 OCF1C: Timer/Counter1, Output Compare C Match Flag

Bit 7:6 Reserved Bits: D tr, phi ghi0 khi ghi vo thanh ghi ETIFR. Bit 5 ICF3: Timer/Counter3, Input Capture Flag:C ny c set khi xy ra

s kin bt ng vo (Input Capture) ca chn ICP3.Khi thanh ghi ICR3 (Input CaptureRegister) c thit lp bi cc bit WGMn3:0 s dng nh mt gi tr TOP th c ICF3


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s c set khi b m t tigi tr TOP.C ICF3 s t ng xa khi ngt tng ngc thc thi,hoc c th xa hay setbng cch ghi mt gi tr logic vo v tr ca n.

Bit 4 OCF3A: Timer/Counter3, Output Compare A Match Flag: : C nyc set ngay sau khi gi tr b m (TCNT3) bng vi gi tr thanh ghi OCR3A (Output

Compare Register A). Ch l mt so snh cng bc (FOC3A) s khng set c ny. COCF3A s t ng xa khi ngt tng ng c thc thi, hoc c th xa hay set bngcch ghi mt gi tr logic vo v tr ca n.

Bit 3 OCF3B: Timer/Counter3, Output Compare B Match Flag: C nyc set ngay sau khi gi tr b m (TCNT3) bng vi gi tr thanh ghi OCR3B (OutputCompare Register B).Ch l mt so snh cng bc (FOC3B) s khng set c ny.COCF3B s t ng xa khi ngt tng ng c thc thi,hoc c th xa hay set bngcch ghi mt gi tr logic vo v tr ca n.

Bit 2 TOV3: Timer/Counter3, Overflow Flag:Vic thit lp c ny ph thucvo thit lp ca ccbit WGMn3:0, trong ch bnh thng v CTC c TOV3 c set

khi b nh thi trn.Xem libng 52 v mc Cc ch thc thi bit cc trnghp khc. Bit 1 OCF3C: Timer/Counter3, Output Compare C Match Flag: C ny

c set ngay sau khi gi tr b m (TCNT3) bng vi gi tr thanh ghi OCR3C (OutputCompare Register C). Ch l mt so snh cng bc (FOC3C) s khng set c ny.COCF3C s t ng xa khi ngt tng ng c thc thi,hoc c th xa hay set bngcch ghi mt gi tr logic vo v tr ca n.

Bit 0 OCF1C: Timer/Counter1, Output Compare C Match Flag: C nyc set ngay sau khi gi tr b m (TCNT1) bng vi gi tr thanh ghi OCR1C (OutputCompare Register C). Ch l mt so snh cng bc (FOC1C) s khng set c ny.COCF1C s t ng xa khi ngt tng ng c thc thi,hoc c th xa hay set bngcch ghi mt gi tr logic vo v tr ca n.

13. Thanh Ghi Special Function IO RegisterSFIOR

Bit 7 TSM: Timer/Counter Synchronization Mode Bit 0 PSR321: Prescaler Reset Timer/Counter3, Timer/Counter2, and

Timer/Counter1


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Bit 7 TSM: Timer/Counter Synchronization Mode: Ghi bit ny thnh 1 skch hot ch ng b b nh thi. Trong ch ny gi tr ghi vo hai bit PSR0 vPSR321 c gi, v th n gicho tn hiu resetcab chia trc (prescaler (8) ) tngng c xc nhn( do b chia trc prescaler vn trng thi Reset ). iu ny

chcchn l cc b Timer/couter tng ng c tm dng c th c cu hnh vigi tr nhnhau m khng lm hng cc cu hnh sn c khc. Khi TMS l 0 th cc bitPSR0 v PSR321 c xa bi phn cng v cc b nh thi (1,2,3) bt u m ngthi.( Xem thm mc : Ch ng B B nh Thi).

Bit 0 PSR321: Prescaler Reset Timer/Counter3, Timer/Counter2, andTimer/Counter1:Khi bit ny l 1 th b chia trc (prescaler) ca ba b nh thi 1,2,3c reset.Bit PSR321 c xa bi phn cng ngoi tr trng hp bit TSM c set.Ch l ba b nh thi 1,2, 3 cng chia s mt b chia trc (prescaler) nn vic reset bchia trc (prescaler) s tc ngln c ba b nh thi ny.

II. B NH THI 3

B nh thi 3 ging b nh thi 1 nn y ch trnh by cc thanh ghi lin quanti b nh thi 3, chc nng ca tng thanh ghi c th xem cc thanh ghi tng ng vin b nh thi 1.

1. Thanh ghi TCCR3A (Timer/Counter3 Control Register A)

Bit 7:6COM3A1:0: Compare Output Mode for Channel A Bit 5:4COM3B1:0: Compare Output Mode for Channel B Bit 3:2COM3C1:0: Compare Output Mode for Channel C Bit 1:0 WGMn1:0: Waveform Generation Mode

2. Thanh ghi TCCR3B (Timer/Counter3 Control Register B)

l khi Input Capture Unit ca b nh thi 3 c khc cht t so vi ca b nh thi1. Xem chi tit v khi Input Capture Unit phn m t KhiInput Capture Unit.


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Bit 7 ICNC3: Input Capture Noise Canceler Bit 6 ICES3: Input Capture Edge Select Bit 5 Reserved Bit Bit 4:3 WGM3 3:2: Waveform Generation Mode Bit 2:0 CS3 2:0: Clock Select

3. Thanh ghi TCCR3C (Timer/Counter3 Control Register C)

Bit 7FOC3A: Force Output Compare for Channel A Bit 6FOC3B: Force Output Compare for Channel B Bit 5FOC3C: Force Output Compare for Channel C Bit 4:0Reserved Bits

4.Thanh Ghi Timer/Counter1TCNT3H and TCNT3L

5. Thanh Ghi Output Compare Register 3 AOCR3AH and OCR3AL


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6. Thanh Ghi Output Compare Register 3 BOCR3BH and OCR3BL

7. Thanh Ghi Output Compare Register 3COCR3CH and OCR3CL

8. Thanh Ghi Input Capture Register 3ICR3H and ICR3L

9.Thanh GhiExtended Timer/Counter Interrupt Mask RegisterETIMSK(Interrupt for Timer/counter 3)

l b nh thi 1 c s dng thanh ghi TIMSK v ETIMSK , cn b nhthi 3ch s dng thanh ghi ETIMSK.

10. Thanh Ghi Extended Timer/Counter Interrupt Flag RegisterETIFR

l b nh thi 1 s dng c 2 thanh ghi TIFR v ETIFR , cn b nh thi 3ch s dng thanh ghi TIFR.


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11.Thanh Ghi Special Function IO RegisterSFIOR

12. Ng Ra Khi Compare Match Output Unit

Hnh 3.2.Ng ra khi Compare Match Output Unit


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Nhn hnh 3.2 trn ta thy Pin OCnX (chn hn pin 15 ca IC tng ng viOC1A), l ng ra ca khi Compare Match Output Unit, c thc ni vi 3 thanhghil OCnX, PortX v DDRX . Thanh ghi no c ni vi OCn l ph thuc vo cc bitCOMn1:0 (tc ty theo ch hot ng ca b nh thi) , gi s ta thit lp cc bit

COMn1:0 cho thanh ghi OCn c ni vi PIN OCn, th hot ng ca PIN OCn (tcdng sng ng ra OCn ) li ph thuc vo thit lp ca cc bit WGMn3:0, cc bitWGMn3:0 s qui nh dng sng ng rati OCnnh th no(xem bng 61). Ngc li,nu ta thit lp b nh thi hot ng ch bnh thng (tc khng s dng chc nngso snh khp th chn OCn tr thnh chn vo ra s thng thng . Ng ra khiCompare Match Output Unit cab nh thi 1cng ging nh b nh thi 3.


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III. B NH THI 0S khi b nh thi 0

B nh thi 0 l b nh thi 8 bit, b nh thi 0 lin quan ti 7 thanh ghivinhiu ch thc thi khc nhau.

CC NH NGHA:

Cc nh ngha sau s c s dng cho b nh thi 0 v 2:BOTTOM B m t ti gi tr BOTTOM khi n c gi tr 00h .MAX B m t ti gi tr MAX khi n bng FFh.TOP B m t gi tr TOP khi n bng vi gi tr cao nht trong chui m,

gi tr cao nht trong chui m khng nht thit l FFh m c th l bt kh gi tr no

c qui nh trong thanh ghi OCRn (n=0,2), ty theo ch thc thi.B nh thi 0 c vi c im chnh nh: B m n knh, xa b nh thi khi

c s kin so snh khp(compare match) v t np li, c th m t b dao ng 32KHz bn ngoi, ch PWM hiu chnh pha,Di y l m t chc nng ca cc thanhghi lin quan ti b nh thi 0.


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1. Thanh Ghi Timer/Counter Control RegisterTCCR0

Bit 7 FOC0: Force Output Compare ( 6 )

Bit 6, 3 WGM01:0: Waveform Generation Mode Bit 5:4 COM01:0: Compare Match Output Mode Bit 2:0 CS02:0: Clock Select Bit 7 FOC0: Force Output Compare: Bit ny ch hot ng khi cc bit WGM

ch nh ch non-PWM ( chn hn ch CTC,). Khi ch PWM nn ghi bit nythnh 0. ch non-PWM, khi bit FOC0 c ghi thnh 1 lp tc mt s kin so snhkhpcng bc( Force compare match ) xy ra b to sng, tc l s kin so snh

khpb bt buc xy ra mt d gi tr b nh thi khng bng vi gi tr ghi sn tron gthanh ghi OCR0. Lc ny ng ra OC0 s thay i ty theo thit lp ca nhng bitCOM01:0 tng ng vi n. Bit FOC0 s t ng xa bi phn cng sau 1 chu k clock.Bit ny khng th c.

Bit 6, 3 WGM01:0: Waveform Generation Mode: Nhng bit ny iu khincc ch thc thi ca bm, theo dng sng tng ngc to ra t b to sng.Cc ch thc thi c h tr l : Normal, CTC, PWM. C th xem bng 52.

Bng 52. La chn cc ch thc thi ca b nh thi0.

(1): Tn cc bit CTC0 v PWM0 khng c s dng na v c thay th bngcc tn khc l WGM01 v WGM00. Khi lp trnh nn ch iu ny.

Bit 5:4 COM01:0: Compare Match Output Mode : Hai bit ny iu khinhnh vi ca chn OC0. Nu mt trong hai bit ny c set thnh 1 th ng ra OC0 c utin hn chc nngI/O thng thng. Ch l cc bit tng ng ca OC0 trong thanh ghiDDR phi c set cho php ng ra. Khibit OC0 c kt ni vi chn ng ra OC0 th


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tc ng cacc bit COM01:0 i vi hnh vi ca chn OC0cn ph thuc vo cc thitlp ca cc bit WGM01:0. Chi tit xem bng 53, 54, 55.

Chnhn, khi ta set bit { WGM00, WGM01, COM00, COM01} = { 0, 0, 1, 0 } thb nh thi 0 s hot ng ch Normal v ch nyhnh vi ca chn OC0 l:

OC0 s thay i mc logic mi khi c s kin So snh khp( Compare match ). l ch Normal, vi thit lp cc bitWGM00, WGM01, COM00, COM01nh trn,gi trthanh ghi OCR0 c cp nht ngay tc thi, khc vi ch PWM gi tr thanh ghiOCR0 ch c cp nht khib nh thi m ti gi tr TOP (gi nh trong on chngtrnh ng dng c s thay i gi tr thanh ghi OCR0).

on chng trnh sau s thit lp b nh thi hot ng ch CTCv set chnOC0 ln 1 mi khi c s kin so snh.

ldi r17,0xFF ; configured as outputout DDRB,r17

ldi r16,0xF0out OCR0,r16 ; match value

ldi r16,0x39out TCCR0,r16 ; CTC mode

Bng 53. iu khin hnh vi ca chn OC0 bng cc bit COM00:1 trong ch non-PWM


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Bng 55. iu khin hnh vi ca chn OC0 bng cc bit COM00:1 trong ch PWM hiu chnh pha

Bng 54. iu khin hnh vi ca chn OC0 bng cc bit COM00:1 trong ch

PWMnhanh

Ch (1): C trng hp t bit l khi thanh ghi OCR0 c gi tr l TOP v bitCOM01 c set , trong trng hp ny vic so snh khp(Compare match) b b qua,nhng vic set hayxa OC0 TOP vn c thc hin.

Bit 2:0 CS02:0: Clock Select: y l 3 bit dng la chn xung clock cho bnh thi. Xem Bng 56. dng b nh thi ta chn { CS00, CS01, CS02 } = {0, 0, 0 }.


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Bng 56. La chn tc xung clock cho b nh thi 0

2.Thanh Ghi Timer/Counter RegisterTCNT0

y l thanh ghi m 8 bit ca b nh thi 0 .Gi tr thanh ghi ny tng hoc gim1 n vsau mi chu k clock. Khng nn ghi vo thanh ghi ny khi n ang m.

3. Thanh Ghi Output Compare RegisterOCR0

OCR0 l thanh ghi 8 bit, gi tr ca n c lin tc so snh vi gi tr ca thanh ghiTCNT0. Khi hai gi tr ca hai thanh ghi ny bng nhau th xy ra mt s kin so snhkhp (compare match). S kin so snh khps to ra mt ngt, nu ngt c cho php.Hay to ra mt dng sng chn ng ra OC0, ty theo ch thc thi ca b nh thi.


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4. Thanh Ghi Timer/Counter Interrupt Mask RegisterTIMSK

Bit 1 OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable Bit 0 TOIE0: Timer/Counter0 Overflow Interrupt Enable Bit 1 OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable:

Khi bit OCIE0 ghi l 1 v bit I ca thanh ghi trng thi SREG c setthnh 1 th ngt skin so snh khp (compare match interrupt ) c cho php. Khi mt ngt s cthc thi khi xy ra mt s kin so snhkhp.

Bit 0 TOIE0: Timer/Counter0 Overflow Interrupt Enable: Khi bit ny c

ghi l 1 v ngt ton cc c cho php th ngt trn b nh thi (Timer/Counter0Overflow interrupt) c cho php. Khi mt ngt tng ng s c thc thi khi bnh thi trn.

5. Thanh Ghi Timer/Counter Interrupt Flag RegisterTIFR

Bit 1 OCF0: Output Compare Flag 0 Bit 0 TOV0: Timer/Counter0 Overflow Flag

Bit 1 OCF0: Output Compare Flag 0: Bit ny s c set ln 1 khi xy ra sosnh khp (compare match) gia b nh thi (tc thanh ghi TCCN0) vi thanh ghiOCR0. C OCF0s t ng xa khi ngt tng ng c thc thi.Ngoi ra ta cng c thxa c OCF0 bngcch ghi mt gi tr logic vo n. Khi bit I trong thanh ghi SREG, bitOCIE0 (Timer/Counter0 Compare Match Interrupt Enable) v bit OCF0 c set ln 1 thngt so snhkhp (Compare Match Interrupt) s c thc thi.

Bit 0 TOV0: Timer/Counter0 Overflow Flag: Bit TOV0 c set thnh 1 khib nh thi trnv n c xa khi ngt tng ng c thc thi. Ngoi ra cng c thxa bng cch ghimt gi tr logic vo v tr ca n . Khi bit I trong thanh ghi SREG, bitTOIE0 (Timer/Counter0 Overflow interrupt) v bit TOV0 c set ln 1 th ngt trn bnh thi 0 (Timer/Counter0 Overflow Interrupt ) s c thc thi. Trong ch PWM cTOV0 cSet khi b nh thi 0 i hng m ti gi tr 00h.


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6. Thanh Ghi Special Function IO RegisterSFIOR

Bit 7 TSM: Timer/Counter Synchronization Mode Bit 1 PSR0: Prescaler Reset Timer/Counter0

Bit 7 TSM: Timer/Counter Synchronization Mode: Ghi bit ny thnh 1 skch hot ch ng b b nh thi (Timer/Counter Synchronization). Trong ch ny,mt gi tr c ghivo cc bit PSR0 v PSR321 s c gi li, v th n gicho tnhiu resetca b chia trc (prescaler) tng ng c xc nhn ( do b chia trc(prescaler) vn trng thi Reset ). iu ny l chc chn l cc b nh thi tng ngs c tm ngh v c th c cu hnh vi cc gi tr nh nhau m khng lm nhhng n mt trong nhng cu hnh nng cao khcca chng. Khi bit ny c ghi thnh0 th cc b nh thi s bt u m ng thi.

Bit 1 PSR0: Prescaler Reset Timer/Counter0: Khi bit ny l 1 th b chiatrc ca b nh thi 0 (Timer/couter 0 prescaler) s c t li. Bit ny thng cxa tc thi bi phn cng.Nu bit ny c ghikhi b nh thi 0 ang thc thi ch khng ng b th n vn gi nguyn gi tr ca ncho n khi b chia trc c t li.Bit ny s khng c xa bi phn cng nu nh bit TSM c set thnh 1.

7. Thanh Ghi Asynchronous Status RegisterASSR

Bit 3 AS0: Asynchronous Timer/Counter0 Bit 2 TCN0UB: Timer/Counter0 Update Busy Bit 1 OCR0UB: Output Compare Register0 Update Busy

Bit 0 TCR0UB: Timer/Counter Control Register0 Update Busy

Bit 3 AS0: Asynchronous Timer/Counter0: Khi bit AS0 l 0 th b nh thic m t ngun xung clock I/O, tc ClkI/O. Khi AS0 c ghi thnh 1 b nh thi


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c m t xung thch anh chn TOSC1. Khi gi tr ca AS0 b thay i th ni dngca cc thanh ghi TCNT0, OCR0 v TCCR0 c th b hng.

Bit 2 TCN0UB: Timer/Counter0 Update Busy: Khi b nh thi0 thc thi qutrnh khng ng b v thanh ghi TCNT0 ang c ghi th bit TCN0UB s set ln 1. Khi

thanh ghi TCNT0 va c cp nht t thanh ghi lu tr tm th bit ny b xa bi phncng. Mc logic 0 trong trng hp ny l ch ra rng thanh ghi TCNT0 sn sng cp nht mt gi tr mi.

Bit 1 OCR0UB: Output Compare Register0 Update Busy: Khi b nh thi 0thc thi qu trnh khng ng b v thanh ghi OCR0 ang c ghith bit OCR0UB s setln 1. Khi thanh ghi OCR0 va c cp nht t thanh ghi lu tr tm th bit ny b xa

bi phn cng .Mc logic 0 trong trng hp ny l ch ra rng thanh ghi OCR0 snsng cp nht mt gi tr mi.

Bit 0 TCR0UB: Timer/Counter Control Register0 Update Busy: Khi b nhthi 0 thc thi qu trnh khng ng b v thanh ghi TCCR0 ang c ghi th bit

TCR0UB s set ln 1. Khi thanh ghi TCCR0 va c cp nht t thanh ghi lu tr tm t hbit ny b xa bi phn cng. Mc logic 0 trong trng hp ny l ch ra rng thanh ghiTCCR0 sn sng cp nht mt gi tr mi.

Nu ghi vo mt trong ba thanh ghi ca b nh thi 0 (TCNT0, OCR0, TCCR0)trong lc cbobn cp nht (update busy flag) ca chng c set, th gi tr cp nht cth b hng v s to ra mt ngt khng bit trc.


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IV.B NH THI 2

S khi b nh thi 2

B nh thi 2 l b nh thi 8 bit, b nh thi 2 lin quan ti 5 thanh ghi vinhiu ch thc thi khc nhau.Cc thuc tnh chnh ca b nh gm: B m n knh,xa b nh thi khi c s kin so snh khp v t ng np li, PWM hiu chnh pha,m s kin bn ngoi

Cc Thanh Ghi B nh Thi 2.

1. Thanh ghi Timer/Counter Control RegisterTCCR2

Bit 7 FOC2: Force Output Compare Bit 6, 3 WGM21:0: Waveform Generation Mode


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Bit 5:4 COM21:0: Compare Match Output Mode Bit 2:0 CS22:0: Clock Select

Bit 7 FOC2: Force Output Compare : Bit FOC2 ch hot ng khi bit WGM20 chnh ch Non-PWM, trong ch PWM nn ghi bit ny thnh 0. ch non-PWM, khibit FOC0 c ghi thnh 1 lp tc mt so snh khp(compare match ) xy ra b tosng, ng ra OC2 thay i ty theo thit lp ca nhng bit COM21:0 tng ng vi n.Bit ny khng th c, khi c ta lun nhn gi tr 0. Bit ny hot ng ging nh bitFOC0 ca b nh thi 0.

Bit 6, 3 WGM21:0: Waveform Generation Mode:Nhng bit ny iu khincc ch thc thi ca bm, theo dng sng tng ngc to ra t b to sng.Cc ch thc thi c h tr l : Normal, CTC, PWM. Xem bng 64.

Bng 64. La chn cc ch thc thi ca b nh thi2Ch : Tn cc bit CTC2 v PWM2 khng c s dng na v c thay th bngcc tn khc l WGM21 v WGM20.

Bit 5:4 COM21:0: Compare Match Output Mode: Hai bit ny iu khin hotng ca chn OC2. Nu mt trong hai bit ny c set thnh 1 th ng ra OC 2 c utin hn chc nngI/O thng thng .Ch l cc bit tng ng ca OC2 trong thanh ghiDDR phi c set cho php ng ra. Khi OC2 c kt ni vi chn ng ra OC2 th vaitr cacc bit COM21:0 cn ph thuc vo cc thit lp ca cc bit WGM21:0. Chi titxem bng 65, 66, 67. Cc bit ny hot ng ging vi cc bit COM01:0 ca bnh thi 0.Xem li b nh thi 0.


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Bng 65. iu khin hnh vi ca chn OC2 bng cc bit COM20:1 trong ch non-PWM

Bng 66. iu khin hnh vi ca chn OC2 bng cc bit COM20:1 trong ch PWM nhanh

Bng 67. iu khin hnh vi ca chn OC2 bng cc bit COM20:1 trong ch PWM hiu chnh pha

Ch : C trng hp t bit l khi thanh ghi OCR2 c gi tr l TOP v bitCOM21 c set , trong trng hp ny s kin so snh khp (Compare match) b bqua, nhng vic set hayxa OC2 TOP vn c thc hin.

Bit 2:0 CS22:0: Clock Select: Dng la chn ngun xung clock cho b nhthi 2. Xem chi tit bng 68.


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Bng 68. La chn tc xung clock cho b nh thi 0

: B nh thi 2 c thc m t ngun clock bn ngoi thng qua chn T2. Khichuyn sang ngun clock ngoi, b m vn m bnh thng ngay c khi chn T2 ccu hnh l ng ra.

2. Thanh ghi Timer/Counter RegisterTCNT2

y l thanh ghi m 8 bit ca b nh thi 2. Gi tr thanh ghi ny tng hoc gim1 n vsau mi chu kh clock. Thanh ghi TCNT2 c truy xut trc tip khi c hay ghi( iu ny khc vi b nh thi 1 v 3 l khi truy xut cc thanh ghi TCNT1 hay TCNT3cn phi thng qua thanh ghi tm trung gian 8 bit ). Khng nn chnh sa thanh ghi TCNT2khi b nh thi ang chy.

3. Thanh ghiOutput Compare RegisterOCR2


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Thanh ghi OCR2 l thanh ghi 8 bit, gi tr ca thanh ghi OCR2 s c lin tc sosnh vi gi tr ca b m, tc thanh ghi TCNT2. Khi gi tr ca hai thanh ghi ny bngnhau s to ra s kin so snh khp ( Compare match). Mt ngt so snh khp (compare match interrupt ) c th c to ranu ngt c cho php, hay mt dngsng

s c to ra chn OC2.Thanh ghi ny hot ng tng t nh thanh ghi OCR0 bnh thi 0.

4.Thanh ghiTimer/Counter Interrupt Mask RegisterTIMSK

Bit 7 OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable Bit 6 TOIE2: Timer/Counter2 Overflow Interrupt Enable

Bit 7 OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable:Khibit OCIE2 c set thnh 1 v bit I trong thanh ghi trng thi c set thnh 1 th ngtso snhkhp (compare match interrupt )ca b nh thi 2c cho php. Khi mtngttng ng s c thc thi khi xy ra mts kinso snhkhp b nh thi 2.Chn hn, xy ra mt so snhkhp (compare match ) b nh thi 2 ta c th set bitOCF2 trong thanh ghi TIFR, hoc l ch cho n khi no gi tr ca hai thanh ghi TCNT2

v OCR2 bng nhau th mt so snhkhp (compare match ) s xy ra. Bit 6 TOIE2: Timer/Counter2 Overflow Interrupt Enable: Khi bit ny cghi l 1 v ngt ton cc c cho php(bit I trong thanh ghi trng thi SREG c setthnh 1) th ngt trn bnh thi 2 (Timer/Counter2 Overflow interrupt) c cho php.Khi mt ngt tng ng s c thc thi khi b nh thi 2 trn. Chn hn, ta set bitTOV2 trong thanh ghi TIFR thnh 1 hoc l ch cho b nh thi 2 b trn khi vt qugi tr TOP ( hay MAX ).

5. Thanh ghiTimer/Counter Interrupt Flag RegisterTIFR


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Bit 7 OCF2: Output Compare Flag 2 Bit 6 TOV2: Timer/Counter2 Overflow Flag

Bit 7 OCF2: Output Compare Flag 2: Bit ny s c set ln 1 khi xy ra skin so snh khp(compare match) gia b nh thi 2 (tc thanh ghi TCCN2) vi thanhghi OCR2. C OCF2 s t ng xa khi ngt tng ng c thc thi.Ngoi ra ta cng cth xa c OCF2bngcch ghi mt gi tr logic vo n. Khi bit I trong thanh ghi SREG,bit OCIE2 (Timer/Counter2 Compare Match Interrupt Enable) v bit OCF2 c set ln 1th ngt s kin so snh khp (Compare Match Interrupt) ca b nh thi 2 s c thcthi.

Bit 6 TOV2: Timer/Counter2 Overflow Flag: Bit TOV2 c set thnh 1 khibnh thi trnv n c xa khi ngt tng ng c thc thi. Ngoi ra cng c thxa bng cch ghimt gi tr logic vo v tr ca n. Khi bit I trong thanh ghi SREG, bit

TOIE2 (Timer/Counter2 Overflow interrupt) v bit TOV2 c set ln1 th ngt trn bnh thi 2(Timer/Counter2 Overflow Interrupt ) s c thc thi. Trong ch PWM cTOV2 cset khi b nh thi 2 i hng m ti gi tr 00h.


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ChngIVCU TRC NGT CAATmega128

I. KHI NIM V NGT

Ngt l mt s kin bn trong hay bn ngoi lm ngt b vi iu khin bo chon bit rng thit b cn dch v ca n.

Mt b vi iu khin c th phc v mt vi thit b, c hai cch thc hin iuny l s dng cc ngt (interrupt) v thm d (polling). Trong phng php s dngcc ngt th mi khi c mt thit b bt k cn n dch v ca n th n bo cho b vi iukhin bng cch gi mt tn hiu ngt. Khi nhn c tn hiu ngt th b vi iu khinngt tt c nhng g n ang thc hin chuyn sang phc v thit b. Chng trnh icng vi ngt c gi l trnh dch v ngt ISR (Interrupt Service Routine) hay cn gi ltrnh qun l ngt (Interrupt handler). Cn trong phng php thm d th b vi iu khinhinth lin tc tnh trng ca mt thit b cho v iu kin tho mn th n phc vthit b. Sau n chuyn sang hin th tnh trng ca thit b k tip cho n khi tt c uc phc v.Mc d phng php thm d c

thth hin th tnh trng ca mt vi thit b v phc vmi thit b khi cc iu kin nht nh c tho mn nhng n khng tn dng ht cngdng ca b vi iu khin. im mnh ca phng php ngt l b vi iu khin c th

phc v c rt nhiu thit b (tt nhin l khng ti cng mt thi im). Mi thit b cth nhn c s ch ca b vi iu khin da trn mc u tin c gn cho n.ivi phng php thm d th khng th gn mc u tin cho cc thit b v n

kim tra tt

c mi thit b theo kiu quay vng . Quan trng hn l trong phng php ngt th b viiu khin cng cn c th che hoc lm l mt yu cu dch v ca thit b. iu ny limt ln na khng th thc hin c trong phng php thm d. L do quan trng nhtm phng php ngt c u chung nht l v phng php thm d lm hao ph thigian ca b vi iu khin bng cch hi d tng thit b k c khi chng khng cn ndch v.

II. TRNH PHC V NGT V BNG VECTOR NGT

i vi mi ngt th phi c mt trnh phc v ngt ISR (In terrupt Service Routine)hay trnh qun l ngt (Interrupt handler). Khi mt ngt c gi th b vi iu khin phcv ngt. Khi mt ngt c gi th b vi iu khin chy trnh phc v ngt. i vi mingt th c mt v tr c nh trong b nh gi a ch ISR ca n. Nhm cc v tr nhc dnh ring gi cc a ch ca cc ISR c gi l bngvc t ngt.


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Khi kch hot mt ngt b vi iu khin i qua cc bc sau: Vi iu khin kt thc lnh ang thc hin v lu a ch ca lnh k tip (PC)

vo ngn xp. N nhy n mt v tr c nh trong b nh c gi l bng vc t ngt ni lu

gi a ch ca mt trnh phc v ngt. B vi iu khin nhn a ch ISR t bng vc t ngt v nhy ti . N bt uthc hin trnh phc v ngt cho n lnh cui cng ca ISR l RETI (tr v t ngt).

Khi thc hin lnh RETI b vi iu khin quay tr v ni n b ngt. Trc htn nhn a ch ca b m chng trnh PC t ngn xp bng cch ko hai byte trn nhca ngn xp vo PC. Sau bt u thc hin cc lnh t a ch .

III. BNG VECTOR NGT CA ATmega128.

Di y l bng vc t ngt ca ATmega128 , cng vi a ch ca n trong b

nh chng trnh ( bng 23).


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Bng 23. Bng Vector Ngt Ca ATmega128

IV. TH T U TIN NGT.

Khng nh vi iu khin h 8051, th t u tin ca cc ngt c th thay ic ( bng cch lp trnh ). Vi vi iu khin AVR th t u tin cc ngt l khng ththay i v theo qui tc: Mt vec t ngt c a ch thp hn trong b nh chng

trnh c mc u tin cao hn. Chn hn ngt ngoi 0 ( INT0 ) c mc u tin caohn ngt ngoi 1 ( INT1 ). cho php mt ngt ngi dng cncho php ngt ton cc (set bit I trong thanh

ghi SREG ) v cc bit iu khin ngt tng ng.Khi mt ngt xy ra v ang c phc v th bit I trong thanh ghi SREG b xa,

nh th khic mt ngt khc xy ra n s khng c phc v, do cho php cc ngt


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trong khi mt ISR ( interrupt service routine ) khc ang thc thi, th trong chng trnhISR phi c lnh SEI set li bit I trong SREG.

V. NGT TRONG NGT.

Khi AVR ang thc hin mt trnh phc v ngt thuc mt ngt no th li cmt ngt khc c kch hot. Trong nhng trng hp nh vy th mt ngt c mcutin cao hn c th ngt mt ngt c mc u tin thp hn. Lc ny ISR ca ngt c mcu tin cao hn s c thc thi(*). Khi thc hin xong ISR ca ngt c mc u tin caohn th n mi quay li phc v tip ISR ca ngt c mc u tin thp hn trc khi tr vchng trnh chnh. y gi l ngt trong ngt. ( hnh 4.1).

Hnh 4.1. Cc ngt lng nhau

Ch :- Gi nh lkhi mt ISR no ang thc thi th xy ra mt yu cu ngt t mt

ISR khc c mc u tin thp hn th ISR c mc u tin thp hn khng c phc v,nhng n s khng b b qua lun m trng thi ch. Ngha l ngay sau khi ISR cmc u tin cao hn thc thi xong th n lt ISR c mc u tin thp hns c

phc v.- (*) : iu ny ch xy ra khi trongcode caISR ca ngt c mc u tin thp

hn c lnh set bit I trong thanh ghi SREG ( l lnhSEI ).


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VI. CC NGT NGOI.

ATmega128 c 8 ngt ngoi t INT0 n INT7 ( y cha k ti ngt reset ).

Tm ngt ny tng ng vi 8 chn ca MCU l INT0 ,INT1, , INT7. l ngay ckhi cc chn INT0, INT1, , INT7 ca MCU c cu hnh nh l chn li ra, th cc ngtngoi vn c tc dng nu c cho php.

Cc ngt ngoi c th bt mu theo kiu cnh ln( Rising ), cnh xung ( Falling )hay mc thp ( Low level ). iu ny c qui nh trong hai thanh ghi EICRA v EICRB .Di y l m t chi tit 2 thanh ghi EICRA v EICRB v cc thanh ghi lin quan ti ccngt ngoi.

1. Thanh ghi External Interrupt Control Register AEICRA

Bits 7..0 ISC31, ISC30ISC00, ISC00: External Interrupt 3 - 0 Sense Control Bits

Tm bit ca thanh ghi EICRA s iu khin kiu bt mu cho 4 ngt INT3, INT2,INT1, INT0. Qui nh c th c th hin trong Bng 48.

ISCn1 ISCn0 Kiu bt mu

0 0 Mc thp s to yu cu ngt0 1 D tr1 0 Cnh xung ( Falling ) s to yu cu ngt1 1 Cnh ln ( Rising ) s to yu cu ngt

n = 3, 2, 1, 0

Bng 48 . iu khin kiu bt mu ngt

2. Thanh Ghi External Interrupt Control Register BEICRB


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Bits 7..0 ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 SenseControl Bits.

Tm bit ca thanh ghi EICRA s iu khin kiu bt mu cho 4 ngt INT7, INT6,INT5, INT4. . Qui nh c th c th hin trong Bng 50 .

ISCn1 ISCn0 Kiu bt mu

0 0 Mc thp s to yu cu ngt0 1 Bt c s thay i mc logic no chn

INTn s tao ra mt yu cu ngt1 0 Cnh xung ( Falling ) gia hai mu s to

yu cu ngt1 1 Cnh ln ( Rising )gia hai mus to yu

cu ngtn = 7,6, 5, 4

Bng 50 . iu khin kiu bt mu ngt

3. Thanh Ghi External Interrupt Mask RegisterEIMSK

Bits 7..0 INT7 INT0: External Interrupt Request 7 - 0 Enable : Khi chophp ngt ton cc ( set bit I trong thanh ghi SREG thnh 1 ) th cc ngt vn cha th thcthi, ngt c th thc thi ta cn phi cho php n, 8 bit trong thanh ghi EIMSK s quytnh 8 ngt ngoi tng ng ( t INT7 ...INT0 ) c c cho php hay khng. Khi mttrong s 8 bit( t INT7 ...INT0 ) c set thnh 1 v ngt ton cc c cho php th ngtngoi tng ng c cho php. Cn tn hiu ngt l mc hay cnh s do cc thanh ghi


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EICRA v EICRB ( nu trn ) qui nh. Kch hot bt c chn( Pin ) no trong 8 chncangt ngoi cng to ra yu cu ngt ngay c khi chn c thit lp thnh ng ra.

4. Thanh Ghi External Interrupt Flag RegisterEIFR

Bits 7..0 INTF7 - INTF0: External Interrupt Flags 70 : y l tm c ngttng ng vitm ngt ngoi INT7..INT0. Khi c tn hiu yu cu ngt ngoi th c ngttng ng s c set thnh 1, nu ngt tng ng c cho php th MCU s nhy ti

bng vc t ngt, c ngt s c xa khi chng trnh phc v ngt ( ISR ) c thc thi.Ngoi ra ta cng c set hay xa c ngt bng cch ghi trc tip mt gi tr logic vo n.

5. Thanh Ghi MCU Control RegisterMCUCR

Trong phn ny ta ch quan tm ti hai bit l: IVCE (Interrupt Vector Select ) v bitIVSEL (Interrupt Vector Change Enable ) ca thanh ghi MCUCR. Bit ny lin quan nvic thit lpv trbng vc t ngt.

Bit 1 IVSEL: Interrupt Vector Select: Khi bit ny l 0 v tr ca bng vc tngt c t phn u b nhchng trnh. Khi bit ny l 1 bng vc t ngt c dichuyn ti phn u ca vng nh Boot Loader.

Bit 0 IVCE: Interrupt Vector Change Enable: Bit ny phi c ghi thnh 1 cho php thay i bit IVSEL. Bit IVCE c xa sau 4 chu k my sau khi n c sethay bit IVSEL c ghi. Trong lc bit ICVE ang set cc ngt s b cm cho ti khi bit

IVSEL c ghi, nubit IVSEL khng c ghi th cc ngt vn b cm trong 4 cho kmy lin tip ( sau 4 chu k my th bit IVCE s t ng b xa nn cc ngt c cho phptr li ).


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ChngVCC BPHNNGOI VI KHC

Ngoi cc b phn ngoi vi c gii thiu cc chng trc nh : B nhthi, cc cng vo ra, EEPROM Vi iu khin ATmega128 c c nhiu b phn ngoivi khc, cc b ngoi vi ny rt tin li trong cc ng dng iu khin ( b PWM ), x l sliu ( b ADC, b so snh Analog), giao tip ( b USART, SPI, I2C ) Vic tch hp cc

b ngoi vi ny vo trong chip gip cho cc thit k tr nn thun tin hn, kch thc bomchcnggn gng hn...

I. B SO SNH TNG T

S n gin ca b so snh tng t ( Analog Comparator ) nh hnh 5.1. B sosnh c hai ng vo tng t l AIN0 v AIN1 v mt ng ra s ACO. Nguyn tc hotng ca b so snh tng t l : Khi ng vo AIN0 c in th cao hn ng voAIN1 th ng ra ACO s mc cao ( tng ng vi logic 1 ), ngc li kh i ng voAIN0 c in th thp hn ng vo AIN1 th ng ra ACO s mc thp ( tngng vi logic 0). Thng th trong hai ng vo, c mt ng vo c in th c gi cnh dng lm in th tham chiu ( VRef ), in th ng cn li c th thay i tham chiu vi ng vo VRef . Trng thi ca ng ra ACO ca b so snh c th cdng to ra mt ngt, kt ni ti b nh thi 1 s dng chc nng input captureca b nh thi ny ( xem m t sau ).

Hnh 5.1. S gin ltca b so snh tng t

Cn ch l c s khc bitv chi tit b so snh tng ti vi cc dngAVR khc nhau, chn hn b so snh tng t ca AT90S8535 hi khc vi b so snhtng t ATmega128, tuy nhin cu trc c bn th vn nh nhau. Sau y l m t cth v b so snh tng t ca ATmega128.

+

-

AIN0PBx

AIN1

PBy

Control

Logic

ACO

Interrupt Flag

To timer 1


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hnh 5.1 ta thy hai ng vo AIN0 v AIN1 tng ng vi hai chn PBx v PBy (x = 2, y = 3 i vi AT90S8535 ), ATmega128 ta c nhiu la chn ng vo hn , ccthanh ghi lin quan s gip ta tht lp cc la chn ny.

1. Thanh ghi Special Function IO RegisterSFIOR

Bit 3 ACME: Analog Comparator Multiplexer Enable

thanh ghi ny ta ch s dng bit Bit 3ACME , khi bit ny l 1 v chc nng

ADC khng cho php hot ng ( bit ADEN trong thanh ghi ADCSRA l 0 ) th ng vom ca b so snh tng t c th l 1 trong s 8 ng vo ADC ty theo thit lp ca ccbit MUX 2, MUX 1, MUX 0 ( xem bng 94), chn hn nu { ACME, ADEN, MUX 2,MUX 1, MUX 0 } = { 1, 0, 0, 0, 0 } th ng ADC0 ( tng ng vi chn s 61 ca vi iukhin )c chn lm ng vo m. Nu bit ACME l 0 th ng vo m ca b so snhtng t l AIN1 ( tng ng vi chn s 5 ca vi iu khin ).

Bng 94. La chn li vo m


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2. Thanh ghi Analog Comparator Control and Status RegisterACSR

Bit 7 ACD: Analog Comparator Disable Bit 6 ACBG: Analog Comparator Bandgap Select Bit 5 ACO: Analog Comparator Output Bit 4 ACI: Analog Comparator Interrupt Flag Bit 3 ACIE: Analog Comparator Interrupt Enable Bit 2ACIC: Analog Comparator Input Capture Enable Bits 1, 0 ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

Bit 7 ACD: Analog Comparator Disable: Khi bit ny l 1 s khng cho phpb so snh tng t hot ng. Khi bit ny l 0 b so snh tng t c php hot ng.Ta c th thay i bit ny bt c lc no cho php hay khng cho php b so snh tngt hot ng. Nhng cn ch l bt c s thay i no ca bit ACD cngc thto ramt ngt (ngt ca b so snh tng t ), do nu khng cn thit ta nn cm ngt ca

b so snh tng t bng cch xa bit ACIE ca thanh ghi ACSR. Bit 6ACBG: Analog Comparator Bandgap Select: Khi bit ny l 1 ng vo

dng s c gi mc in th c nh khong 1,23 V ( 250C v Vcc= 5 V ) v cdng lm in th tham chiu, gi l in th tham chiu ni ( Internal voltage reference ) .

Nh vy, trong trng hp ny ng vo m s thay i gi tr v tham chiu ti gi tr

1,23 V. Ch l khi ta s dng in th tham chiu ni 1,23 V nh nu trn th ta cnthit lp bit ACBG thnh 1 trc khi cho php b so snh tng t hot ng, bi v khiin th tham chiu ni c cho php n cn mt khong thi gian khi ng l 40 s c th n nh in th 1,23V. Khi bit ny l 0 chn AIN0 ( tng ng vi chn s 4 cavi iu khin )tr thnh ng vo dng.

Bit 5 ACO: Analog Comparator Output: Bit ny chnh l trng thi ng raca b so snh, c bit ny ta s bit c trng thi hin thi ca ng vo. Khi tng quanso snh hai ng vo thay i, cn t 1 ti 2 chu k my phn nh kt qu ny ng raACO.

Bit 4 ACI: Analog Comparator Interrupt Flag: y l bit c ngt ca b so

snh tng t, khi xy ra ngt b so snh tng t bit ny s c set ln 1 bi phncng, trnh phc v ngt c thc thi nu ngt c cho php ( bng cch set bit ACIEtrong ghi ACSR v bit I trong thanh ghi SREG ). Vc t ngt ca b so snh tng t ca ch l $002E. Bit ACI s c t ng xa bi phn cng khi trnh phc v ngt cthc thi. Ch : Bit ACI s t ng xa khi c bt c s thay i no ca thanh ghiACSR. Chn hn khi ta ghi vo bit ny gi tr logic 1 th sau khi thc hin xong lnh


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ghi ta vn nhn c gi tr logic 0 bit ny . Do ta khng th no set c bit nybng phn mm.

Bit 3 ACIE: Analog Comparator Interrupt Enable :y l bit cho php ngtca b so snh tng t.Khi bit ny l 1 th ngt b so snh tng t c cho php.

Ngc li, khi bit ny l 0 th ngt b so snh tng t b cm. Bit 2 ACIC: Analog Comparator Input Capture Enable: bit ny lin quan titnh nng input capture ca b nh thi 1 ( xem li b nh thi 1 ). Khi bit ny l 1 ng raca b so snh c ni trc tip ti li vo ca khiinput capture ca b nh thi 1, nhcch ny ta c th tn dng tnh nng kh nhiu ng vo input capture ca b nh thi 1,trong cch thit lp ny ngt input capture vn c th hot ng nu c cho php ( bngcch cho php ngt ton cc v set bit TICIE1 trong thanh ghi TIMSK ln 1 ). Khi bit nyl 0 ng ra ca b so snh tng t khng c kt ni vi ng vo ca khi inputcapture ca b nh thi 1.

Bits 1, 0 ACIS1, ACIS0: Analog Comparator Interrupt Mode Select: Hai bit

ny qui nh cch thc to ra ngt khi c s thay i trng thi ng ra ACO. Chn hn,khi ta thit lp { ACIS1, ACIS0 } = { 0, 0 } th khi c s thay i mc ( bao gm mc caoxung mc thp hoc mc thp ln mc cao ) ng ra ACO s to ra ngt. Cc thit lpkhc c m t bng 93.

ACIS1 ACIS0 M t

0 0 Thay i mc to ra ngt

0 1 Khng s dng ( d tr )

1 0 Cnh xung ng ra to ra ngt

1 1 Cnh ln ng ra to ra ngt

Bng 93. Cc cch thc to ra ngt b so snh tng t

Ch : Khi ta thay i mt trong hai (hoc c hai ) bit ACIS1, ACIS0 c thto rangt ca b so snh tng t nu ngt c cho php. Do , nu khng cn thit ta nncm ngt ca b so snh tng ttrc khi thay i hai bit ny.

Hnh 107m t cu trc ca b so snh tng t ca ATmega128, ta c th phn

tch hot ng ca b so snh tng t thng qua s ny. u tin l tn hiu ACBG (nt s 1 ), khi ACBG l 1 chn AIN0 b cm, in th tham chiu ni ( nt s 9 ) i quacng truyn hai chiu ti ng vo dng. Ngc li khi ACBG l 0 in th tham chiu ni

b cm.Xt tn hiu ACME v ADEN ( nt s 2 ) hai tn hiu ny iu khin 2 cng truynni vi n cho php ng vo m l AIN1 hay cc chn ADC ( nt s 10 ). Tn hiu ACD


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( nt s 3 ) l 1 s cp ngun cho b so snh tng t hot ng, ngc li ngun nui cab so snh tng t b ngt.Bn c c th t phn tch cc tn hiu cn li.

Tm li lp trnh cho b so snh tng t ta thc hin cc bc sau:

1. Chn ng vo dng( l in th tham chiu ni hay chnAIN0 )bng cch thitlp bit ACBG.

2. Chn ng vo m( l cc chn ADC hay chn AIN1 ) bng cch thit lp cc bitACME v ADEN.

3. Chn kiu hot ng ca b so snh tng t nh: s dng ngt, kt ni ti b nhthi 1

4. Ghi bit ACD thnh 0 cho php b so snh tng t hot ng.

II. B BIN I ADC


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1. Gi Thiu B ADC Ca ATmega128.

Bbin i ADC c chc nng bin i tn hiu tng t (analog signal) c gi tr

thay i trong mt di bit trc thnh tn hiu s (digital signal). B ADC caATmega128 c phn gii 10 bit, tc ti a 1 Mbps, sai s tuyt i 2 LSB, di tnhiu ng vo t 0v VCC, tn hiu ng vo c nhiu la chn nh : c 8 ng vo a hpn hng (Multiplexed Single Ended), 7 ng vo vi sai (Differential Input), B ADCca ATmega128 l loi ADC xp x lin tip (succesive approximation ADC) vi hai ch hot ng c th lu chnl chuyn i lin tc(Free Running) v chuyn i tngbc(Single Conversion). S khi n gin ca mt b ADC c th hin nh hnh5.2.

Hnh 5.2. S n gin ca mt khi ADC

Nguyn tc hot ng ca khi ADC : Tn hiu tng t a vo cc ng ADC0:7

c ly mu v bin i thnh tn hiu s tng ng. Tn hiu s c lu trong hai thanhghi ACDH v ADCL. Mt ngt c th c to ra khi hon thnh mt chu trnh bin iADC.

Thc t, b ADC ca ATmega128 phc tp hn nhiu, tuy nhin c s vn da vonguyn tc trn. kho st b ADC ca ATmega128 ta cn tm hiu cc khi chc nngsau:


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in Th Tham Chiu: l gi tr in th dng so snh vi in th ca tn hiutng t cn bin i ng vo ADC. ATmega128 c 3 la chn in th tham chiu lAVCC bng vi VCC, in th tham chiu ni 2.56v, v Vref l ty chn.Bn c cn

l AVR c 2 ngun in th tham chiu ni l internal reference= 2.56v v bandgapreference= 1.24v. in th bandgap reference l mt hng s vt l, n lun l 1.24v,cn in th internal reference th c th thay i ty theo cc dng chip khc nhau.Trong AVR, internal reference c to ra t bandgap reference.Trong ti liu ny,tc gi iu dch hai dng in th trn iu l in th tham chiu ni,tuy vy, bn cnn hiu s khc nhau gia hai khi nim trn.

Tn S Clock ADC: l tn s clock cung cp cho b bin i ADC, gi tr c ththay i t vi KHz n vi MHz. Tuy nhin, tn s thch hp khong t 50KHz n200KHz cho phn gii 10 bitv c th cao hn200KHz nu phn gii thp hn.

Ng Vo Tng T: ATmega128 c hai la chn ng vo tng t:

- 10 ng vo n hng(single ended):10 ng vo ny l ADC0:7, AGND v bandgapreference. Thc t ta thng dng 8 ng vo ADC0:7. V c 8 ng vo ADC0:7 nn tac th a vo 8 tn hiu tng t khc nhau. Khi la chn ng vo kiu ny (tc kiusingle ended) th kt qu chuyn i c tnh nh sau:

- Ng vo vi sai: Ta c tha hai tn hiu tng t vo ng vo ADC, hai tn hiutng t ny s qua mt b vi sai (mch tr), kt qu ng ra c th c khuch iri sau mi a vo khi ADC bin i. B vi sai c 2 ng vo l Vpos(ng vodng) v Vneg(ng vo m). Cc chn ADC3:7 dng lm ng vo dng, cc chnADC0:2 l ng vo m, hnh 5.3. i vi la chn ny, kt qu ADC s l :

y Gain l li c th ty chn. Cng thc trn cho thy kt qu ADC c thl s m khi Vpos < Vneg. Do , di gi tr ca ADC trong trng hp ny l -512 ti511. V vy, kt qu trong thanh ghi ADC c biu din di dng s b 2. bit c

*1024VinADC

Vref

( ) * *512POS NEG

REF

V V Gain

ADC V


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kt qu l s m hay dng ta kim tra bit ADC9 (trong thanh ghi ADCH), nu bit ny l 1th kt qu l s m, nu bit ny l 0 th kt qu l s dng.

Ch : in th qua b vi sai c th m, nhng in th cp cc ng vo ADC0:7(cho c hai trng hp ng vo vi sai v ng vo n hng) phi lun nm trong khong

0vAVCC.

Hnh 5.3. Ng vo vi sai

Ch Hot ng: C hai ch hot ng ca b ADC l chuyn i lin tc(Free Running) v chuyn i tng bc(Single Conversion).

- Chuyn i lin tc: l ch m sau khi khi ng th b ADC thc hin chuyni lin tc khng ngng.

- Chuyn i tng bc: l m b ADC sau khi hon thnh mt chuyn i th sngng, mt chuyn i tip theo ch c bt u khi phn mm c yu cu chuyni tip.

2.Cc Thanh Ghi Ca B ADC.


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a. Thanh ghi ADC Multiplexer Selection - ADMUX

Bit 7:6REFS1:0: Reference Selection Bits Bit 5ADLAR: ADC Left Adjust Result Bits 4:0MUX4:0: Analog Channel and Gain Selection Bits

Bit 7:6 REFS1:0: Reference Selection Bits: hai bit ny dng la chn inth tham chiu l mt trong 3 ngun: AVCC, in th tham chiu ni 2.56v v VREFnh bng 97. Nu chn in th VREF th cc ty chn cn li khng c s dng trnh b ngn mch, iu ny c ngha l nu ta chn in th tham chiu l VREFri, thtrong sut qu trnh hot ng ca b ADC ta khng c la chn in th tham chiukhc, v nu khng, ngun in th VREFbn ngoi do cha c tho i s lm hng chipdo ngn mch.

Bng 97. La chn in th tham chiu

Bit 5ADLAR: ADC Left Adjust Result: Bit ny la chn cch b tr d liu tronghai thanh ghi d liu ADCH v ADCL. Xem phn m t hai thanh ghi d liu ADCHv ADCL bit chi tit.

Bits 4:0MUX4:0: Analog Channel and Gain Selection Bits: Cc bit ny la chnkiu ng vo (n hay vi sai) v li, xem bng 98.


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Bng 98. La chn kiu ng vo v li


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b. Thanh ghi ADC Control and Status Register AADCSRA

Bit 7 ADEN: ADC Enable Bit 6 ADSC: ADC Start Conversion Bit 5 ADFR: ADC Free Running Select Bit 4 ADIF: ADC Interrupt Flag Bit 3 ADIE: ADC Interrupt Enable Bits 2:0 ADPS2:0: ADC Prescaler Select Bits

Bit 7 ADEN: ADC Enable: Bit ny l 1 scho phpbADC hot ng, ngc li, sngng b ADC ngay c khin ang trong qu trnh bin i. Bit 6 ADSC: ADC Start Conversion: Ghi bit ny thnh 1 bt u qu trnh chuyni. Trong ch chuyn i tng bc, sau mi ln chuyn i hon thnh bit ny b xav 0, ta phi set li bit ny bt u mt bin i tip theo. Trong ch chuyn i lintc, ta ch cn set bit ny mt ln. Bit 5 ADFR: ADC Free Running Select: Set bit ny ln 1 la chn ch hot

ng bin i lin tc. Bit ny l 0 s cho php ch bin i tng bc. Bit 4 ADIF: ADC Interrupt Flag: Bit ny s c set thnh 1 khi mt chu trnh bin

i ADC hon thnh, bit ny c xa bi phn cng khi trnh phc v ngt tng ngc thc thi. Ch l khi ta chnh sa thanh ghi ADCSRA (nh dng cc lnh CBI, SBI)th bit ny s b xa. V vy, xa bit ny bi phn mm, ta ch cn ghi gi tr 1 vo n. Bit 3 ADIE: ADC Interrupt Enable:Bit ny cho php ngt ADC, khi bit ADIE (cho

php ngt ADC) v bit I (cho php ngt ton cc) trong thanh ghi SREG c set ln 1 scho php ngt ADC hot ng. Bits 2:0 ADPS2:0: ADC Prescaler Select Bits: V tn s clock ADC c ly t xungclock h thng (hnh 109), nn cc bit ADPS2:0 s cho php chia xung clock h thng vicc h s xc nh (bng 99) trc khi a vo ngun clock ADC. Vi phn gii 10 bit,tn s clock ADC khong t 50 200 KHz, nn ty theo tn s clock h thng m ta lachn h s chia thch hp.

: Trnh bin dch AVRStudio 4 ca Atmel xem ADCSRA v ADCSR l mt, c hai iuch ti thanh ghi ADCSRA. Chn hn, lnh sbiADCSRA, ADSC v sbiADCSR, ADSC ltng ng.


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Hnh 109. Ngun clock ADC

Bng 99. La chn cc h s chia cho ngun clock ADC

c. Thanh ghiADC Data RegisterADCL and ADCH

y l hai thanh ghi cha kt qu ADC, ty theo thit lp ca bit ADLAR (trongthanh ghi ADMUX) m 10 bit d liu ADC c th c b tr v pha phi hay tri cahai thanh ghi ADCH v ADCL, c th nh sau:


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ADLAR = 0

ASDLAR = 1

Tm tt: s dng b ADC ta thc hin cc bc sau:

1.

Cu hnh cho b ADC: chn in th tham chiu, kiu ng vo bng cch cu hnhcho thanh ghi ADMUX.

2.

Cho php ADC hot ng: Chn ch hot ng, cc ngt, tn s Clock ADCbng cch cu hnh cho thanh ghi ADCSRA.

V d. on chng trnh nh sau cho php b ADC hot ng ch bin itngbc, ng vo l chn ADC3, khng dng ngt.(vit bng C c th xem chng VII)

ADC_Init:

ldir16,3 ;outADMUX, r16 // chn ng vo ADC3, in th tham chiu VREF

ldir16, 0b10000101outADCSRA, r16 // khng dng ngt, h s chiaclock l 32, chy tng bc

sbiADCSRA, ADSC // khi ng b ADC

Wait:

sbisADCSRA, ADIF //i ADC hon thnhrjmpWait

inr16, ADCL // lu kt qu ADCinr17,ADCH


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III.B TRUYN NHN D LIU NI TIP USART

1.Tm Lc V USART.

USART (Universal Synchronous and Asynchronous serial Receiver andTransmitter):B Truyn Nhn Ni Tip ng B V Bt ng B Ph Qut, y l khichc nng dng cho vic truyn thng gia vi iu khin vi cc thit b khc. Trong vn truyn d liu s, c th phn chia cch thc (method) truyn d liu ra hai ch (mode) c bn l :Ch truyn nhn ng b(Synchronous) v Ch truyn nhnBtng b(Asynchronous). Ngoi ra, nu gc phn cngth c th phn chia theo cchkhc l: Truyn nhn d liu theo kiu Ni tip(serial) v Song song(paralell).

Truyn Nhn ng B: l kiu truyn d liu trong b truyn (Transmitter) vb nhn (Receiver) s dng chung mt xung ng h (clock). Do , hot ngtruyn v nhn d liu din ra ng thi. Xung clock ng vai tr l tn hiu ng

b cho h thng (gm khi truyn v khi nhn).u im ca kiu truyn ng bl tc nhanh, thch hp khi truyn d liu khi (block).

Truyn Nhn Bt ng B: L kiu truyn d liu trong mi b truyn(Transmitter) v b nhn (Receiver) c b to xung clock ring, tc xung clock hai khi ny c th khc nhau, nhng thng khng qu 10 o/o . Do khng dngchung xung clock, nn ng b qu trnh truyn v nhn d liu, ngi ta phitruyn cc bit ng b (Start, Stop,) i km vi cc bit d liu. Ccb truyn v

b nhns da vo cc bit ng b ny quyt nh khi no th s thc hin haykt thc qu trnh truyn hoc nhn d liu. Do , h thng truyn khng b cnc gi l h thng truyn t ng b.

T hai kiu truyn d liu c bn trn, ngi ta a ra nhiu giao thc (Protocol) truynkhc nhau nh: SPI (ng b), USRT (ng b), UART (bt ng b),Tuy vy, cng cgiao thc truyn m khng th xp c vo kiu no: ng b hay bt ng b, chn hnkiu truyn I2C (Trong AVR gi l TWI), tuy vy mt cch hi gng p th c th thygiao thc truyn I2C gn vi kiu ng b hn v cc thit b giao tip vinhau theo chunI2C iu dng chung mt xung clock.

2.Gi Thiu B USART Ca ATmega128.

ATmega128 c hai b USART l USART0 v USART1. Hai b USART ny l c

lp nhau, iu ny c ngha l hai khi USART0 v USART1 c th hot ng cng mtlc. S khi n gin ca khi USART th hin trong hnh 79.


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Hnh 79. S khi b USART

S khi ca b USART phn chia thnh ba phn r rng: Khi to xung clock (clockGenerator), Khi Truyn (Transmitter) v Khi nhn (Receiver).Cn cc thanh ghi iukhin USART c dng chung.

(Phn ny cha y , cn c bn c b sung)


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ChngVIH THNG XUNG CLOCK V LP TRNH B NH

ON-CHIP

I. H THNG XUNG CLOCKH thng xung clock ca ATmega128 cchia thnh nhiu khi khc nhau, mi

khi (module ) s cung cp xung clock cho cc khi ngoi vi ng dng tng ng. Hnh 18th hin s ca h thng xung clock trn ATmega128.


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cu hnh cho chip hot ng theo ch xung clock no, ngi ta dng cc bitcu ch ( fuse bit ) CKSEL 3, CKSEL2, CKSEL 1. Ngoi ra khi vi iu khin c nhthc t cc ch ngh sang ch hot ng bnh thng, b to dao ng cn c mtkhong thi gian n nh, khong thi gian ny gi l thi gian khi ng ( start -up

time ). CPU ch thc hin lnhkhi ht khong thi gian khi ng ny. Khi ta reset CPUcng cn mt khong thi gian tr hon (delay time ) ngun nui t mc n nh trckhi thc bt u thc thi lnh. Ngi ta dng cc bit cu ch CKSEL 0, SUT1, SUT0 thit lp thi gian khing v thi gian tr hon.Khong thi gian khi ng v thi giantr hon c o c o bng mt ng h ring, l b dao ng Watchdog. Tn sca b dao ng Watchdog ph thuc vo in th ngun nui v nhit mi trng. Vcc = 5V v nhit 25oC th tn s ca b dao ng Watchdog l 1 MHz.Lin quan nvic thit lp ca h thng xung clock ngi ta cn dng ti bit cu ch CKOPT m vai trca n kh linh hot ty theo vic thit lp xung clock cho h thng nh th no.Hnh 18cho thyATmega128 c ti 7 b to xung clock c th c la chn. Di y l m t

c th cho tng trng hp cu hnh xung clock ca h thng.

1. B DAO NG THCH ANH

B dao ng thch anh c mc theo hnh 19. Trong chn XTAL1 v XTAL2 (tng ng chn s 24 , 23 ca vi iu khin ) ln lt l ng vo v ng ra ca bkhuch i o c tch hp sn trong chip.

Hnh 19. Ghp ni b dao ng thch anh

Gi tr ca t C1 v C2 phi bng nhau v thng c gi tr vo khong 12pF 22pF. ViATmega128 th tn s xung clock h thng ti a l 16MHz v t c tn s ti any bit cu ch CKOPT phi c lp trnh ( ghi thnh 0 ). Nu bit CKOPT khng c lptrnh ( ghi gi tr 1 ) th tn s ti a ch l 8 MHz. Cc bit CKSEL3..1 c dng la


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chn di tn s ti u nh trong bng 8. Cc bit CKSEL0 v SUT1..0 c dng thitlp thi gian khi ng ( start-up ) v thi gian tr hon ( delay time ) nh trong bng 9.Tacng c th thay th tinh th thch anh ( Quartz crystal ) bng gm cng hng ( CeramicResonator ).

Bng 8. Ti u di tn s

La chn (1) ch nn dng cho gm cng hng, khng nn dng cho thch anh

Bng 9. Thit lp thi gian khi ng v tr hon


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V d s dng thch anh 16 MHz lm xung clock h thng, thi gian khi ng l 16 K( 16384 chu k xung clock ca b dao ng watchdog ) v thi gian tr hon l 65 ms th tacn thit lp cho cc bit cu ch l :

{ CKOPT, CKSEL3..0, SUT1..0 } = { 0, 1, 0, 1, 1, 1, 1 }

2. B DAO NG THCH ANH C TN S THP

Thch anhtrong trng hp ny c tn s thp 32,768 KHz c mc vo mch nhhnh 19. Tn s thp c s dng gim cng sut tiu th ca h thng v thch hpcho cc ng dng cn o thi gian thc. cu hnh cho h thng xung clock theo ch ny, cn thit lp cc bit cu ch { CKSEL3..0 } = { 1, 0, 0, 1 }. Cc t C1, C2 cng c thc b i bng cch lp trnh cho bit CKOPT cho php t bn trong chip hot ng. T

bn trong chip c gi tr nh danh l 36 pF.Thi gian khi ng v thi gian tr hon cla chn nh vo cc bit cu ch SUT1..0 theo nh bng 10.

Bng 10. Thit lp thi gian khi ng v tr hon

3. B DAO NG R-C BN NGOI

B dao ng R-C bn ngoi thch hp cho nhng ng dng khng i hi cao v schnh xc thi gian . Mch R-C c mc nh hnh 20. Tn s dao ng vo khon

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