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VLSI Design

(2mark questions and answers)

Unit I

1. Define Threshold voltage

The threshold voltage VT for a MOS transistor can be defined as the

voltage between the gate and the source terminals below which the drain

to source current effectively dros to !ero"

Define body effect or substrate bias effect.

The threshold voltage VT is not a constant with resect to the voltage

difference between the substrate and the source of the MOS transistor"

This effect is called the body effect or substrate bias effect"

2. Give the different modes of oeration of !"S transistor

#ut off mode

$inear mode

Saturation mode

#. $hat are the different regions of oeration of a !"S transistor%

a. &ut off region

%ere the current flow is essentially !ero (accumulation mode)

b. Linear region&t is also called weak inversion region where the drain current is

deendent on the gate and the drain voltage w" r" to the substrate"

c. Saturation region

#hannel is strongly inverted and the drain current flow is ideally

indeendent of the drain'source voltage (strong'inversion region)"

'. Give the e(ressions for drain current for different modes of

oeration of

!"S transistor.

a" #ut off region

& *

b" $inear region

& kn +(V,S - VT) VS - VS2.2/

c" Saturation region

& (kn .2) (V,S - VT)2

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). *lot the current+voltage characteristics of a n!"S transistor.

,. Define accumulation mode.

The initial distribution of mobile ositive holes in a tye silicon

substrate of a mos transistor for a voltage much less than the threshold

voltage

-. $hat are the secondary effects of !"S transistor%

a" Threshold voltage variations

b" Source to drain resistance

c" Variation in &'V characteristics

d" Subthreshold conduction

e" #MOS latchu

. $hat is &!"S latchu% /o0 it can be revented%The MOS technology contains a number of intrinsic biolar

transistors"These are esecially troublesome in #MOS rocesses0 where the

combination of wells and subtrates results in the formation of 'n''n

structures" Triggering these thyristor like devices leads to a shorting of V

1 VSS lines0 usually resulting in a destruction of the chi"

The remedies for the latch+u roblem include

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(i) an increase in substrate doing levels with a consequent dro in the

value of subs"

(ii) reducing nwell by control of fabrication arameters and ensuring

a low contact resistance to V"

(iii) by introducing guard rings"

. $hat are the different fabrication rocesses available to &!"S

technology%

a" 'well rocess

b" n'well rocess

c" Twin'tub rocess

d" Silicon On &nsulator (SO&) . Silicon On Sahire (SOS) rocess

13. $hat is intrinsic and e(trinsic semiconductor%

The ure silicon is known as &ntrinsic Semiconductor" 3hen imurityis added with ure silicon0 it is electrical roerties are varied" This is known

as 45trinsic semiconductor"

12. $hat are the stes involved in manufacturing of I&%

66 i" wafer rearation

ii" 4ita5ial growth

iii" O5idation

iv" hoto lithograhy

v" iffusion and &on &mlantation

vi" &solation

vii" Metalli!ation

1#. $hat is meant by 4 eita(y 5 %

4ita5y means arranging atoms in single crystal fashion uon a single

crystal substrate"

1'. 0hat are the rocess involved in hoto lithograhy%

i" making rocess

ii" hoto etching rocessthese are imortant rocess involved in hotolithograhy"

1). 0hat is the urose of mas6ing in fabrication of I&%

Masking is used to identify the lace in which &on &mlantion should

not be occurred"

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1,. 0hat are the materials used for mas6ing%

7hoto resist0 Sio20 Si80 oly Silicon"

1-.0hat are the tyes of etching %

3et etching and dry etching are the tyes of hoto etching"

1. 0hat is diffusion rocess % 0hat are doing imurities%

iffusion is a rocess in which imurities are diffused in to the silicon

chi at 9****# temerature" :2O;and 72O

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2). 0hat is t0in+tub rocess% $hy it is called so%

Twin'tub rocess is one of the #MOS technology" There are two

wells are available in this rocess" The other name of well is tub" So0

because of these two tubs0 this rocess is known as twin'tub rocess"

Unit II

1. Dra0 the circuit of a n!"S inverter.

"

2. Give the e(ression for ull+u to ull+do0n ratio 8 Zpu/Zpd9 for ann!"S

inverter driven by another n!"S inverter.

"

"

#. Dra0 the circuit of a &!"S inverter.

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'. $hat are the advantages of &!"S inverter over the other inverter

configurations%

a" The steady state ower dissiation of the #MOS inverter circuit is

negligible"

b. The voltage transfer characteristic (VT#) e5hibits a full outut

voltage wing between *V and V" This results in high noise margin"

). $hat are stic6 diagrams%

Stick diagrams are used to convey layer information through the

use of a color code" = stick diagram is a cartoon of a chi layout" They

are not e5act models of layout" The stick diagram reresents the

rectangles with lines which reresent wires and comonent symbols"

,. $hat are the different color codes used for single oly silicon n!"S

technology%

n'diffusion (n'diff") and other thino5ide regions 'green

7olysilicon (oly") ' red

Metal 9 (metal) ' blue

&mlant ' yellow

#ontacts ' black or brown (buried)

-. $hat are design rules%

esign rules are the communication link between the designer

secifying requirements and the fabricator who materiali!es them" esign

rules are used to roduce workable mask layouts from which the various

layers in silicon will be formed or atterned"

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. Define a suerbuffer.

= suerbuffer is a symmetric inverting or noninverting gate that can

suly or remove large currents and switch large caacitive loads faster

than a standard inverter"

.$hat are :i&!"S Gates%

3hen biolar and MOS technology are merged0 the resulting circuits

are referred to as bi#MOS circuits" %igh gain vertical nn transistors with

their collectors tied to the ositive rail0 and medium'gain lateral nn

transistors are both comatible with conventional #MOS rocessing"

:i#MOS gates can be used to imrove the erformance of line drivers and

sense amlifiers"

13. 0hat is the secial feature of t0in+tub rocess%

&n twin'tub rocess0 threshold voltage0 body effect n and devices areindeendently otimi!ed"

11. 0hat are the advantage of t0in+tub rocess%

=dvantages of twin'tub rocess are

i" Searate otimi!ed wells are available"

ii" :alance erformance is obtained for n and transistors"

12. 0hat is S"I% $hat is the material used as Insulator%SO& means Silicon'on'&nsulator" &n this rocess0 Sahire or SiO2is

used as insulator"

1#. 0hat are the various etching rocess used in S"I rocess%

Various etching rocess used in SO& are

i" &sotroic etching rocess"

ii" =nisotroic etching rocess"

iii" 7referential etching rocess"

1'. 0hat are the advantages and disadvantages 3f S"I rocess%

7dvantages of S"I rocess

i" There is no well formation in this rocess"

ii" There is no field'&nversion roblem"

iii" There is no body effect roblem"

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Disadvantages of S"I rocess

i" &t is very difficult to rotect inuts in this rocess"

ii" evice gain is low"

iii" The couling caacitance between wires always e5ist"

1). 0hat are the ossible modes in n!"S enhancement transistor%

i" accumulation mode

ii" deletion mode

ii" &nversion mode

1,. In saturation region; 0hat are the factors that affect Ids%

i" distancebetween source and drain"

ii" channel width

iii"Threshold oltage

iv"thickness of o5ide layer

v" dielectric constant of gate insulator

vi" #arrier mobility"

1-. $hat is :ody effect%

The threshold voltage VT is not a constant w" r" to the voltage difference

between the substrate and the source of MOS transistor" This effect is called

substrate'bias effect or body effect"

1.$hat is &hannel+length modulation%

The current between drain and source terminals is constant and

indeendent of the alied voltage over the terminals" This is not entirely

correct" The effective length of the conductive channel is actually modulated

by the alied VS0 increasing VS causes the deletion region at the drain

?unction to grow0 reducing the length of the effective channel"

1.Define Threshold voltage in &!"S%

The Threshold voltage0 VTfor a MOS transistor can be defined as the

voltage alied between the gate and the source of the MOS transistor below

which the drain to source current0 &Seffectively dros to !ero"

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23. Define

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1. $hat are the static roerties of comlementary &!"S Gates%

a" They e5hibit rails'to'rail swing with VO% V and VO$

,8"

b" The circuits have no static ower dissiation0 since the circuits are

designed such that the ull'down and ull'u networks are mutually

e5clusive"

c" The analysis of the # voltage transfer characteristics and the noise

margins is more comlicated than for the inverter0 as these arameters

deend uon the data inut atterns alied to the gate"

2. Dra0 the e>uivalent

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reali!es the logic function and a simle load device0 which relace the entire

ull'u network" = ratioed logic which uses a grounded MOS load is

referred to as a seudo'nMOS gate

). $hat is true single hase cloc6ed register%

The True single'hase clocked register (TS7#) uses a single clock0

#$C" Dor the ositive latch0 when #$C is high0 the latch is in the

transarent mode and corresonds to two cascaded invertersE the latch is

non'inverting0 and roagates the inut to the outut" On the other hand0

when #$C*0 both inverters are disabled0 and the latch is in the hold mode"

,. Define a tally circuit.

= tally circuit counts the number of inuts that are high and oututs the

answer" &f there are 8 inuts there are 8 F9 ossible oututs0 corresonding

to *0 90 20 G" 8 inuts that are high"

-. Give the ?7?D+1A1BCL*S"/*/$D$L

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A" Dra0 the &!"S imlementation of '+to+1 !UK using transmission

gates "

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13. $hat are the various modeling used in Verilog%

9" ,ate'level modeling

2" ata'flow modeling

;" Switch'level modeling

H" :ehavioral modeling

11. $hat is the structural gate+level modeling%

Structural modeling describes a digital logic networks in terms of the

comonents that make u the system" ,ate'level modeling is based on using

rimitive logic gates and secifying how they are wired together"

12.$hat is S0itch+level modeling%

Verilog allows switch'level modeling that is based on the behavior of

MOSD4Ts" igital circuits at the MOS'transistor level are described using

the MOSD4T switches"

1#. $hat are the tyes of rogrammable device%

7rogrammable logic structure

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7rogrammable &nterconnect

erogrammable gate arry

1'. $hat is &L:%

#$: means #onfigurable $ogic :lock"

1).$hat are the t0o tyes of !"S=T%

Two tyes of MOS4T are n'channel MOS4T and 'channel MOSD4T"

These are known as n'MOS and 'MOS"

1,.0hich !"S can ass logic 1 and logic 3 strongly%

'MOS can ass strong logic 9

n'MOS can ass strong logic *

1-. $hat is 7"I logic function%

=8 O &nvert logic function (=O&) imlements oeration in the order of

=80 O0 8OT oerations" So this logic function is known as =O& logic

function"

1. $hat is bubble ushing%

=ccording to e Morgan>s laws0

F

F

So 8=8 gate may be drawn as bubbled O gate" :ubbles are introducedin the inut side" This concet is known as bubble ushing"

1. Imlement y M using bubble ushing concet%

I can be imlemented using bubbled =8 gate"

F

23. $hat is "7I 221 Gate%

O=& 2290 here 229 refers to number of inuts in each section"

21. $rite the features of &!"S Domino Logic%

These structures occuy small area comared with conventional logic

structure"

7arasitic caacitance is to be small to increase the seed"

4ach gate can make one Jlogic 9> to Jlogic *> transition"

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22. $hat are the tally circuits%

Tally circuits one of the alications of the ass transistor logic"

&t is used to count the number of inuts which are high and the outut

is roduced"

2#. $hat are the various forms of inverter based &!"S logic%

i" 7seudo 8'MOS logic

ii" ynamic #'MOS logic

iii" #locked #'MOS logic

iv" #'MOS domino logic

v" n' #'MOS logic

2'. $hat is *I* in KILI?IK%

7&7 means 7rogrammable &nterconnect 7oint in K&$&8&K"

2). $hat are the advantages and disadvantages of *L7%

7dvantages of *L7

Simlicity

Small si!e

Disadvantages of *L7

Seed roblem occur (ull'us may become slow on large terms )

Unit IV

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1. Give the basic n!"S *L7 structure.

The basic 7$= structure consists of an =8 lane driving an O

lane" The terminology corresonds to a sum of roducts (SO7) reali!ation

of the desired function" The SO7 reali!ation converts directly into a 8=8'

8=8 imlementation" 3hen a roduct of sums (7OS) reali!ation is

desired0 it can be imlemented in O'=8 or 8O'8O logic" &n either

case0 the first array is referred to as the =8 lane0 and the second array as

the O lane" The line connecting the =8 lane to the O lane are called

the roduct lines"

2. $hat do you mean by &!"S *L7.

The basic #MOS 7$= is obtained by roviding a well and relacing

the ull'u devices in the 8=8'8=8 array or in the 8O' 8O array

with enhancement mode MOS devices" The #MOS array can be

recharged or not0 and can be clocked 2 =8 lane O lane egister

egister &n uts Oututs 9 with the same two'hase clocking scheme as used

for the MOS 7$=" #MOS 7$= design offers many more varieties of layoutthan does nMOS"

#. Define finite state machine.

3hen feedback is added to the =8 O 7$= structure0 the 7$=

becomes a finite state machine (DSM)" =n DSM can be designed as a Mealy

Machine or a Moore Machine" The Mealy machine has oututs0 which may

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change with inut changes in an asynchronous manner and cause erroneous

behavior" %ence0 the Mealy machine should be avoided whenever ossible"

The Moore machine has oututs which deend uon and change only with

state changes0 since all the oututs of the :oolean'logic block go through a

state register0 and are synchronously clocked"

'. $hat are the imortance of the *L7N=S! in VLSI%

(i) egularity B &t has a standard0 easily e5andable layout"

(ii) #onvenience B $ittle design effort is required"

(iii) #omacted B &t is efficient for small circuits"

(iv) Modularity B &t makes it ossible to design hierarchical 7$=s and

DSMs into large sequential systems"

(v) Suitability to being comuter generated"

). Give the structure of a &*LD.= #7$ comrises multile circuit blocks on a single chi0 with

internal wiring resources to connect the circuit blocks" 4ach circuit block is

similar to a 7$= or a 7=$"&t includes four 7=$ like blocks that are

connected to a set of interconnection wires" 4ach 7=$ like block is also

connected to a sub circuit labeled &.O block0 which is attached to a number

of the chi>s inut and outut ins"

,. Give the &*LD ac6ages available.

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a" *L&& ac6ageB The 7$## ackage has ins that Lwra around

the edges of the chi on all four of its sides" The socket that houses the

7$## is attached by solder to the circuit board0 and the 7$## is held in the

socket by friction"

b. >uad flat ac6 ac6age The ND7 ackage has ins on all four

sides0 and they e5tend outward from the ackage0 with a downward'wiring

shae" The ND7>s ins are much thinner than those on a 7$##0 which

means that the ackage can suort a larger number of insE ND7s are

available with more than 2** ins"

-. Give the structure of !7K -333 &*LD.

. $hat is meant by =*G7%

= field rogrammable gate array (D7,=) is a rogrammable logic

device that suorts imlementation of relatively large logic circuits" D7,=s

can be used to imlement a logic circuit with more than 2*0*** gates

whereas a #7$ can imlement circuits of uto about 2*0*** equivalentgates" D7,=s are quite different from #7$s because D7,=s do not

contain =8 or O lanes" &nstead0 they rovide logic blocks for

imlementation of the required functions"

A" Give the general structure of =*G7"

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13. $hat are the different commercial =*G7 roducts%

Manufacturer D7,= roducts www $ocator

=ctel =ct 902 and ;0MK0SK www"actel"com

=ltera D$4K***0P*** and 9*k =74K 2*kwww"altera"com

=tmel =T***0 =TH*k www"ateml"com$ucent O#= 902 and ; www"lucent"com

Nuick$ogic =S 902 and ; www"quicklogic"com

Vantis VD& www"vantis"com

Kilin5 K#;***0K#H***0K#

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i" #ontrol logic alication

ii" &nut.Outut

iii" ata'ath logic

1). $hat is finite state machine 8=S!9%3hen feedback is added to =8'O 7$= structure0 then it becomes DSM"

1,. $hat are the characteristics of *L7N=S!%

i" egularity

ii" Modularity

iii" Suitability

iv" 4fficiency

1-. $hat is &L:%#$: means #onfigurable $ogic :lock"

1. Define mealy machine%

&n mealy machine0 outut may change with the change in the inut

asynchronously"

1. Define moore machine%

&n moore machine0 outut can be changed when state is changed"

23. $hat is /DL%

V%S %ardware descrition $anguage"

21. $hat is V/SI&%

Very %igh Sed &ntegrated #ircuits"

22. $hat are the various oerators in V/DL%

i" $ogical oerators

ii" elational oerators

iii" Shift oerators

iv" =dding oerators

v" Multilying oerators

vi" Miscellaneous oerators

2#. $hat are the data tyes available in V/DL%

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i" Scalar tye

ii" #omosite tye

iii" =ccess tye

iv" Dile tye

2'. $hat are the tyes of subrograms%

Dunctions and 7rocedures are tyes of subrograms"

2). $hat is the use of actual%

=ctual in a subrogram call is used to ass the values from and to a

subrogram"

U?IT )

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V/DL

19$rite the acronym for V/DL%

V/DL is an acronym for V/SI& %ardware escrition $anguage

(V%S is an acronym for Very %igh Seed &ntegrated #ircuits)"

29 $hat are the different tyes of modeling V/DL%

9) Structural modeling

2) ata flow modeling

;) behavioral modeling

H) Mi5ed tye of modeling

#9 $hat is ac6ages and 0hat is the use of these ac6ages

= ackage declaration is used to store a set of common declaration

such as comonents tyes rocedures and functions these declaration canthen be imorted into others design units using a use caluse"

'9 $hat is variable class ;give e(amle for variable

=n ob?ect of variable class can also hold a single value of a given tye

0 %owever in this case different values can be assigned to a variable at

different time"

45Bvariable ssB integerE

)9 ?ame t0o subrograms and give the difference bet0een these t0o.

9) Dunction 2) rocedure

Only one outut is ossible in function""

Many oututs ossible using rocedure

,9 $hat is subrogram "verloading

&f two or more subrogram to be e5ecuted in a same name"

overloading of subrogram should be erformed"

-9 0rite the V/DL coding for a se>uential statement 8d+fliflo 9

entity dff isort(clk0dBin stdQlogicE

qBout stdQlogic)E

endE

architecture dff of dff is

begin

rocess(clk0d)

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begin

if clk> event and clk> 9> then

qRdE

end rocessE

endE

9 $hat are the different 6inds of The test bench

Stimulus only

Dull testbench

Simulator secific

%ybrid testbench

Dast testbench

9 $hat is !oore =S!

The outut of a Moore finite state machine(DSM) deends only on thestate and not on its inuts" This tye of behaviour can be modeled using a

single rocess with the case statement that switches on the state value"

139 $rite the testbench for and gate

entity testand2 is

end entity

architecture io of testand2 is

signal a0b0cBstdQlogicE

begin

g9Bentity work"and2(e52) ort ma(a0b0c)

aR> *> 0> 9> after 9** nsE

bR> *> 0 J9> after 9

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i" To create waveforms and aly stimulus at discrete time intervals"

ii" To generate stimulus based on the state of the entity or outut of the

entity"

1'. Differentiate bet0een channeled F channel less gate array.#hanneled ,ate =rray #hannel less ,ate =rray

9" Only the interconnect is customi!ed only the to few mask layers are

customi!ed"

2" The interconnect uses redefined saces between rows of base cells" 8o

redefined areas are set aside for routing between cells"

;" outing is done using the saces outing is done using the area of

transistors unused"

H" $ogic density is less $ogic density is higher"

1). $hat is a =*G7%

= field rogrammable gate array (D7,=) is a rogrammable logic device

that suorts imlementation of relatively large logic circuits" D7,=s can be

used to imlement a logic circuit with more than 2*0*** gates whereas a

#7$ can imlement circuits of uto about 2*0*** equivalent gates"

1,. $hat are the different methods of rogramming of *7Ls%

The rogramming of 7=$s is done in three main waysB

Dusible links

V - erasable 47OM 447OM (427OM) - 4lectrically 4rasable 7rogrammable OM

1-.$hat is an antifuse%

=n antifuse is normally high resistance (U9**M3)" On alication of

aroriate

rogramming voltages0 the antifuse is changed ermanently to a low'

resistance

structure (2**'

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#ircuit level

1.$hat are macros%

The logic cells in a gate'array library are often called macros"

23. $hat are *rogrammable Interconnects%

&n a 7=$0 the device is rogrammed by changing the characteristics if the

switching element" =n alternative would be to rogram the routing"

21. Give the stes in7SI& design flo0.

a" esign entry

b" $ogic synthesisSystem artitioning

c" 7relayout simulation"

d" Dloorlanning

e" 7lacementf" outing

g" 45traction

22. $rite notes on functionality tests%

Dunctionality tests verify that the chi erforms its intended function" These

tests assert that all the gates in the chi0 acting in concert0 achieve a desired

function" These tests are usually used early in the design cycle to verify the

functionality of the circuit"

2#. $rite notes on manufacturing tests%

Manufacturing tests verify that every gate and register in the chi functions

correctly" These tests are used after the chi is manufactured to verify that

the silicon is intact"

2'. !ention the defects that occur in a chi%

a) layer'to'layer shorts

b) discontinuous wires

c) thin'o5ide shorts to substrate or well

2). Give some circuit maladies to overcome the defects%

a" nodes shorted to ower or ground

b" nodes shorted to each other

c" inuts floating.oututs disconnected