MC LC

MC LC1PHN CNG CNG VIC3NI DUNG TI41.Quy trnh thit k ASIC s dng b phn mm ca Synopsys41.1Tng quan v cng ngh ASIC41.2 Quy trnh thit k ASIC51.3B phn mn Synopsys72.Tng quan ti93.S khi ca cc module.93.1 Module digital_clock_top93.2 Module counter113.3Module extract_bits.133.4 Module LED_7_segs.154.RTL Coding164.1 Module Top_DongHoSo164.2 Module Counter174.3 Module ExtractBits184.4 Module Led7seg195.M phng trn ModelSim205.1 Module TestBench206.Thit k trn Synopsys226.1 Leda226.2 VCS_Kim tra chc nng trc khi tng hp.266.3 Design Compiler:286.4 VCS_Kim tra sau khi tng hp456.5 Formality466.6 Primetime trc khi layout516.7 IC Compiler566.8 VCS_ Kim tra sau khi layout756.9 PT_Kim tra sau khi layout76TNG KT79

PHN CNG CNG VIC

STTH tnMSSVCng vic

1V Ngc Din20111327Thit k Synopsys

2Nguyn Vn Hip20111591V s khi trn Visio v vit bo co

3ng nh Lm20111735Thit k trn Synopsys

4L Vn Sn20112066Code verilog

5Nguyn Trung Thnh20112190Code verilog v m phng

NI DUNG TI1. Quy trnh thit k ASIC s dng b phn mm ca Synopsys1.1 Tng quan v cng ngh ASIC ASIC - Application Specific Integrated Circuit: mch thch hp ng dng chuyn bit. ASIC c xy dng bng vic kt ni cc mch c sn d c xy dgj theo cc phng php mi v vy ASIC thun tin v d dng hn. Asic l mt mch thch hp c sn xut cho mt ng dng c trng v thng c kch thc tng nh. Cng ngh ASIC c s dng rng khp trong cc thit b iu khin t ng iu khin cc chc nng ca cc phng tin truyn thng, xe c, cc h thng x l, dy chuyn cng nghip1.1.1 S lc qu trnh pht trin ca mch thch hp IC SSI : Small Scale Intergation Mch tch hp c nh ( 4'd4) c1 = d1 + 2'd3;else c1 = d1;d2={c1[2:0],number_i[2]};if(d2>4'd4) c2 = d2 + 2'd3;else c2 = d2;d3={c2[2:0],number_i[1]};if(d3>4'd4) c3 = d3 + 2'd3;else c3 = d3;if(number_i== 6'b111111) begintens_o = 4'b1111;units_o = 4'b1111;endelsebegintens_o = {1'b0, c1[3], c2[3], c3[3]};units_o = {c3[2:0], number_i[0]};endendendmodule4.4 Module Led7segmodule led7seg(output_o,input_i, en);input [3:0]input_i;input en;output reg [6:0]output_o;always @(en or input_i)beginif(en) begin if(input_i == 0) output_o = 7'b1111110; else if(input_i == 1) output_o = 7'b0110000; else if(input_i == 2) output_o = 7'b1101101; else if(input_i == 3) output_o = 7'b1111001; else if(input_i == 4) output_o = 7'b0110011; else if(input_i == 5) output_o = 7'b1011011; else if(input_i == 6) output_o = 7'b1011111; else if(input_i == 7) output_o = 7'b1110000; else if(input_i == 8) output_o = 7'b1111111; else if(input_i == 9) output_o = 7'b1111011; else output_o = 7'b1111110;endelse output_o = 7'b0000000;endendmodule

5. M phng trn ModelSim5.1 Module TestBench` module tb_digital_clock(); reg rst;reg clk;regen;wire[6:0] hour_led_tens;wire[6:0] hour_led_unit;wire[6:0] min_led_tens;wire[6:0] min_led_unit;wire[6:0] sec_led_tens;wire [6:0] sec_led_unit;DongHoSo test(.rst(rst),.en(en),.clk(clk),.tens_hour_o(hour_led_tens),.units_hour_o(hour_led_unit),.tens_min_o(min_led_tens),.units_min_o(min_led_unit),.tens_sec_o(sec_led_tens),.units_sec_o(sec_led_unit));initial begin#1rst = 0; en = 0;#1rst = 1; en = 1;//#1000000000$finish;endinitial beginclk=1;forever #5 clk = ~clk;end

endmodule

6. Thit k trn Synopsys6.1 Leda To th mc rtl cha code Verilog ca thit k v th mc leda trong project. M ca s terminal, chn ng dn n th mc leda, ri g lnh leda, ca s giao din phn mm hin ra: Chn New project OK

Hnh 1 To project mi bng leda Sau khi ca s hin ra trong mc Project Name c th thay tn project c ui m rng l .pro, sau chn next.

Hnh 2 t tn cho project

Sau khi ca s mi hin ra, trong mc Verision chn 2001 (verilog 2001):

Hnh 3 Chn ngn ng miu t phn cng v phin bn Chn Next. Ca s tip theo hin ra

Hnh 4 Thm file vo project

Chn Add ri chn ng dn n th mc cha code verilog. Chn OK chn Next ca s tip theo chn Finish.

Hnh 5 To xong project Vo Check chn Load Configuration ri chon RTL. Chn biu tng ! xut hin ca s:

Hnh 6 Cu hnh chn reset v enable Sau khi xut hin ca s vo mc Test clock/reset thit lp clock v reset ri chn OK. Ca s mi s hin th cc trng thi kim tra nh sau:

Hnh 7 Check li Nu ca s hin th trng thi cc mu xanh th code c kim tra ng Nu hin th cc mu nu bo cc cnh bo nn c qua v c th iu chnh. Nu hin th cc mu phi c chi tit cc cnh bo vo sa li code tun theo cc lut mnh chn. Sau khi sa code chy li kim tra mt ln na cho n khi no trn ca s khng xut hin mu na.

6.2 VCS_Kim tra chc nng trc khi tng hp. To th mc vcs trong project. Trong th mc vcs to th mc pre_syn cha cc file sinh ra trong qu trnh m phng code RTL trc khi tng hp bng design compiler. Copy cc file .v t th mc rtl vo th mc pre_syn. Vo th mc pre_syn m ca s lnh Terminal g lnh sau: vcs -debug +v2k *.v

Hnh 8 Khi ng vcs Sau khi phn tch cc file .v xong n s to ra mt file simv trong th mc pre_syn. tip tc vo terminal g lnh sau thc hin m phng chc nng: ./simv gui

Hnh 9 Start gui VCS Sau khi ca s hin ra chn file testbench click chut phi vo chn Add to Wave ri chn New Wave view. Ca s mi hin ra bm F5 hoc chn run (mi tn c chiu hng xung di) s xut hin ra timing cn kim tra. Kt qu:

Hnh 10 Kt qu m phng Da vo kt qu hin th trn waveform chng ta c th kt lun rng code Rtl tha mn cc yu cu chc nng ca specification.1. 2. 3. 4. 5. 6. 6.1.

6.3 Design Compiler: To th mc dc trong project, vo terminal g lnh:design_vision

Giao din ngi dng hin ln:

Hnh 11 Khi ng DC

Hnh 12 Mn hnh khi ng Design Compiler

Bc 1: Ci t th vinFile Setup

Hnh 13 Ci t th vin Search path : chn ng dn n th vin milkyway : /home/lab/Desktop/milkyway/tcbn45gsbwp_120a/frame_only_HVH_0d5_0/tcbn45gsbwp/LM/ Link library : ng dn n th vin bao gm 2 th vin Synthetic library v Target library Target library: th vin cng ngh ca nh sn xut /home/lab/Desktop/milkyway/tcbn45gsbwp_120a/frame_only_HVH_0d5_0/tcbn45gsbwp/LM/tcbn45gsbwpbc.db Symbol library : th vin k hiu c sn trong th mc ci t ca synopsys/opt/synopsys/dc/libraries/syn/generic.sdb Synthetic library : th vin tng hp c sn trong th vin ca synopsys/opt/synopsys/dc/libraries/syn/dw_foundation.sldb Bc 2 : To file theo di qu trnh c ui m rng .svf. Vo terminal g lnhset_svf top.svf Bc 3: c file *.vFile Readc tt c cc file verilog trong th mc rtl tr cc file testbench.

Hnh 14 c file thit k Bc 4 : AnalyzeFile Analyze

Hnh 15 Analyze Bc 5: ElaborateFile ElaborateTrong mc Design chn file top module

Hnh 16 Elaborate Bc 6: Kim tra thit k Design Check Design OKBc ny s kim tra thit k. Trn ca s terminal s c cc cnh bo nn c k.

Hnh 17 Check Design Bc 7: Set clock constraints Chn vo biu tng trn thanh menu s hin ln schematic. S dng I (zoom in) v O (zoom out) phng to hoc thu nh s , dng ln chut v shift hoc ctrl ln xung hoc sang ngang. Chn vo tn hiu clk trong s :

Hnh 18 Chn tn hiu clock set Constraints

Sau khi chn tn hiu clk vo Atributes trn thanh Menu chn Specify Clock Ta c cc thit lp sau:create_clock -name "clk" -period 1000000000 -waveform { 0 500000000 } { clk } Trong mc Clock name t tn l clk. Trong mc Period : 1000000000 (ns)(do chu k thc hin ca ng h s l 1s ). Trong mc rising: 0 (ti 0 th xut hin sng ln ca xung nhp). Trong mc falling: 500000000 ns (ti 0.5 s th xut hin sn xung ca xung nhp). Chn Don't touch network : trong qu trnh tng hp th tn hiu clock c bo v. Chn Fix hold : khc phc cc li hold time sau khi tng hp.Ngoi ra cn c cc rng buc khc bng cch s dng cu lnh nh:- set_clock_uncertainty 10000000 [get_clocks clk] // thit lp lch gia 2 FF k tip nhau. set_clock_latency 200000000 [get_clocks clk] // thit lp tr ca xung clock t b to dao ng n FF. set_input_transition 100000000 [all_inputs] // thit lp tr chuyn trng thi ca lock ( dc ca sn clock). Bc 8: Thit lp cc rng buc thit k (constrain) Tr u vo: Chn cc tn hiu u vo trn s (tr tn hiu clock)Trn thanh Menu vo Atributes chn Operating Environment Input delay

Hnh 19 Xt constraints cho input Tr u ra : Chn cc tn hiu ra trn s Trn thanh Menu vo Atributes chn Operating Environment Output delay

Hnh 20 Xt constraints cho output iu kin hot ng (Operating condition)Trn thanh Menu vo Atributes chn Operating Environment Operating conditions

Hnh 21 Xt iu kin hot ng Wire load:Trn thanh Menu vo Atributes chn Operating Environment Wire load

Hnh 22 Wire Load Thit lp in tr, in dung u vo, u ra cho IC:Khi cc cng kch thch u vo v ti u ra cha bit th ta dng Load Budget, xc nh d phng cho thit k. Gi s cc u vo c kch thch bng cell yu nhtset all_in_ex_clk [remove_from_collection [all_inputs] [get_ports clk]]set_driving_cell -no_design_rule -lib_cell INVD0BWP $all_in_ex_clk t in dung u vo ln nht l 10 cell AN2D0BWPset MAX_INPUT_LOAD [expr [load_of tcbn45gsbwpbc/AN2D0BWP/A1] * 10]set_max_capacitance $MAX_INPUT_LOAD $all_in_ex_clk t in dung u ra ln nht l 3 khi 10 cellset_load [expr $MAX_INPUT_LOAD * 3] [all_outputs] Hnh v:

Design constraintsTrn thanh Menu vo Atributes chn Operating Environment Design constraints

Hnh 23 Xt kch thc ti a C th thit lp thm cc rng buc v cng sut ng, cng sut dng r, Max fanout, maxtransition. Bc 9 : Compile Design Trn thanh Menu vo Design Compile Design OKNgoi ra bn c thm cc la chn sao cho sau qu trnh tng hp thit k ca mnh ti u nht.

Hnh 24 Compile

Hnh 25 Kt qu sau Compile Design Bc 10: Compile Ultra Sau qu trnh tng hp thit k, bc ny s va tng hp va ti u ha thit k nhng cng no tha hoc khng cn thit trong qu trnh tng hp s b xa. Trn thanh Menu vo Design Compile Ultra OK

Sau qu trnh tng hp khi xem li s mch s tr nn phc tp hn rt nhiu:

Hnh 26 Kt qu sau Compile ultra

C th thy rng sau khi compile ultra th mch hon ton l cc standard cell ni vi nhau => c th xut ra file netlist. Bc 11 : To file .ddc File .ddc c s dng cho phn mm ICC layout v kim tra chc nng trong PrimetimeFile Save as

Hnh 27 To file *.ddc

Bc 12 : To file Netlist File Netlist l file m t mc cng ca thit k bao gm cc cell c bn (AND, OR, MUX, FF) c ni dy vi nhau.File Save as

Hnh 28 To file netlish dng cho formality

Bc 13 : To file .sdf File .sdf l file nh ngha tr tng cng, dy dn.. Vo terminal g lnh sau:write_sdf top.sdf Bc 14 : To file .sdc File .sdc (synopsys design constraints) c s dng trong ICC a cc rng buc thit k ca mnh vo thc hin layout. Vo Terminal g lnh sau:write_sdc top.sdc Bc 15 : Xut bo co Sau khi tng hp kim tra xem thit k ca mnh c p ng c cc yu cu v timing, cng sut, din tch,.. hay khng cn phi xem qua cc bo co m phn mm t ng to ra cho mnh. C mt s bo co in hnh nh sau: Report_timing : Timing Report Timing Path Hnh 29 Xut Report Timing Path Report_constraints: Design Report Constraints

Hnh 30 Xut Report Constraints Report_power : Design Report Power

Hnh 31 Xut Report Power Report_Resource : Design Report resource

Hnh 32 Xut Report resource Max time

Hnh 33 Report Timing

Min time

Hnh 34 Report Timing Bc 16 : Tt file theo di Vo terminal g cu lnh:set_svf off File .svf c s dng trong qu trnh kim tra Formality.Thit lp cho Design Compiler:set_svf top.svfread_file -format verilog {/home/lab/VLSI10/rtl/DongHoSo.v /home/lab/VLSI10/rtl/counter.v /home/lab/VLSI10/rtl/extractBits.v /home/lab/VLSI10/rtl/led7seg.v}analyze -format verilog {/home/lab/VLSI10/rtl/led7seg.v /home/lab/VLSI10/rtl/extractBits.v /home/lab/VLSI10/rtl/counter.v /home/lab/VLSI10/rtl/DongHoSo.v}elaborate DongHoSo -architecture verilog -library WORKuplevel #0 check_designchange_selection [get_s clk]create_clock -name "clk" -period 1000000000 -waveform { 0 500000000 } { clk }change_selection [get_s en]change_selection -add [get_s rst]set_input_delay -clock clk -add_delay -max -rise 200000000 "rst en"set_input_delay -clock clk -add_delay -max -fall 200000000 "rst en"set_input_delay -clock clk -add_delay -min -rise 100000000 "rst en"set_input_delay -clock clk -add_delay -min -fall 100000000 "rst en"change_selection [get_s {{tens_hour_o[6:0]} {tens_hour_o[6]} {tens_hour_o[5]} {tens_hour_o[4]} {tens_hour_o[3]} {tens_hour_o[2]} {tens_hour_o[1]}}]change_selection -add [get_s {{tens_hour_o[0]}}]change_selection -add [get_s {{tens_min_o[6:0]} {tens_min_o[6]} {tens_min_o[5]} {tens_min_o[4]} {tens_min_o[3]} {tens_min_o[2]} {tens_min_o[1]}}]change_selection -add [get_s {{tens_min_o[0]}}]change_selection -add [get_s {{tens_sec_o[6:0]} {tens_sec_o[6]} {tens_sec_o[5]} {tens_sec_o[4]} {tens_sec_o[3]} {tens_sec_o[2]} {tens_sec_o[1]}}]change_selection -add [get_s {{tens_sec_o[0]}}]change_selection -add [get_s {{units_hour_o[6:0]} {units_hour_o[6]} {units_hour_o[5]} {units_hour_o[4]} {units_hour_o[3]} {units_hour_o[2]} {units_hour_o[1]}}]change_selection -add [get_s {{units_hour_o[0]}}]change_selection -add [get_s {{units_min_o[6:0]} {units_min_o[6]} {units_min_o[5]} {units_min_o[4]} {units_min_o[3]} {units_min_o[2]} {units_min_o[1]}}]change_selection -add [get_s {{units_min_o[0]}}]change_selection -add [get_s {{units_sec_o[6:0]} {units_sec_o[6]} {units_sec_o[5]} {units_sec_o[4]} {units_sec_o[3]} {units_sec_o[2]} {units_sec_o[1]}}]change_selection -add [get_s {{units_sec_o[0]}}]set_output_delay -clock clk -add_delay -max -rise 200000000 "{tens_min_o[6]} {tens_min_o[5]} {tens_min_o[4]} {tens_min_o[3]} {tens_min_o[2]} {tens_min_o[1]} {tens_min_o[0]} {tens_sec_o[6]} {tens_sec_o[5]} {tens_sec_o[4]} {tens_sec_o[3]} {tens_sec_o[2]} {tens_sec_o[1]} {tens_sec_o[0]} {units_min_o[6]} {units_min_o[5]} {units_min_o[4]} {units_min_o[3]} {units_min_o[2]} {units_min_o[1]} {units_min_o[0]} {tens_hour_o[6]} {tens_hour_o[5]} {tens_hour_o[4]} {tens_hour_o[3]} {tens_hour_o[2]} {tens_hour_o[1]} {tens_hour_o[0]} {units_sec_o[6]} {units_sec_o[5]} {units_sec_o[4]} {units_sec_o[3]} {units_sec_o[2]} {units_sec_o[1]} {units_sec_o[0]} {units_hour_o[6]} {units_hour_o[5]} {units_hour_o[4]} {units_hour_o[3]} {units_hour_o[2]} {units_hour_o[1]} {units_hour_o[0]} {units_sec_o[6]} {tens_hour_o[2]} {tens_sec_o[5]} {units_min_o[4]} {units_hour_o[3]} {tens_min_o[3]} {tens_hour_o[6]} {units_sec_o[3]} {tens_sec_o[2]} {units_min_o[1]} {units_hour_o[0]} {tens_min_o[0]} {tens_hour_o[3]} {tens_sec_o[6]} {units_min_o[5]} {units_hour_o[4]} {tens_min_o[4]} {units_sec_o[0]} {units_sec_o[4]} {tens_hour_o[0]} {tens_sec_o[3]} {units_min_o[2]} {units_hour_o[1]} {tens_min_o[1]} {tens_hour_o[4]} {units_min_o[6]} {units_hour_o[5]} {tens_min_o[5]} {units_sec_o[1]} {tens_sec_o[0]} {units_sec_o[5]} {tens_hour_o[1]} {tens_sec_o[4]} {units_min_o[3]} {units_hour_o[2]} {tens_min_o[2]} {tens_hour_o[5]} {units_hour_o[6]} {tens_min_o[6]} {units_sec_o[2]} {tens_sec_o[1]} {units_min_o[0]}"set_output_delay -clock clk -add_delay -max -fall 200000000 "{tens_min_o[6]} {tens_min_o[5]} {tens_min_o[4]} {tens_min_o[3]} {tens_min_o[2]} {tens_min_o[1]} {tens_min_o[0]} {tens_sec_o[6]} {tens_sec_o[5]} {tens_sec_o[4]} {tens_sec_o[3]} {tens_sec_o[2]} {tens_sec_o[1]} {tens_sec_o[0]} {units_min_o[6]} {units_min_o[5]} {units_min_o[4]} {units_min_o[3]} {units_min_o[2]} {units_min_o[1]} {units_min_o[0]} {tens_hour_o[6]} {tens_hour_o[5]} {tens_hour_o[4]} {tens_hour_o[3]} {tens_hour_o[2]} {tens_hour_o[1]} {tens_hour_o[0]} {units_sec_o[6]} {units_sec_o[5]} {units_sec_o[4]} {units_sec_o[3]} {units_sec_o[2]} {units_sec_o[1]} {units_sec_o[0]} {units_hour_o[6]} {units_hour_o[5]} {units_hour_o[4]} {units_hour_o[3]} {units_hour_o[2]} {units_hour_o[1]} {units_hour_o[0]} {units_sec_o[6]} {tens_hour_o[2]} {tens_sec_o[5]} {units_min_o[4]} {units_hour_o[3]} {tens_min_o[3]} {tens_hour_o[6]} {units_sec_o[3]} {tens_sec_o[2]} {units_min_o[1]} {units_hour_o[0]} {tens_min_o[0]} {tens_hour_o[3]} {tens_sec_o[6]} {units_min_o[5]} {units_hour_o[4]} {tens_min_o[4]} {units_sec_o[0]} {units_sec_o[4]} {tens_hour_o[0]} {tens_sec_o[3]} {units_min_o[2]} {units_hour_o[1]} {tens_min_o[1]} {tens_hour_o[4]} {units_min_o[6]} {units_hour_o[5]} {tens_min_o[5]} {units_sec_o[1]} {tens_sec_o[0]} {units_sec_o[5]} {tens_hour_o[1]} {tens_sec_o[4]} {units_min_o[3]} {units_hour_o[2]} {tens_min_o[2]} {tens_hour_o[5]} {units_hour_o[6]} {tens_min_o[6]} {units_sec_o[2]} {tens_sec_o[1]} {units_min_o[0]}"set_output_delay -clock clk -add_delay -min -rise 100000000 "{tens_min_o[6]} {tens_min_o[5]} {tens_min_o[4]} {tens_min_o[3]} {tens_min_o[2]} {tens_min_o[1]} {tens_min_o[0]} {tens_sec_o[6]} {tens_sec_o[5]} {tens_sec_o[4]} {tens_sec_o[3]} {tens_sec_o[2]} {tens_sec_o[1]} {tens_sec_o[0]} {units_min_o[6]} {units_min_o[5]} {units_min_o[4]} {units_min_o[3]} {units_min_o[2]} {units_min_o[1]} {units_min_o[0]} {tens_hour_o[6]} {tens_hour_o[5]} {tens_hour_o[4]} {tens_hour_o[3]} {tens_hour_o[2]} {tens_hour_o[1]} {tens_hour_o[0]} {units_sec_o[6]} {units_sec_o[5]} {units_sec_o[4]} {units_sec_o[3]} {units_sec_o[2]} {units_sec_o[1]} {units_sec_o[0]} {units_hour_o[6]} {units_hour_o[5]} {units_hour_o[4]} {units_hour_o[3]} {units_hour_o[2]} {units_hour_o[1]} {units_hour_o[0]} {units_sec_o[6]} {tens_hour_o[2]} {tens_sec_o[5]} {units_min_o[4]} {units_hour_o[3]} {tens_min_o[3]} {tens_hour_o[6]} {units_sec_o[3]} {tens_sec_o[2]} {units_min_o[1]} {units_hour_o[0]} {tens_min_o[0]} {tens_hour_o[3]} {tens_sec_o[6]} {units_min_o[5]} {units_hour_o[4]} {tens_min_o[4]} {units_sec_o[0]} {units_sec_o[4]} {tens_hour_o[0]} {tens_sec_o[3]} {units_min_o[2]} {units_hour_o[1]} {tens_min_o[1]} {tens_hour_o[4]} {units_min_o[6]} {units_hour_o[5]} {tens_min_o[5]} {units_sec_o[1]} {tens_sec_o[0]} {units_sec_o[5]} {tens_hour_o[1]} {tens_sec_o[4]} {units_min_o[3]} {units_hour_o[2]} {tens_min_o[2]} {tens_hour_o[5]} {units_hour_o[6]} {tens_min_o[6]} {units_sec_o[2]} {tens_sec_o[1]} {units_min_o[0]}"set_output_delay -clock clk -add_delay -min -fall 100000000 "{tens_min_o[6]} {tens_min_o[5]} {tens_min_o[4]} {tens_min_o[3]} {tens_min_o[2]} {tens_min_o[1]} {tens_min_o[0]} {tens_sec_o[6]} {tens_sec_o[5]} {tens_sec_o[4]} {tens_sec_o[3]} {tens_sec_o[2]} {tens_sec_o[1]} {tens_sec_o[0]} {units_min_o[6]} {units_min_o[5]} {units_min_o[4]} {units_min_o[3]} {units_min_o[2]} {units_min_o[1]} {units_min_o[0]} {tens_hour_o[6]} {tens_hour_o[5]} {tens_hour_o[4]} {tens_hour_o[3]} {tens_hour_o[2]} {tens_hour_o[1]} {tens_hour_o[0]} {units_sec_o[6]} {units_sec_o[5]} {units_sec_o[4]} {units_sec_o[3]} {units_sec_o[2]} {units_sec_o[1]} {units_sec_o[0]} {units_hour_o[6]} {units_hour_o[5]} {units_hour_o[4]} {units_hour_o[3]} {units_hour_o[2]} {units_hour_o[1]} {units_hour_o[0]} {units_sec_o[6]} {tens_hour_o[2]} {tens_sec_o[5]} {units_min_o[4]} {units_hour_o[3]} {tens_min_o[3]} {tens_hour_o[6]} {units_sec_o[3]} {tens_sec_o[2]} {units_min_o[1]} {units_hour_o[0]} {tens_min_o[0]} {tens_hour_o[3]} {tens_sec_o[6]} {units_min_o[5]} {units_hour_o[4]} {tens_min_o[4]} {units_sec_o[0]} {units_sec_o[4]} {tens_hour_o[0]} {tens_sec_o[3]} {units_min_o[2]} {units_hour_o[1]} {tens_min_o[1]} {tens_hour_o[4]} {units_min_o[6]} {units_hour_o[5]} {tens_min_o[5]} {units_sec_o[1]} {tens_sec_o[0]} {units_sec_o[5]} {tens_hour_o[1]} {tens_sec_o[4]} {units_min_o[3]} {units_hour_o[2]} {tens_min_o[2]} {tens_hour_o[5]} {units_hour_o[6]} {tens_min_o[6]} {units_sec_o[2]} {tens_sec_o[1]} {units_min_o[0]}"set_operating_conditions -library tcbn45gsbwpbc BCCOMchange_selection set_wire_load_model -name TSMC512K_Lowk_Aggresive -library tcbn45gsbwpbcset all_in_ex_clk [remove_from_collection [all_inputs] [get_ports clk]]set_driving_cell -no_design_rule -lib_cell INVD0BWP $all_in_ex_clkset MAX_INPUT_LOAD [expr [load_of tcbn45gsbwpbc/AN2D0BWP/A1] * 10]set_max_capacitance $MAX_INPUT_LOAD $all_in_ex_clkset_load [expr $MAX_INPUT_LOAD * 3] [all_outputs]set_max_area 1000compile -exact_map -ungroup_allcompile_ultrauplevel #0 { report_timing -path full -delay max -nworst 1 -max_paths 1 -significant_digits 2 -sort_by group }uplevel #0 { report_timing -path full -delay min -nworst 1 -max_paths 1 -significant_digits 2 -sort_by group }uplevel #0 { report_constraint -significant_digits 2 }uplevel #0 { report_power -analysis_effort low }uplevel #0 { report_resources }write -hierarchy -format verilog -output /home/lab/VLSI10/dc/top_netlist.vwrite -hierarchy -format ddc -output /home/lab/VLSI10/dc/top.ddcwrite_sdf top.sdfwrite_sdc top.sdcset_svf -off

6.4 VCS_Kim tra sau khi tng hp To th mc after_syn trong th mc vcs Sau khi tng hp bng cng c Design Compiler s sinh ra mt file Netlist c ui m rng l .v bao gm cc cell c bn c ni dy vi nhau v file delay c ui m rng l .sdf. kim tra timming sau khi tng hp cn c 4 file cn thit l: file netlist .v file delay .sdf file th vin cell tcbn45gsbwp.v file testbench .vCh : cc file .v u phi chn dng `timescale 1ns/1ps. Cc file kia cn phi copy vo trong th mc after_syn. Vo terminal g cc lnh sau :vlogan -debug +v2k *.vvcs -debug tn file module ca testbench -sdf typ:tn modue top:file.sdf l comp.logV d: vcs -debug digital_clock_tb -sdf typ:digital_clock_top:top.sdf -l comp.log Sau khi phn tch cc file trn trong th mc, s to ra file simv. Vo terminal g lnh sau: ./simv gui Ri lm tng t nh cc bc trc khi trc khi tng hp.

Hnh 35 Kt qu m phng VCS sau DC C th thy mch vn p ng c yu cu v chc nng nh ban u. Cc im mu vng trong wave form l do m phng c cha tham s v thi gian gy ra tr, dn ti chuyn trng thi khng ng thi trn cc ng tn hiu.6.5 FormalityTo th mc fm trong project. thc hin phn mm cn co cac file sau: File theo doi top.svf Cc file code RTL *.v File Netlist top.v Bc 1: M terminal g lnh hin th giao din ngi dng fm_shell gui

Hnh 36 Khi ng formality Bc 2: Chn Guidance chn ng dn n file top.svf chn Load Files

Hnh 37 Load file *.svf Bc 3: Chn Reference c tt c cac file verilog tr file testbench Chn Load File

Hnh 38 Load cc file trc khi tng hp Vo mc 3 chn Set Top Design chn file top module Set top Set reference

Hnh 39 Set top Bc 4 : Chn Implementation Chn Verilog chn ng dn m file top.v sau khi tng hp trong th mc dc. Chn Load File.

Hnh 40 Load file sau khi tng hp Chn Read DB Libraries : chn file tcbn45gsbwpbc.db trong th vin Milkyway chn Load Files

Hnh 41 Chn th vin tng hp Chn file top module Set top Set Implementation.

Hnh 42 Set top cho file .v sau tng hp Bc 5: Match Chn Run Matching s c ca s thng bo c bao nhiu im so snh ging nhau v bao nhiu im so snh khc nhau.

Hnh 43 Run Matching Bc 6 : Verify Chn Verify : Trn ca s bo Verify Succeeded tc la kim tra thnh cng. Trong mc Debug s hin ra cac im so sanh gia 2 file code RTL va file netlist.

Hnh 44 Verify6.6 Primetime trc khi layoutM phng mch tng hp logic bng vcs ch cho ta bit thit k sau khi tng hp logic c tha mn cc yu cu chc nng hay khng, m khng m bo thit k khng vi phm cc tiu chun v thi gian. m bo iu ny, thit k ca chng ta phi c kim tra bng phn mm prime time trong b phn mm synopsys, prime time s kim tra li thi gian tt cc cc path c th ca thit k. Bc 1 : Ci t th vin To th mc pt trong project Vo th mc pt m ca s lnh g lnh:pt_shell Ci t Search Path:set lib_path "/home/lab/Desktop/milkyway/tcbn45gsbwp_120a/frame_only_HVH_0d5_0/tcbn45gsbwp/LM";set ADDITIONAL_SEARCH_PATH "$lib_path";set TARGET_LIBRARY_FILES "tcbn45gsbwpbc.db";set_app_var search_path "$search_path $ADDITIONAL_SEARCH_PATH";set_app_var target_library $TARGET_LIBRARY_FILES;set_app_var link_library "* $target_library";

Bc 2 : c file .ddc c file .ddc s dng cu lnh sau:read_ddc ../dc/top.ddc

Hnh 45 Khi ng PrimeTime M giao din ngi dng dng lnh : start_gui Bc 3: Xut bo co Xut bo co Coverage.txt:Vo timing Analysis Coverage Lu file bo co t tn file l coverage.txtReport CoverageReport : analysis_coverage-check_type {setup hold recovery removal min_period min_pulse_width clock_separation max_skew clock_gating_setup clock_gating_hold out_setup out_hold nochange}Design : DongHoSoVersion: D-2010.06-SP3-4Date : Wed Jun 3 18:25:36 2015****************************************

Type of Check Total Met Violated Untested--------------------------------------------------------------------------------setup 20 7 ( 35%) 0 ( 0%) 13 ( 65%)hold 20 7 ( 35%) 0 ( 0%) 13 ( 65%)recovery 20 7 ( 35%) 0 ( 0%) 13 ( 65%)removal 20 7 ( 35%) 0 ( 0%) 13 ( 65%)min_pulse_width 160 28 ( 18%) 0 ( 0%) 132 ( 83%)out_setup 42 42 (100%) 0 ( 0%) 0 ( 0%)out_hold 42 42 (100%) 0 ( 0%) 0 ( 0%)--------------------------------------------------------------------------------All Checks 324 140 ( 43%) 0 ( 0%) 184 ( 57%)

Nh vy, tt c cc path(324 path) ca thit k u c kim tra v khng c path no gp phi cc li v thi gian. Tin hnh thit lp ng h v tr u vo nh thc hin vi bc tng hp bng cc lnh c ly t file command.log xut ra trong bc tng hpcreate_clock -name "clk" -period 1000000000 -waveform { 0 500000000 } { clk } set_input_delay -clock clk -add_delay -max -rise 200000000 "rst en" set_input_delay -clock clk -add_delay -max -fall 200000000 "rst en" set_input_delay -clock clk -add_delay -min -rise 100000000 "rst en" set_input_delay -clock clk -add_delay -min -fall 100000000 "rst en" set_output_delay -clock clk -add_delay -max -rise 200000000 "." set_output_delay -clock clk -add_delay -max -fall 200000000 "." set_output_delay -clock clk -add_delay -min -rise 100000000 "." set_output_delay -clock clk -add_delay -min -fall 100000000 "."

Hnh 46 Thit lp constraint Xut bo co trn ti a :Vo Timing Report Timing Lu tn file l rpt_timing_max.txt

Hnh 47 Export Report Timing maxdelayReport Timing maxdelay ----------------------------------------------------------------------------- data required time 800000000.000 data arrival time -200000000.325 --------------------------------------------------------------- slack (MET) 600000000.000

Xut bo co tr ti thiu:Report Timing Edit Trong th mc Data type chn min Lu tn file l mindelay.txt

Hnh 48 Export Report Timing mindelayReport Timing mindelay -------------------------------------------------------------------------- data required time 0.011 data arrival time -0.075 ------------------------------------------------------------------------------ slack (MET) 0.065

6.7 IC CompilerPhn IC Complier l phn mm c chc nng layout to ra IC da vo file nestlist (.ddc), (.sdc) v cc th vin vt l (milkyway techfile). Quy trnh thit k ca IC Complier c biu din nh sau :

Bc 1: Ci t d liu M ca s giao din ngi dung bng cch g lnh sau:icc_shell gui

Hnh 49 Khi ng ICC Ci t th vinFile Setup Application SetupThc hin tng t nh bc ci t th vin trong Design Compiler

Hn 50 Ci t th vin To th vin milkywayFile Creat Library

Hnh 51 To th vin C cc thit lp sau: New library path: Chn ng dn n th mc minh cn cha th vin New library name : t tn th vin V d :my_lib Technology Files: Chn ng dn n file th vin cong ngh trong Milkyway/home/lab/Desktop/milkyway/tcbn45gsbwp_120a/techfiles/HVH_0d5_0/tsmcn45_10lm7X2ZRDL.tf Trong mc input reference libraries Chn Add chn n th vin tcnbn45gspwb/home/lab/Desktop/milkyway/tcbn45gsbwp_120a/frame_only_HVH_0d5_0/tcbn45gsbwp Chn Open library. Chn OK. c File top.ddcFile Import Read DDC

Hnh 52 c file *.DDC c file top.sdcFile SDC l file rng buc thit k. No c a vao rang buc thit k sao cho thit k ca mnh ti u nht.File Import Read SDC

Hnh 53 c file *.SDC Sau khi c file top.sdc, chn Window New layout window , s xut hin ca s giao din hin th cc cell c xp chng ln nhau.

Hnh 54 Cc cell ca IC cha sp xp

To TLU+File Set TLU+

Hnh 55 Xt th vin TLU+C cc thit lp sau: Max TLU+ file : Chn n th vin cng ngh theo ng dn sau:/home/lab/Desktop/milkyway/tcbn45gsbwp_120a/techfiles/tluplus/cln45gs_1p10m+alrdl_rcbest_top2.tluplus Min TLU+ file : Chn n th vin cong ngh theo ng dn sau:/home/lab/Desktop/milkyway/tcbn45gsbwp_120a/techfiles/tluplus/cln45gs_1p10m+alrdl_rcworst_top2.tluplus Layer name : Chn n th vin cong ngh theo ng dn sau:/home/lab/Desktop/milkyway/tcbn45gsbwp_120atechfiles/tluplus/star.map_10M Lu : Trong th vin c nhiu la chn khc nhau ng vi s lp metal khc nhau. kim tra th vin s dng cc lnh sau :check_librarycheck_tlu_plus_fileslist_libs Ngoi ra c th xut cc bo co kim tra xem trong qu trnh layout gp phi vn g thng qua cc lnh sau:check_timingreport_timing_requirementsreport_disable_timingreport_case_analysisreport_clockreport_clock skew Trong khi tng hp, cc cng c xt mc l tng nn khi layout cn phi xa c tnh ny, s dng cu lnh:remove_ideal_network [get_ports] Sau khi ci t xong d liu, cn lu li bc ny c th d dng xem li cc thit lp ca mnh, s dng cu lnh sau:save_mw_cel -as data_setupHoc vao File Save Design. Bc 2: Floor Planning Thc hin khi to nnFloorplan Initialize Floorplan

Hnh 56 Khi to nnSau khi khi to nn s c hnh nh sau:

Thc hin to chn ni ngun v ni t VDD v VSSPreRoute Derive PG Conection

Hnh 57 VDD v VSS To cc vng dy VDD v VSSPreroute Creat ring Net(chn VDD)

Hnh 58 Chn lp cho VDD Tip theo chn VSS

Hnh 59 Chn lp cho VSS Sau khi to c cc vng dy VDD v VSS trn hnh s xut hin nh sau:

Hnh 60 Sau khi to VDD v VSS Thit lp rng cho day ngun dy t cho tng lp kim loi:Preroute Creat power strap VDD:

Hnh 61 rng VDD VSS:

Hnh 62 rng VSS To vng m:Preroute Creat Pad ring

Hnh 63 To vng m Sau khi xong bc Floor Planning ta cn lu li s dng cu lnhsave_mw_cel -as floorplanned Bc 3: Placement (sp xp cell) v kim tra tc nghn Placement Core Placement and Optimization

Hnh 64 Sp xp cellSau khi sp xp cc cell xong ta c:

kim tra tc nghn xut bo co sau:report_congestion -grc_based -by_layer -routing_stage global Lu li qu trnh thc hin Placement:save_mw_cel -as placed Bc 4: To clock treeClock Tree Synthesis l cng c dng ti u ng tn hiu clock phn phi cho cc mch dy trong thit k. Khi khng c Clock Tree Synthesis th trong thit k s xut hin nh sau:

Khi thc hin xong Clock Tree Synthesis, phn b tn hiu clock s nh sau:

thc hin Clock Tree Synthesis, chn Clock Core CTS and Optimization

Hnh 65 Clock tree Sau khi to c clock tree:

Hnh 66 Kt qu clock tree Lu li bc to clock tree save_mw_cel -as ctsed Bc 5: Thc hin i dy Route Core Routing and Optimization

Hnh 67 RoutingLu li kt qu sau khi i dy t ng save_mw_cel -as routed Route Extract RC

Hnh 68 Extract RC Kt qu sau ICC:

Bc 6: Xut cc file .sdc, .sdf, .v, .spef,..v bo coTo th mc rpt trong th mc icc cha cc file report Xut cc file .sdc, .sdf, .v, ...write_sdf icc.sdfwrite_sdc icc.sdcwrite -format ddc -hierarchy -modified -output {icc.ddc}write_verilog icc.v Xut ra cc file bo co vo th mc rptreport_qor > rpt_icc_qor.txtreport_area > rpt_icc_area.txtreport_constraint -all_violators > rpt_icc_constraint.txtreport_port > rpt_icc_port.txtreport_power > rpt_icc_power.txtreport_timing > rpt_icc_timing.txtreport_timing -nosplit > rpt_icc_timing_nosplit.txtreport_timing -delay min > rpt_icc_timing_delay_min.txtreport_design -physical > rpt_icc_design_physical.txt6.8 VCS_ Kim tra sau khi layout To th mc after_icc trong vcs. Trong qa trnh Layout c th lm sai timing v vy sau khi layout xong cn phi kim tra li timing xem c ng nh timming mnh kim tra sau khi tng hp hay khng. kim tra timming bc ny cn c cc file sau: file .v c to ra sau khi layout file delay .sdf c to ra sau khi layout file th vin cell tcbn45gsbwp.v file testbench .v Thc hin cc bc tng t nh khi kim tra chc nng trc khi tng hp.

Hnh 69 Kt qu m phng VCS sau ICC

6.9 PT_Kim tra sau khi layout S dng file .ddc c to ra sau khi chy ICC. Cc bc thc hin tng t nh trc khi layout. PT sau ICC Report : analysis_coverage -check_type {setup hold recovery removal min_period min_pulse_width clock_separation max_skew clock_gating_setup clock_gating_hold out_setup out_hold nochange}Design : DongHoSoVersion: D-2010.06-SP3-4Date : Wed Jun 3 22:28:49 2015**************************************** Type of Check Total Met Violated Untested--------------------------------------------------------------------------------setup 20 7 ( 35%) 0 ( 0%) 13 ( 65%)hold 20 7 ( 35%) 0 ( 0%) 13 ( 65%)recovery 20 7 ( 35%) 0 ( 0%) 13 ( 65%)removal 20 7 ( 35%) 0 ( 0%) 13 ( 65%)min_pulse_width 160 28 ( 18%) 0 ( 0%) 132 ( 83%)out_setup 42 42 (100%) 0 ( 0%) 0 ( 0%)out_hold 42 42 (100%) 0 ( 0%) 0 ( 0%)--------------------------------------------------------------------------------All Checks 324 140 ( 43%) 0 ( 0%) 184 ( 57%)

***** End Of Report *****

Report timing max sau ICC ------------------------------------------------------------------------ data required time 999999999.989 data arrival time -200000000.169------------------------------------------------------------------------- slack (MET) 800000000.000

Report timing min sau ICC ------------------------------------------------------------------------- data required time 0.008 data arrival time -0.063 ------------------------------------------------------------------------ slack (MET) 0.065

TNG KT

Trong qu trnh thc hin phn bi tp ln trn nhm : Tham kho mt s ti liu nh: Slide bi ging VLSI ca TS Nguyn V Thng, slide bi ging verilog ca TS Nguyn Hong Dng, SPEC hng dn bi tp ln ca thy Nguyn Nam Phong, , gio trnh Thc hnh Thit k h thng s v IC s ca H Bch Khoa H Ch Minh. Thun li: c s h tr tn tnh chu o ca cc thy Nguyn V Thng, Nguyn Nam Phong. S h tr ca cc anh kha trn tng nghin cu v s dng synopsys v cc bn tham gia kha hc phn cng. Kh khn: Ln u lm quen vi phn mm mi, yu cu cao v cc chun nn trong qu trnh chy code cha th sa c li: Dng min_clock_w ti u ra ca counter second lm u vo clk cho khi counter minute, tng t vi hour_clock_w. Th nghim phng n B: Phn m phng chy th trn leda c cht chnh sa v code vt qua li v t lut ca leda.Chng em xin cm n!8