54
WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 0 RFIC 2014 WSK: 60GHz WiGig Frequency Synthesizer Using Injection Locked Oscillator Kenichi Okada Tokyo Institute of Technology

WSK: 60GHz WiGig Frequency Synthesizer Using … Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 0 RFIC 2014 WSK: 60GHz

Embed Size (px)

Citation preview

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 0

RFIC 2014

WSK: 60GHz WiGig Frequency Synthesizer

Using Injection Locked Oscillator

Kenichi Okada

Tokyo Institute of Technology

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 1

RFIC 2014

Outline

• Motivation

• Phase Noise Requirement

for IEEE802.11ad/WiGig

• 60GHz Synthesizer Design

• 60GHz Transceiver

• Conclusion

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 2

RFIC 2014

Worldwide Frequency Allocation

9GHz-BW for IEEE802.11ad/WiGig

Frequency [GHz]

57 58 59 60 61 62 63 64 65 66

America, Canada

Europe

Japan

Australia

60GHz unlicensed band

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 3

RFIC 2014

60GHz-Band Capability

QPSK 3.52Gbps/ch

16QAM 7.04Gbps/ch

64QAM 10.56Gbps/ch

57 58 59 60 61 62 63 64 65 66

Channel

Number

Low Freq.

(GHz)

Center Freq.

(GHz)

High Freq.

(GHz)

Nyquist BW

(GHz)

Roll-Off

Factor

A1 57.24 58.32 59.40 1.76 0.25

A2 59.40 60.48 61.56 1.76 0.25

A3 61.56 62.64 63.72 1.76 0.25

A4 63.72 64.80 65.88 1.76 0.25

Channel

Number

Low Freq.

(GHz)

Center Freq.

(GHz)

High Freq.

(GHz)

Nyquist BW

(GHz)

Roll-Off

Factor

A1 57.24 58.32 59.40 1.76 0.25

A2 59.40 60.48 61.56 1.76 0.25

A3 61.56 62.64 63.72 1.76 0.25

A4 63.72 64.80 65.88 1.76 0.25

1 2 4

240

MHz

120

MHz

1.76 GHz2.16 GHz

3

fGHz

from IEEE802.11ad/WiGig

from Clause 21.3.1 (p.443) & Annex E (p.539) in 802.11ad-2012.pdf

56.16GHz + 2.16GHz x (1, 2, 3, 4)

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 4

RFIC 2014

Outline

• Motivation

• Phase Noise Requirement

for IEEE802.11ad/WiGig

• 60GHz Synthesizer Design

• 60GHz Transceiver

• Conclusion

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 5

RFIC 2014

Required CNR for BER < 10-3

1e-6

1e-5

1e-4

1e-3

1e-2

1e-1

1e+0

0 5 10 15 20 25 30

QPSK

9.8dB

16QAM

16.5dB64QAM

22.5dB

CNR [dB]

BE

R𝐒𝐲𝐬𝐭𝐞𝐦 𝐒𝐍𝐑 = (𝐓𝐗 𝐒𝐍𝐑)𝟐+(𝐑𝐗 𝐒𝐍𝐑)𝟐

+3dB is required.

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 6

RFIC 2014

802.11ad TX EVM Requirement

MCS ModulationData rate

[Mb/s]

TX EVM

[dB] (spec)

9 p/2-QPSK SC 2502.5 -15

12 p/2-16QAM SC 4620 -21

17 QPSK OFDM 2079.00 -13

21 16QAM OFDM 4504.50 -20

24 64QAM OFDM 6756.75 -26SC: single carrierfrom Table 21-18, 21-21 (p.472, 477) & Table 21-14, 21-16 (p.461, 469) in 802.11ad-2012.pdf

-TX EVM=TX SNR(MER)

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 7

RFIC 2014

60GHz Transceiver Challenge

TX

AM-AM, AM-PM: -30dB (EVM-vs-Pout)

phase noise: -30dB

I/Q mismatch: <-40dB

gain/phase flatness: <-40dB

RX

NF, IIP3: <-40dB (depending on Pin)

phase noise: -30dB

I/Q mismatch: <-40dB

gain/phase flatness: <-40dB (depending on DBB)

EVM degradation (TX EVM <-26dB for 64QAM)

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 8

RFIC 2014

Phase Noise Issue at mmW

• Phase noise degrades EVM.

• Phase noise becomes larger at millimeter-

wave for both in-band and out-of-band of

PLL.

ℒ𝐨𝐮𝐭−𝐨𝐟−𝐛𝐚𝐧𝐝 ∝𝒇𝐨𝐬𝐜

𝒇𝐨𝐟𝐟𝐬𝐞𝐭

𝟐e.g.

5GHz 60GHz

+21.6dB increase=20log10(60GHz/5GHz) ℒ𝐢𝐧−𝐛𝐚𝐧𝐝 ∝

𝒇𝐨𝐬𝐜

𝒇𝐫𝐞𝐟

𝟐

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 9

RFIC 2014

-160

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+081kHz 1MHz1Hz

Offset frequency [Hz]

Ph

as

e n

ois

e [

dB

c/H

z]

Phase Noise Degradation

5GHz

=125 x 40MHz

60GHz

=1500 x 40MHz

=20log10(60/5)

+21.6dB

+21.6dB

We cannot avoid this situation.

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 10

RFIC 2014

Influence on EVM

• Phase noise influence on EVM can be

estimated by the following equations.

• Integrated DSB phase noise 𝝋𝐑𝐌𝐒𝟐 is

sometimes integrated from 10kHz to

40MHz due to measurement issue.

correct?

𝝋𝐑𝐌𝐒𝟐 = 𝟐 𝟎

𝑩/𝟐ℒ 𝒇 𝒅𝒇 ≅ 𝟐 𝟎

∞ℒ 𝒇 𝒅𝒇

𝑻𝑿 𝑬𝑽𝑴 =𝟏

𝑺𝑵𝑹𝟐+𝝋𝐑𝐌𝐒

𝟐

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 11

RFIC 2014

-160

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+081kHz 1MHz1Hz

Offset frequency [Hz]

Ph

as

e n

ois

e [

dB

c/H

z]

Phase Noise for 802.11ac

𝝋𝐑𝐌𝐒𝟐 =-33.2dBPLL

𝝋𝐑𝐌𝐒𝟐 =-34.6dB

(10kHz-40MHz)

@5GHz

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 12

RFIC 2014

-160

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+081kHz 1MHz1Hz

Offset frequency [Hz]

Ph

as

e n

ois

e [

dB

c/H

z]

Phase Noise for 802.11ad

𝝋𝐑𝐌𝐒𝟐 =-11.5dBPLL

𝝋𝐑𝐌𝐒𝟐 =-12.9dB

(10kHz-40MHz)

@60GHz

+21.6dB

This seems capable of up to QPSK?

-95dBc/Hz@1MHz

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 13

RFIC 2014

Carrier Tracking at Digital Baseband

-160

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

1Hz 1kHz 1MHz

Offset frequency [Hz]

Ph

ase n

ois

e [

dB

c/H

z]

-160

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

1Hz 1kHz 1MHz

Offset frequency [Hz]

Ph

as

e n

ois

e [

dB

c/H

z] after demodulationbefore demodulation

ftrack=1kHz

A decision-directed PLL used for symbol-

timing recovery can cancel low-offset phase

noise, which is 2nd-order LPF at ftrack.

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 14

RFIC 2014

IEEE802.11ac standard (OFDM)

Modulation Code

rate

NBPSC NCBPS NDBPS Data rate

[Mbps]

QPSK 3/4 2 936 702 195

16-QAM 3/4 4 1872 1404 390

64-QAM 5/6 6 2808 2340 650

256-QAM 5/6 8 3744 3120 866.67

Subcarrier frequency spacing: 0.3125MHz (=160MHz/512)# of data subcarriers=468 (in 501 with 156.5625MHz-BW)

TDFT: OFDM IDFT/DFT period (=3.2us)

TGI: Guard Interval duration (=0.4us = TDFT/8)

R: code rate

NBPSC:# coded bits per single carrier

NCBPS:# coded bits per symbol (=468*NBPSC)

NDBPS:# data bits per symbol (=NCBPS*R)

Data rate = NDBPS/(TDFT+TGI) = 0.3125MHz*NDBPS*TDFT/(TDFT+TGI)

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 15

RFIC 2014

IEEE802.11ad standard (OFDM)

MCS Modulat

ion

Code

rate

NBPSC NCBPS NDBPS Data rate

[Mbps]

17 QPSK 3/4 2 672 504 2079.00

21 16-QAM 13/16 4 1344 1092 4504.50

24 64-QAM 13/16 6 2016 1638 6756.75

from Table 21-4 (p.446) & Table 21-14 (p.462) in 802.11ad-2012.pdf

Subcarrier frequency spacing: 5.15625MHz# of data subcarriers=336 (in 355 with 1830.5MHz-BW)

TDFT: OFDM IDFT/DFT period (=0.194us)

TGI: Guard Interval duration (=48.4ns = TDFT/4)

R: code rate

NBPSC:# coded bits per single carrier

NCBPS:# coded bits per symbol (=336*NBPSC)

NDBPS:# data bits per symbol (=NCBPS*R)

Data rate = NDBPS/(TDFT+TGI) = 5.15625MHz*NDBPS*TDFT/(TDFT+TGI)

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 16

RFIC 2014

Maximum ftrack?

𝑺𝐭𝐫𝐚𝐜𝐤(𝒇) =𝟏

𝟏 +𝒇

𝒇𝐭𝐫𝐚𝐜𝐤

𝟒

𝒇𝐭𝐫𝐚𝐜𝐤 =𝒇

𝟏𝑺𝐭𝐫𝐚𝐜𝐤(𝒇)

− 𝟏

𝟏𝟒

For a rough estimation, assume

𝒇 = 1/2 x subcarrier spacing

𝑺𝐭𝐫𝐚𝐜𝐤 𝒇 = 𝟏𝟎−𝟑 (=-30dB)

802.11ac

𝒇𝐭𝐫𝐚𝐜𝐤 < 𝟑𝟏𝟐. 𝟓𝐤𝐇𝐳 × 𝟎. 𝟎𝟖𝟗 = 𝟐𝟕. 𝟖𝐤𝐇𝐳

802.11ad

𝒇𝐭𝐫𝐚𝐜𝐤 < 𝟓𝟏𝟓𝟔. 𝟐𝟓𝐤𝐇𝐳 × 𝟎. 𝟎𝟖𝟗 = 𝟒𝟓𝟖. 𝟔𝐤𝐇𝐳

J. R. Pelliccio, et al., APPLIED MICROWAVE & WIRELESS, 2001

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 17

RFIC 2014

-160

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08

Phase Noise for 802.11ac

1kHz 1MHz1Hz

Offset frequency [Hz]

Ph

as

e n

ois

e [

dB

c/H

z]

ftrack=0.1kHz

𝝋𝐑𝐌𝐒𝟐 =-33.2dB

ftrack=10kHz

𝝋𝐑𝐌𝐒𝟐 =-34.8dB

𝝋𝐑𝐌𝐒𝟐 = -33.2dB

PLL@5GHz

ftrack=1kHz

𝝋𝐑𝐌𝐒𝟐 =-33.4dB

𝝋𝐑𝐌𝐒𝟐 =-34.6dB

(10kHz-40MHz)

good estimation

𝒇𝐭𝐫𝐚𝐜𝐤 < 𝟐𝟕. 𝟖𝐤𝐇𝐳

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 18

RFIC 2014

-160

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

-40

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 1.E+08

Phase Noise for 802.11ad

1kHz 1MHz1Hz

Offset frequency [Hz]

Ph

as

e n

ois

e [

dB

c/H

z]

ftrack=400kHz

𝝋𝐑𝐌𝐒𝟐 =-27.7dB

𝝋𝐑𝐌𝐒𝟐 =-11.5dB ftrack=10kHz

𝝋𝐑𝐌𝐒𝟐 =-13.2dB

ftrack=100kHz

𝝋𝐑𝐌𝐒𝟐 =-21.7dB

PLL @60GHz

𝒇𝐭𝐫𝐚𝐜𝐤 < 𝟒𝟓𝟖. 𝟔𝐤𝐇𝐳

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 19

RFIC 2014

Effective Integrated Phase Noise

𝝋𝐑𝐌𝐒,𝐞𝐟𝐟𝟐 = 𝟐

𝟎

𝑩/𝟐

ℒ 𝒇 𝟏 −𝟏

𝟏 +𝒇

𝒇𝐭𝐫𝐚𝐜𝐤

𝟒𝒅𝒇

𝑻𝑿 𝑬𝑽𝑴 =𝟏

𝑺𝑵𝑹𝟐+𝝋𝐑𝐌𝐒,𝐞𝐟𝐟

𝟐

𝑩 : bandwidth of modulated signal

(𝑩 can be infinity for approximation)

𝒇𝐭𝐫𝐚𝐜𝐤: tracking bandwidth of symbol timing recovery

(𝒇𝐭𝐫𝐚𝐜𝐤 < 𝟒𝟓𝟔. 𝟖𝐤𝐇𝐳 for IEEE802.11ad OFDM)

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 20

RFIC 2014

0

1

2

3

4

5

-100 -98 -96 -94 -92 -90 -88 -86 -84

AM-AM of PA

16QAM

8PSK

QPSKD R

eq

uir

ed

CN

R [

dB

]

Phase noise [dBc/Hz] @ 1MHz offset

Cross Effect

*K. Okada, et al., JSSC 2011

-90dBc/Hz@1MHz

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 21

RFIC 2014

Phase Noise Requirement

Requirement for IEEE802.11ad/WiGig

QPSK: -83dBc/Hz@1MHz (-15.7dB)

16QAM: -90dBc/Hz@1MHz (-22.7dB)

64QAM: -96dBc/Hz@1MHz (-28.7dB)

with ftrack=400kHz & 2.7dB margin

In-band phase noise is not important, but

the supply-pushing has to be cared for a

TDD operation.

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 22

RFIC 2014

Outline

• Motivation

• Phase Noise Requirement

for IEEE802.11ad/WiGig

• 60GHz Synthesizer Design

• 60GHz Transceiver

• Conclusion

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 23

RFIC 2014

60GHz LO Considerations

2ch-bond

4ch-bond

f [GHz]58.32 60.48 62.64 64.8059.40 63.7261.56

Ch.1 Ch.2 Ch.3 Ch.4

• -96dBc/Hz@1MHz for 64QAM

• 7 carrier frequencies for channel bonding from

58.32GHz to 64.80GHz (10.5%)

• 40-MHz reference clock for sharing other WiFi

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 24

RFIC 2014Oscillation Frequency

Qc < 10 @ 60GHz

60-GHz fundamental oscillation is not a good idea.

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 25

RFIC 2014Frequency Multiplier

12GHz

4x

48GHz

RFIF

*S. Emami, et al., ISSCC 2011

2x

30GHz

90o

hybrid0

o

90o

60GHz**C. Marcu, et al., ISSCC 2009

20GHz

0o, 180

o

90o, 270

o

60GHz ***W. Chan, et al., ISSCC 2008

(1)

(2)

(3)

• for hetero-dyne TRX

• reasonable for PN and FTR

• 60GHz QILO***

• good for PN and FTR

• 30GHz is a bit high

for PN and FTR

• I/Q phase calibration

is required.(20GHz x3, 15GHz x4 are OK.)

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 26

RFIC 2014Quadrature ILO

Gmi

Gmc

Gmc

Qosc20GHz

PLL

60GHz QILO

QILO: Quadrature Injection-Locked Oscillator*

Iosc

**K. Okada, et al., ISSCC 2011Single-side injection**

*W. Chan, et al., ISSCC 2008working as a frequency tripler

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 27

RFIC 2014

60GHz Quadrature LO Design

36/40MHz ref.

PFD CP LPF

20GHz PLL

4 (54,55,56,57

58,59,60)

2

5

4.5

60GHz QILO

58.32GHz

59.40GHz

60.48GHz

61.56GHz

62.64GHz

63.72GHz

64.80GHz

*K. Okada, et al., ISSCC 2014

• 20GHz PLL: 64mW

• 60GHz QILO: 18mW(TX)&15mW(RX)

• QILO frequency range: 58-66GHz

• Phase noise improvement by injection locking

• -96.5dBc/Hz @ 1MHz at 61.56GHz

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 28

RFIC 2014Quadrature ILO

20GHz

20GHz

*W. Chan, et al., ISSCC 2008 **A. Musa, et al., JSSC 2011 ***K. Okada, et al., ISSCC 2011, 2012

VDD VDD

Q-

Q+I+

I-

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 29

RFIC 201420GHz VCO

Tail feedback TEG VCO achieves -107dBc/Hz@1MHz

0

*K. Okada, et al., JSSC 2011

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 30

RFIC 2014Comparison of 60GHz LO

Ref.REF

Freq.

(MHz)

Frequency

(GHz)

Phase Noise

@1MHzFeatures

Power

(mW)

[1] 100 57.0-66.0 -75dBc/Hz Direct 60GHz QPLL 78

[2] 203.2 59.6-64.0 -92dBc/Hz 30GHz PLL + hybrid 76

[3] 100 56.4-63.4 -90dBc/Hz 60GHz AD-PLL 48

[4] 36 58.1-65.0 -96dBc/HzSub-harmonic Injection

20GHz PLL + 60GHz QILO72

[5] 36/40 58-66 -97dBc/HzSub-harmonic Injection

20GHz PLL + 60GHz QILO79

[6] 36/40 58.3-65.4 -95dBc/HzSub-harmonic Injection

20GHz PLL + 60GHz QILO33

[1] K. Scheir, et al., ISSCC 2009 [2] C. Marcu, et al., JSSC 2009 [3] W. Wu, et al., ISSCC 2013

[4] W. Deng, et al., JSSC 2013 [5] K. Okada, et al., ISSCC 2014 [6] T. Siriburanon, et al., RFIC

2014

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 31

RFIC 2014

Outline

• 60GHz Synthesizer Design

• 20GHz-to-5GHz ILFD

• QILO as a phase shifter

• Sub-sampling PLL

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 32

RFIC 2014

20GHz-to-5GHz ILFD (/4)

2fo @ 0o

2fo @ 270o

Icore Icore Icore Icore

0o

180o

90o

270o

135o

315o

2fo @ 90o

2fo @ 180o

225o

45o

+INJ

-INJ

5GHz

10GHz

20GHz

Progressive-mixing ILFD*,**

*A. Musa, et al., A-SSCC 2011 **T. Siriburanon, et al., ESSCIRC 2013

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 33

RFIC 2014

Divide-by-4 Operation

Locked State of Divide-by-4 operation

2n

d H

arm

on

ic

Ou

tpu

tO

utp

ut

Sig

na

l4

th H

arm

on

ic

Ou

tpu

t5GHz

10GHz

20GHz

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 34

RFIC 2014

Divide-by-4 Dividers

FeaturesLocking Range

(GHz)

Power

(mW)

Area

(mm2)

[1] Direct mixing 22.6-28 (21%) 8.3 0.140

[2] Direct mixing 31.0-41.0 (27%) 3.3 0.002

[3]LC Direct

mixing58.5-72.9 (22%) 2.2 0.032

[4] CML + LC ILFD 13.5-30.5 (77%) 7.3 0.33

[5]Progressive

mixing 13.4-21.3 (31%) 3.9 0.003

[6]Progressive

mixing 15.2-20.4 (24%) 3.1 0.002

[1] A-SSCC 2007 [2] ISSCC 2006 [3] CICC 2012 [4] T-MTT 2011

[5] A. Musa, et al., A-SSCC 2011 [6] T. Siriburanon, et al., ESSCIRC 2013

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 35

RFIC 2014

Outline

• 60GHz Synthesizer Design

• 20GHz-to-5GHz ILFD

• QILO as a phase shifter

• Sub-sampling PLL

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 36

RFIC 2014

PPF

Quadrature ILO

I Q

20GHz

60GHz

PPF:polyphase filter*W. Chan, et al., ISSCC 2008

Dq

20GHz

60GHz

I Q

3Dq

Previous work* This work**

I/Q mismatch Single-side injection

- This can be used as a

very fine phase shifter.**K. Okada, et al., ISSCC 2012

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 37

RFIC 2014

Phasor Analysis

I/Q phase difference can be controlled by Zi and Zq.

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 38

RFIC 2014I/Q Phase Shift

QILO can be used as a very-fine phase shifter.

∆𝝓=𝐬𝐢𝐧−𝟏 𝟐𝑸𝐈𝝎𝟎𝐈−𝝎𝐢𝐧𝐣_𝐏𝐋𝐋(𝟐𝟎𝐆𝐇𝐳)

𝝎𝟎𝐈

𝑰𝐨𝐬𝐜_𝐈

𝑰𝐢𝐧𝐣_𝐈(𝟔𝟎𝐆𝐇𝐳 𝐐)+𝜶𝑰𝐢𝐧𝐣_𝐏𝐋𝐋(𝟐𝟎𝐆𝐇𝐳)

−𝐬𝐢𝐧−𝟏 𝟐𝑸𝐐𝝎𝟎𝐐−𝝎𝐢𝐧𝐣_𝐏𝐋𝐋(𝟐𝟎𝐆𝐇𝐳)

𝝎𝟎𝐐

𝑰𝐨𝐬𝐜_𝐐

𝑰𝐢𝐧𝐣_𝐐(𝟔𝟎𝐆𝐇𝐳 𝐈)

Gmi

Gmc

Gmc

Iosc.

Qosc.

20GHz

PLL

Quadrature ILO

𝑰𝐨𝐬𝐜_𝐈

𝑰𝐨𝐬𝐜_𝐐

𝑰𝐢𝐧𝐣_𝐏𝐋𝐋

𝑰𝐢𝐧𝐣_𝐈𝑰𝐢𝐧𝐣_𝐐

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 39

RFIC 2014Phase Resolution

0

5

10

15

20

25

30

58.32 58.52 58.72 58.92 59.12 59.32

Frequency[GHz]

BeforeAfter

Ph

as

e e

rro

r [d

eg

]

0.1 degree/code (estimated) can be realized.

0

10

20

30

40

50

60

0 200 400 600 800 1000 1200

IRR

[d

B]

DAC code of QILO

I/Q gain cal.: RF VGA

I/Q phase cal. : QILO with 10-bit DAC

*S. Kawai, et al., RFIC 2013

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 40

RFIC 2014

Outline

• 60GHz Synthesizer Design

• 20GHz-to-5GHz ILFD

• QILO as a phase shifter

• Sub-sampling PLL

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 41

RFIC 2014

mmW Sub-Sampling PLL

36MHz ref.

40MHz ref.

PFD

with DZ CP2

LPF

4 (54,55,56,57

58,59,60)

2

5

4.5

CP1SSPD

Pulser Core loop

Frequency

lock loop

20GHz

*T. Siriburanon, et al., RFIC 2014 **V. Szortyka, et al., ISSCC 2014

Improvement of in-band phase noise

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 42

RFIC 2014

Phase Noise of SS-PLL

-140

-120

-100

-80

-60

-40

-20

10K 100K 1M 10M

Ph

ase

No

ise

(d

Bc/H

z)

Offset Frequency (Hz)

60GHz (normal operation)

60GHz (subsamplingoperation)

20GHz (subsamplingoperation)

9.5dB

@62.64GHz

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 43

RFIC 2014

Phase Noise Comparison

Ref. REF Freq. (MHz)

Frequency(GHz)

Integrated Jitter (ps)

Phase Noise @10kHz

offset

Phase Noise @10MHz

offsetFeatures Power

(mW)

[1] 100 57.0-66.0 1.5 -66 dBc/Hz -108 dBc/Hz Direct 60GHz QPLL 78

[2] 203.2 59.6-64.0 2.3 -65 dBc/Hz -112 dBc/Hz 30GHz PLL + Coupler 76

[3] 100 56.0-62.0 0.94 -71 dBc/Hz -109 dBc/Hz 60GHz AD-PLL 48

This [6](normal) 36/40 58.3-65.4 12.0 -40 dBc/Hz -115 dBc/Hz

Sub-harmonic Injection

20GHz PLL + 60GHz QILO32.8

This [6] (SS) 36 58.3-65.4 2.1 -69 dBc/Hz -115 dBc/Hz

Sub-harmonic Injection

20GHz SS-PLL + 60GHz

QILO

34.2

[1] K. Scheir, et al., ISSCC 2009 [2] C. Marcu, et al., JSSC 2009 [3] W. Wu, et al., ISSCC 2013

[4] W. Deng, et al., JSSC 2013 [5] K. Okada, et al., ISSCC 2014 [6] T. Siriburanon, et al., RFIC

2014

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 44

RFIC 2014

Outline

• Motivation

• Phase Noise Requirement

for IEEE802.11ad/WiGig

• 60GHz Synthesizer Design

• 60GHz Transceiver

• Conclusion

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 45

RFIC 2014

PA

60GHz

QILO

LNA

LO buf.

LO buf.60GHz

QILO

20GHz

PLL

TX Output

Control

Logic

I Q

I Q

Transceiver Block Diagram

RX Input

*K. Okada, et al., ISSCC 2014

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 46

RFIC 2014

64QAM & 28Gbps 16QAM

64QAM with 10.56Gb/s is achieved for the full 4 channels.

Channel ch.1

58.32GHz ch.2

60.48GHz ch.3

62.64GHz ch.4

64.80GHz ch.1-ch.4

bond

Modula- tion

64QAM 16QAM

Data rate 10.56Gb/s 10.56Gb/s 10.56Gb/s 10.56Gb/s 28.16Gb/s

Conste- llation

Spec- trum

TX EVM -27.1dB -27.5dB -28.0dB -28.8dB -20.0dB

TX-to-RX EVM

-24.6dB -23.9dB -24.4dB -26.3dB -17.2dB

-50

-40

-30

-20

-10

0

55.82 58.32 60.82

-50

-40

-30

-20

-10

0

57.98 60.48 62.98

-50

-40

-30

-20

-10

0

60.14 62.64 65.14

-50

-40

-30

-20

-10

0

62.30 64.80 67.30

-50

-40

-30

-20

-10

0

55.56 58.56 61.56 64.56 67.56

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 47

RFIC 2014

Measurement for IEEE802.11ad/WiGig

MCS ModulationData rate

[Mb/s]

TX EVM [dB]

Spec. Meas.

9 QPSK SC 2502.5 -15 -27.1

12 16QAM SC 4620 -21 -27.0

24 64QAM OFDM 6756.75 -26 -26.5

MCS9 MCS12 MCS24

Measured by

Agilent AWG

+ Osc. + VSA

+ 81199A

in ch.3

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 48

RFIC 2014Conclusion

• Phase noise requirement for IEEE802.11ad/WiGig

QPSK: -83dBc/Hz@1MHz

16QAM: -90dBc/Hz@1MHz

64QAM: -96dBc/Hz@1MHz

• <20GHz oscillation with a frequency multiplier

for good phase noise and wide frequency tuning

(58.32-64.80GHz)

• The quadrature injection-locked oscillator can

be used as a frequency tripler and phase shifter.

• A 64QAM transceiver is demonstrated.

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 49

RFIC 2014Acknowledgement

This work was partially supported by MIC,

SCOPE, MEXT, STARC, and VDEC in

collaboration with Cadence Design

Systems, Inc., and Agilent Technologies

Japan, Ltd.

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 50

RFIC 2014References

[1] K. Okada, et al., “A 64-QAM 60GHz CMOS Transceiver with 4-Channel Bonding,” IEEE

ISSCC, pp. 346-347, Feb. 2014.

[2] K. Okada, et al., “A Full 4-Channel 6.3Gb/s 60GHz Direct-Conversion Transceiver with

Low-Power Analog and Digital Baseband Circuitry,” IEEE ISSCC, pp. 218-219, Feb.

2012.

[3] K. Okada, et al., “Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver with Low-

Power Analog and Digital Baseband Circuitry,” IEEE JSSC, Vol. 48, No. 1, pp.46-65,

Jan. 2013.

[4] K. Okada, et al., “A 60GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver

for IEEE 802.15.3c,” IEEE ISSCC, pp. 160-161, Feb. 2011.

[5] K. Okada, et al., “A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver

for IEEE802.15.3c,” IEEE JSSC, Vol. 46, No. 12, pp. 2988-3004, Dec. 2011.

[6] A. Musa, et al., “A Low Phase Noise Quadrature Injection Locked Frequency

Synthesizer for MM-Wave Applications,” IEEE JSSC, Vol. 46, No. 11, pp. 2635-2649,

Nov. 2011.

[7] W. Deng, et al., “A Sub-harmonic Injection-locked Quadrature Frequency Synthesizer

with Frequency Calibration Scheme for Millimeter-wave TDD Transceivers,” IEEE

JSSC, Vol. 48, No. 7, pp. 1710-1720, July 2013.

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 51

RFIC 2014References

[8] S. Kawai, et al., “A Digitally-Calibrated 20Gb/s 60GHz Direct-Conversion Transceiver in

65-nm CMOS,” IEEE RFIC Symposium, pp.137-140, June 2013.

[9] K. Okada, et al., “Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver with Low-

Power Analog and Digital Baseband Circuitry,” IEEE JSSC, Vol. 48, No. 1, pp.46-65,

Jan. 2013.

[10] T. Siriburanon , et al., “A 60-GHz Sub-Sampling Frequency Synthesizer Using Sub-

Harmonic Injection-Locked Quadrature Oscillators,” IEEE RFIC Symposium, June

2014.

[11] T. Siriburanon, et al., “A 13.2% Locking-Range Divide-by-6, 3.1mW, ILFD Using Even-

Harmonic-Enhanced Direct Injection Technique for Millimeter-Wave PLLs,” IEEE

ESSCIRC, pp.403-406, Sep. 2013.

[12] J. R. Pelliccio, H. Bachmann and B. W. Myers, “Phase Noise Effects on OFDM

Wireless LAN Performance,” APPLIED MICROWAVE & WIRELESS, pp.68-80, 2001.

[13] F. M. Gardner, “Interpolation in digital modems Part I: Fundamentals,” IEEE Trans.

Communications, vol. 41, no. 3, pp. 501–507, Mar. 1993.

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 52

RFIC 2014

Digital Carrier and Timing Recovery

RXADC

ADC

TX

DAC

DAC

LPF

LPF

VGA

VGA

LPF

LPF

Analog Digital

RX

filter

TX

filter

Carrier

& Timing

Recovery

Dem

ap

per

FE

C

Deco

der

Map

pe

r

FE

C

En

co

der

WSK: Frequency synthesis for 60-GHz and beyond: architectures and building blocks RFIC2014, Tampa Bay, 1-3 June, 2014 53

RFIC 2014

Digital Carrier and Timing Recovery

NCO: Number-Controlled OscillatorLF: Loop FilterPD: Phase Detector

timing recovery (phase)

timing-recoveredsignal

PDLFNCO

carrier recovery (freq.)

rotationfilter

PDLFNCO

interpolationfilter

timing- & carrier-recovered signal

ADC

Cancel in-band phase noise at < ftrack