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数字接口的发送端测试方案介绍

泰克科技（中国）有限公司张晓

[email protected]

Agenda

Tektronix Solutions Overview

HDMI

MHL

USB3.0

PCIE

SATA/SAS

Thunderbolt/DisplayPort

Tektronix Optical Solutions Overview

11/1/2012 数字接口的发送端测试方案 2

5 & 8

Gb/s

5.4 Gb/s

9.6 Gb/s

6 Gb/s

3 Gb/s

5 Gb/s Multi-

cores 9.6

Gb/s

Tektronix DPO/DSA/MSO70000 Analysis Tools Available

• SAS 12G/6G/3G

• SFP+/10G KR

• SATA 6G/3G/1.5G

• PCIe Gen3/2/1

• DDR/DDR2/DDR3/LPDDR/LPDDR2/GDDR3/GDDR5

• 10M/100M/1000M/10G Base-T

• MIPI D-Phy

• MIPI M-Phy

• HDMI/MHL

• DisplayPort

• QPI

• USB 3.0/2.0/1.1

• Thunderbolt

WiMedia

CAN/LIN protocol

I2C, SPI, RS-232/422/485/UART,

USB 2.0, and MIPI® decode

8b/10b decode

64b/66b decode

Coherent Lightwave(DP-QPSK/PM-QPSK)

Optical OFDM

Communication MASK

Power

DVI

Satellite Communication

Radar

11/1/2012 3 数字接口的发送端测试方案

DPOJET业内测试内容最丰富的抖动和眼图测试工具

• 测试内容丰富多样，包括抖动、眼图和各种时序测量

• 支持各种测试标准、抖动分析模型 – Tektronix专利的抖动分析模型

– Dual Dirac抖动分析模型(PCIE2.0规范使用)

– 标准定义模板以及用户自定义模板

• 最多可同时测试99个项目


DPOJET业内分析能力最强大的抖动测试工具

• 多域分析抖动

– 抖动直方图

– 抖动频谱图

– 时间趋势图

• 提供Tektronix专利的抖动分离方法，帮助工程师定位故障

– 抖动频域分离方法，业内公认的抖动分离方法

• 丰富多样的时钟恢复方法，满足各种应用的需求

– Golden PLL

– TypeI/II PLL loop BW 用户可自定义

– 外部时钟

• 眼图测量帮助定位隐藏在串行数据中“有嫌疑”的bit


HDMI TX solution


HDMI – 设备类型

7 11/1/2012

Plug Plug Receptacle

Tx

Receptacle

Rx

Sink Devices

• TVs, Monitors,

Repeaters, etc.

Source Devices

• Mobile Phone,Set-top

Boxes, DVDs, Repeaters,

Gaming devices

Cable Assemblies

• Cables

数字接口的发送端测试方案

HDMI1.3的原理框图


HDMI1.4的原理框图

11/1/2012 9

HEAC通道是1.4规范新增的功能


HDMI ATC的采用情况

目前全球有12个ATC Lab,有至少7个ATC lab正在采用泰克的HDMI

1.3/1.4 solution进行认证测试。分别是NXP France, Sony-

Tokyo(2),Panasonic-Osaka, Sony-Taiwan, Sony -Shenzhen, Philips-

India(其中HDCP Lab只进行HDCP认证，不涉及到物理层和协议层的认证)。同时在终端客户群中泰克的市场分额占据60% 以上.


HDMI Source Testing

11/1/2012 11

Source Sink Cable

– Rise/Fall Time

– Inter-pair Skew

– Clock Duty Cycle

– Clock Jitter

– Eye Diagram

– Voltage VL

– Intra-pair Skew

Differential

Single-ended


Typical Source Test Configuration

Differential Measurements using Tektronix Oscilloscope

11/1/2012 12

EFF – HDMI –TPA - P

P7313SMA

Or EDID board

03.30

ET – HDMI –TPA - P

Tektronix system supports simultaneous

differential path acquisition

Requires fixture for Source DUT access


Typical Source Test Configuration

Single-ended Measurements using Tektronix Oscilloscope

11/1/2012 13

03.30

P7313SMA

Or EDID board

ET – HDMI –TPA - P

Terminate unused fixture connectors with 50 ohms after pulling them to 3.3V using Bias-Tees

Tektronix DPO/DSA70000B Oscilloscope

performs 2 Channel Single-Ended

measurements

Requires fixture for Source DUT access


HDMI TMDS Test Fixture

11/1/2012 14

TPA-R


高速串行信号的一致性测试的要求

Harmonic

11/1/2012 15

1st 3rd 5th

HDMI 1.3/1.4实际最高Data Rate=2.97Gbps,

HDMI 1.2实际最高Data Rate=1.485Gbps

• 对于HDMI 2.97Gbps,由于其是非归零码，基频为

2.97/2=1.485GHz,5次谐波为1.485*5=7.425GHz

规范推荐使用8Ghz示波器进行测试。

• 对于HDMI 1.485Gbps,5次谐波为3.7GHz

• 规范推荐使用4Ghz示波器进行测试。

•对于其他的分辨率，可以根据数据速率的预估

• 选择适当的示波器进行测试。

Frequency

dB


MHL TX solution


Tektronix is a contributor adopter for MHL CTS

11/1/2012 17

Welcome MHL Adopters

BizLink Technologies, Inc.

www.bizlinktech.com

Cable Assemblies and Wiring Harnesses

Compal Electronics Inc.

www.compal.com

Electronics manufacturer of notebook computers and monitors

Explore Microelectronics, Inc.

http://www.epmi.com.tw

Fabless company developing high-speed interface ICs

Fairchild Semiconductor

www.fairchildsemi.com

Delivers semiconductor solutions for power and mobile designs

Hosiden Corporation

www.hosiden.com

Manufactures and sells electronic components, electromechanical parts and LCD

elements

Johnson Component and Equipment Co., Ltd.

www.jcecable.com

Cable Manufacturer

Niketech Electronic Corporation

www.niketech.com.tw

Provider of connectors for the electronics industry

Parade Technologies, Inc.

www.paradetech.com

Develops and supplies advanced and cost-effective high-speed display interface

solutions

Sumitomo Electric Industries, Ltd.

global-sei.com

Designs, manufactures and sells cable and components and advanced electronic

devices

Sunplus Technology Co., Ltd.

www.sunplus.com

Provider of multimedia IC solutions

Sure-Fire Electrical Corporation

www.sure-fire.com.tw

Global OEM/ODM supplier of cables, connectors and devices

Synopsys

www.synopsys.com

Provider of electronic design automation (EDA) software, IP and services

Tektronix

www.tek.com

Test, measurement and monitoring solutions

YFC-BonEagle Electric Co., Ltd.

www.cables.com.tw

Manufactures power cord sets, LAN cable, patch cords and networking

accessories


http://www.bizlinktech.com/

http://www.compal.com/

http://www.epmi.com.tw/

http://www.fairchildsemi.com/

http://www.hosiden.com/

http://www.jcecable.com/

http://www.niketech.com.tw/

http://www.paradetech.com/

http://global-sei.com/



http://www.sunplus.com/

http://www.sure-fire.com.tw/



http://www.synopsys.com/home.aspx

http://www.tek.com/

http://www.cables.com.tw/

MHL Introduction

11/1/2012 18

Mobile HD Link (MHL) technology is a low pin count HD audio and video

interface that connects portable electronics devices such as mobile phones,

digital cameras, camcorders and portable media players, to HDTVs.

The technology allows mobile devices to output digital 1080 Full HD

resolution via the existing mobile connector without the real estate

and cost of another dedicated video connector.

Together with an MHL-to-HDMI bridge, the MHL-enabled mobile device

becomes a fully compliant HDMI source and can connect to the television’s

standard HDMI input port.


Difference between HDMI and MHL

11/1/2012 19

HDMI

– Four lanes

– One differential clock lane

– Three differential TMDS

data lanes

– DDC

– Max. 3.4GHz data rate/per lane

@ 340MHz clock

– HDMI connector

– Max. resolution 4096 x 2160p24

– Not support PackedPixel mode

– For home multimedia

– CTS 1.4

MHL

– Only one lane

– One differential TMDS data

lane

– Clock is embedded

– C-Bus

– Max. 2.225GHz data rate @

74.25MHz clock

– Compatible with uUSB

– Max. resolution 1920 x 1080i60

1080p in packedpixel mode

– Support PackedPixel mode

– For mobile device

– CTS 1.1 (June 2011)


MHL Signal Complexity

11/1/2012 20

MHL Consortium was formed in Sept

2009 with the following founding

members: - NOKIA

- SAMSUNG

- Silicon Image

- Sony

- Toshiba

The Specification 1.1 version was

announced in Q12011 and

Specification 1.2 in Feb 2012.

The Consortium released CTS 1.1

version in June 2011. CTS 1.2 is just

announced.

COMPLETE TEKTRONIX SOLUTION

APPROVED in CTS1.1 and CTS 1.2.

Tektronix is a Contributor adopter and

actively involved in defining the CTS.


Announcing Tektronix MHL Solution

11/1/2012 21

DPO/DSA/MSO 70804B/C Series Real Time Oscilloscope with BW ≥ 8GHz

MHL Compliance Software – Option MHD

Innovative MHL Protocol Software from Third party – TEK-PGY-MHL-PA-SW

Probes – P7313SMA (two) and P7240 (one)

MHL Test Fixture – Available from Tektronix.

AWG7122C with Opt 01,02 or 06 and 08 for the innovative direct Synthesis

based MHL Rx/Dongle testing.

C-Bus Sink and Source board is needed and is available from Simplaylabs

DSA8200 or Equivalent with 80E03/80E04 and I-Connect Software for MHL

cable testing ( performed manually using MOIs)

Please contact local Tektronix account managers for further details.


Tektronix MHL Tx Setup

11/1/2012 22

MHL Differential and CM Test Setup

7 tests Single Ended and Intra Pair Skew Test Setup

3Tests

Also same setup is used for MHL Protocol Testing

** C-Bus Sink and Source Board is needed for hand shaking and is available from Simplay Labs


MHL Compliance Software for Automated Tx Tests: Option MHD


MHL Fixtures :

11/1/2012 24

Wilder P/N Wilder Model # Tektronix nomenclature Description

640-0452-000 MHL-TPA-TT TF-MHL-TPA-TT MHL Termination Board

640-0453-000 MHL-TPA-P-WOSO TF-MHL-TPA-P-WOSO MHL Source Test Board Plug without Termination

640-0454-000 MHL-TPA-R-WOSO TF-MHL-TPA-R-WOSO MHL Dongle Test Board Receptacle without Termination

640-0455-000 MHL-TPA-R-WOC TF-MHL-TPA-R-WOC MHL Cable Test Board Receptacle without Termination

640-0456-000 MHL-TPA-R-WOSI TF-MHL-TPA-R-WOSI MHL Sink Calibration Test Board Receptacle without Termination

640-0457-000 MHL-TPA-P-WOSI TF-MHL-TPA-P-WOSI MHL Sink Test Board Plug without Termination

640-0458-000 MHL-TPA-R-SO-RSEN TF-MHL-TPA-R-SO-RSEN MHL Source RxSense Test Board Receptacle

640-0459-000 MHL-TPA-R-SI-RSEN TF-MHL-TPA-R-SI-RSEN MHL Sink and Dongle RxSense Test Board Receptacle

MHL Fixture KITS

640-0475-000 MHL-TPA-TEK( Complete

MHL Fixture kit) TF-MHL-TPA-TEK( Complete MHL

Fixture kit) MHL Test Kit includes 640-0452-000 thru 640-0459-000

640-0476-000 MHL-TPA-TEK-SO( Source

Fixture Only Kit) TF-MHL-TPA-TEK-SO( Source

Fixture Only Kit) MHL Source Test Kit includes 640-00452 and 640-0453-000

640-0477-000 MHL-TPA-TEK-SI( Sink

Fixture kit) TF-MHL-TPA-TEK-SI( Sink Fixture

kit) MHL Sink Test Kit includes 640-0452-000, 640-0456-000, 640-0457-000

640-0478-000 MHL-TPA-TEK-DG( Dongle

Fixture Kit) TF-MHL-TPA-TEK-DG( Dongle

Fixture Kit) MHL Dongle Test Kit includes 640-0452-000, 640-0453-000, 640-0454-000

640-0479-000 MHL-TPA-TEK-CB( Cable

Fixture Kit) TF-MHL-TPA-TEK-CB( Cable

Fixture Kit) MHL Cable Test Kit includes 640-0455-000, 640-0456-000

640-0480-000 MHL-TPA-TEK-RSEN( RSEN

Kit) TF-MHL-TPA-TEK-RSEN( RSEN

Kit) MHL RxSense Kit includes 640-0458-000 and 640-0459-000


640-0452-000

MHL-TPA-TT

640-0453-000

MHL-TPA-P-WOSO

Tektronix P7313

SMA Differential

Probe

Tektronix P7313

SMA Differential

Probe

Tektronix P7240

Common Mode

Clock

uUSB

Plug

VBus/CBUS

uUSB Receptacle VBus/CBUS

Jumpers

Wilder Fixtures: Tektronix MHL Source Testing Setup


USB3.0 TX solution


USB 行业领导地位

Tektronix 是第一家推出 USB 2.0测试方案的公司

唯一对Wimedia USB物理层测试提供测试步骤方法 (MOI)

数百万被Tektronix测试方案认证过的USB设备

Tektronix 是唯一参与 USB 3.0 规范制定的测试测量仪器公司!


Super Speed USB 和High Speed USB电气层比较

High-Speed

– 480MT/s

– 没有SSC

– 2 个走线做信号传输

– 发射和接收用同一个走线

– 1 双向链接

– 半双工

– 非屏蔽双绞线

– DC 耦合总线

– NRZ 编码

SuperSpeed

– 5.0GT/s (10X 速度递增)

– 有SSC

– 4 个走线做信号传输

– 2个发射2个接收

– 单向链接

– 全双工

– 屏蔽双绞线

– AC 耦合总线

– 8b/10b 编码

11/1/2012 28

Source: USB-IF


USB 3.0 Key Considerations

Receiver testing now required – Jitter tolerance

– SSC, Asynchronous Ref

Clocks can lead to

interoperability issues

Channel considerations – Need to consider

transmission line effects

– Software channel emulation

for early designs

New Challenges – 12” Long Host Channels

– Closed Eye at Rx

– Equalization – De-emphasis at Tx

– Continuous Time Linear

Equalizer (CTLE) at Rx

Test strategy – Cost-effective tools

– Flexible solutions 29

Source: USB 3.0 Rev 1.0 Specification

11/1/2012 数字接口的发送端测试方案

USB 3.0 Compliance Test Configuration

USB 3.0 is a closed eye specification

– Reference channel is embedded and CTLE is applied

USB 3.0 Reference Channels

– Host Reference Channel

– 11” back panel is applied for device testing

– Device Reference Channel

– 5” device channel is applied for host testing

– 3 Meter Reference Cable

– Used for host and device (except captive devices) testing in addition to

reference channels

USB 3.0 Reference Equalizer

– Attenuates the low frequency content of the signal to open the eye

30

Transmit Channel CTLE TP1 TP2


Transmitter Solutions

TekExpress Fully Automated Compliance Environment

DPOJET Debug and Analysis

31 11/1/2012 数字接口的发送端测试方案

USB 3.0 Test Fixtures

Two options for USB 3.0 Test Fixtures

– Tektronix supplied fixtures

– Enables SW channel emulation for TX and RX

testing

– Published electrical specifications

– Supports TX, RX, and Cable testing

– Available from Tektronix

– USB-IF supplied fixtures and cables (shown

below)

– Used for compliance testing

– Enables SW channel emulation for TX only

– Supports TX and RX testing

– Available from the USB-IF


USB 3.0 Transmitter Measurement Overview

Voltage and Timing – Eye Height

– Pk to Pk Differential

Voltage

– RJ

– DJ

– TJ

– Slew Rate

Low Frequency Periodic

Signaling (LFPS) – Pk to Pk Differential

Voltage

– Rise / Fall Time

– AC Common Mode

– tBurst

– tRepeat

– tPeriod

SSC – Modulation Rate

– Deviation 33 11/1/2012 数字接口的发送端测试方案

LFPS TX Measurements

LFPS signaling is critical for establishing link communication

LFPS TX test verify common mode, voltage, tPeriod, tBurst, tRepeat

Channel is not embedded for LFPS tests


SSC Measurements

Both Maximum and Minimum Frequency Deviation must be

considered

– Assume nominal UI of 200ps

– Limits are +0/-4000ppm and +0/-5000ppm, plus +/- 300ppm for ref clock

accuracy

Compliance Channel is not embedded for SSC measurements


USB 3.0 Droop / Drop Test

New Test Fixture Available from USB-IF

– Provides 150mA / 900mA load

– Previous fixture provides 100mA / 500mA load

Amount of power drawn is changed from 500mA to 900mA for high

power devices

Fixture is orderable at:

http://www.usb.org/developers/estoreinfo/USB_product_order_form.p

df


Complete USB 3.0 Transmitter Solution DPO/DSA70000 Series Oscilloscopes

Go Beyond Compliance Testing

– Debug Suite with DPOJET

– SDLA for Channel Modeling

– Tektronix Super Speed USB

Fixtures

Automation software for

characterization and compliance

– TekExpress with option USB-TX

(includes option USB3)

Recommended Scope

– 12.5 GHz Real-Time Scope

– 50GS/s Sample Rate

– P7313SMA Differential Probe

(Optional)

37 TF-USB3-AB-KIT

Opt. USB3

Opt. USB-TX


PCIE TX solution



PCIe 3.0 Timeline as of June 2012 2012

Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec

2010 Jan Feb Mar

0.9 1.0

PCIe3 Base

0.7 0.9 1.0 PCIe3 CEM

0.3 0.5 0.9 1.0

PCIe3 Test

0.7

6 mo FYI

βTesting at workshops

Test procedures posted

IL Ready

27 mo

CBB / CLB requirements understood

CBB / CLB schematics and gerbers ready

First CBB / CLB ready for testing

Sigtest ready for testing CBB / CLB available

for membership (early testing)

Final CBB / CLB available for member purchase

Final Sigtest posted

PCIECV 2.1 release, PCIECV beta release for 3.0

8G platform for PCIECV testing available

Final PCIECV release and source posted

PTC vendors submit proposals

PTC HW and SW ready for beta testing

Final PTC available for member purchase

SW binary and source posted

PTC vendor selection complete

Apr May Jun

2011

Slip

Completed

Milestone

Original

Milestone

Estimated

Milestone

Jul Aug

0.71

Scheduled

CWs

Planned

CWs

Sep Oct Nov Dec Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr

2013

11/1/2012 39

PCIe Physical Layer

Three main components in Physical Layer

– Transmitter : Responsible for converting data from Parallel to Serial and transmitting the data

stream using various encoding schemes

– Channel : Includes Traces / Connectors / Cables / Backplanes between the transmitter and

receiver

– Receiver: responsible for receiving the bits from serial stream and converting them to parallel

Each part of the Physical layer is allocated a performance criteria to meet overall

system performance

Each part of the Physical Layer is tested separately against the set performance criteria

PCIe Base Specification

– Used for Silicon and embedded systems

PCIe CEM Specifications

– Used for Add-In cards

数字接口的发送端测试方案 11/1/2012 40

PCIe 3.0 Transmitter Compliance Testing

Compliance Testing is based on the

Compliance Test Specification which is

under development

New compliance Pattern for Gen3

128b/130b data

Three types of tests

– Electrical: Eye Height/Width

measurement must pass one preset

value

– Preset Test: All preset tests are tested to

be within their limits

– Transmitter Equalization Test: verify that

Transmitter will respond to equalization

change requests

Measurements are taken after the

compliance and Rx equalization

using the compliance base and load

board 11/1/2012 41 数字接口的发送端测试方案

Tx Testing

Tx tests are performed with the Transmitter in

compliance mode against compliance test

spec to assure interoperability.

In compliance mode Transmitter puts out

predefined compliance test patterns designed

to replicate worst case conditions.

Three ways to enter into compliance mode

– Force the link into compliance by

programming Link Control register

– Assert compliance receive bit in Training

sequences

– Send 100 MHz signal for about 1 ms on one

leg of a differential pair at 350mV peak-to-

peak on any Lane

Using 100MHz signal is the most preferred

method to enter into compliance


Compliance Patterns

Once in compliance more, bursts of 100MHz clock can used to cycle through various settings of

compliance patterns to perform, Jitter, voltage, timing measurements.

Data Rate Preshoot De-emphasis

2.5 GT/s, -3.5 dB

5.0 GT/s, -3.5 dB

5.0 GT/s, -6.0 dB

8.0 GT/s, P0 = 0.0 -6.0±1.5dB

8.0 GT/s, P1 = 0.0 -3.5±1.5dB

8.0 GT/s, P2 = 0.0 -4.4±1.5dB

8.0 GT/s, P3 = 0.0 -2.5±1dB

8.0 GT/s, P4 = 0.0 0.0dB

8.0 GT/s, P5 = 1.9±1dB 0.0dB

8.0 GT/s, P6 = 1.9±1dB 0.0dB

8.0 GT/s, P7 = 1.9±1dB -6.0±1.5dB

8.0 GT/s, P8 = 1.9±1dB -3.5±1dB

8.0 GT/s, P9 = 1.9±1dB 0.0dB

8.0 GT/s, P10= 1.9±1dB Test Max Boost

Limit


Test Fixtures (System Board)

Compliance Load Board (CLB)

– Used for testing System Boards

– All Tx / Rx Lanes and Ref Clk routed to SMP

– Compliance Mode Toggle Switch

– Various types of Edge Connectors to support

different types of Slots on System Boards

– Separate CLB’s for Gen1/2/3

Compliance Load Board (CLB)

Ref Clk

Data

System Board / Mother Board with Multiple Slots

CLB

with

toggle

switch


Test Fixture (Add-In Card)

Compliance Base Board (CBB)

– Used for Testing Add-In cards

– All Tx / Rx Lanes are routed SMP

– Compliance Mode Toggle Switch

– Various types of Slot Connectors to support

types of Add-In cards

– Low Jitter Clean Reference Clock

– Separate CBB for Gen 1/2/3

Compliance Base Board (CBB)

CBB with Multiple Slots of different widths and toggle switch

Data

Data

Add-In

Card


Channel must be de-embedded before measurements can be

taken

SDLA for de-embedding

SDNA for acquiring s-parameters

Base Specification Transmitter Measurements

Signal at TX Pins Measured Signal

at TP1

Apply Sparameters Signal with Channel

Effects Removed


Tx Compliance Testing challenges

Checklist of parameters assure interoperability

– Tx Signal Quality Test,

– Tx Preset Test

– Ref Clock Measurments

PCISIG recommends SigTest SW required for Tx compliance

– Analyzes Oscilloscope waveforms

Oscilloscope setup and acquisition required for:

- Multiple slots

- Multiple lanes (x1, x4, x8, x16)

- 1 Gen1, 2 Gen2, and 11 Gen3 Presets

Manually Toggling through 14 presets

Data from dozens of SigTest reports need to be manually analyzed (about 224 acq’s for complete x16 coverage and about 15 for just compliance)


Introducing the NEW! Opt PCE3

TekExpress Automation for Tx

Compliance

– Sets up the Scope and DUT

for testing!

– Toggles thru and verifies the

different Presets and Bit

Rates!

– Tests multiple slots and lanes

– Acquires the Data!

– Processed with SigTest!

– Provides custom reporting!

Single option for both DPOJET

an TekExoress


Automated DUT Control

Ref Clk

Data

System Board / Mother Board with Multiple Slots

CLB

with

toggle

switch

Oscilloscope

AFG

Control

100MHz Burst for toggling


TekExpress Automation for Tx Compliance - Setup

Run Analysis on Live or

Pre-Recorded Data

Type of test / device

selection

Test selection

Automate DUT control


PCI Express Base Specification Measurements

Voltage

Package Loss

Transmitter Equalization

Jitter


Transmitter Equalization Measurements VTX-BOOST-FS / VTX-BOOST-RS

What’s new for Gen 3.0

– De-Emphasis (Va) and pre-shoot (Vc)

– Transmitters must support 11TX equalization pre-sets

The high frequency nature of 8.0 GT/s signaling

makes measurement of single UI pulse heights

impractical due to attenuation by the package and

breakout channel

– Amplitude measurements are taken on low frequency

waveforms (64 ones/ 64 zeros in the compliance

pattern) using last few UI of each half period

– Va and Vc values are obtained by setting the DUT to a

different preset value where the desired Va or Vc

voltage occurs during the Vb interval.


Transmitter Voltage Measurements VTX-EIEOS-FS / VTX-EIEOS-RS

Launch Voltage of Electrical Idle Exit

Ordered Set

Required to ensure that the RX can

properly detect an exit from electrical

idle

Taken on a pattern of eight ones

followed by eight zeros repeated 128

times included in the compliance pattern

– Taken on the middle five UI to reduce

attenuation effects of the channel

VTX-EIEOS-FS - Full Swing Signaling

– Measured by Preset 10

VTX-EIEOS-RS – Reduced Swing

Signaling

– Measured by Preset 1


Package Loss Measurements PS21

Can be taken at TP1 while capturing silicon package loss and drive

characteristics, but due to the high frequency content of the 1010

pattern the measurement must be de-embedded back to the TX pins

Measured by comparing 64 zeros and 64 ones PP voltage against a

1010 pattern

Measured with de-emphasis and pre-shoot set to 0 at the end of

each interval to minimize ISI and low frequency effects


Transmitter Jitter Measurements

Necessary to take transmitter jitter measurements with all lanes

operating in order to capture crosstalk effects

Measurements are taken at TP1 and de-embedded back to the pins of

the TX

Necessary to separate uncorrelated and data dependent jitter in order

to ensure that jitter that can be recovered is not budgeted as

uncorrelated jitter

Jitter

Measurements

Data Dependent

Jitter

Uncorrelated

Jitter

Cause Due to package loss and

reflections (dynamics in

the channel, ISI)

Uncorrelated - PLL jitter,

crosstalk, noise conversion

(amplitude to phase)

How to

Compensate

Can be reduced by

equalization

Difficult to remove (better

components, layout)


Transmitter Jitter Measurements: Data Dependent Jitter TTX-DDJ

DDJ Measurement Process

Measurement taken on multiple repeats of the compliance pattern

using a 1st order CDR function representing a high pass filter

A PDF is created for each edge crossing of the compliance pattern

DDJ is calculated as the difference of the mean of each PDF and the

recovered clock edge

Measurement is defined as the absolute value of DDJ(max) –

DDJ(min)


Uncorrelated Jitter Example TTX-UTJ / TTX-UDJDD

DDJ is removed from the PDF

of each edge

Data is converted to Q-Scale

Uncorrelated Deterministic Jitter

Dual Dirac (UDJDD)

− Accounts for Periodic Jitter and

Crosstalk Convert the PDF to

Q-Scale

Random Jitter is implied by

subtracting UDJDD from UTJ


Uncorrelated Total and Deterministic PWJ TTX-UPW-TJ / TTX-UPW-DJDD

Pulse Width Jitter

– Addresses lone bits that are

attenuated the most in lossy

channel and could likely cause bit

errors

DDJ is removed to accurately

quantify PWJ

Calculate edge-to-edge jitter

Construct Q-scale PDF curve and

Extrapolate to BER = 10-12 (Q=

7.03) to determine Uncorrelated

Pulse Width Jitter (containing F/2 or

Odd/Even Jitter) and Deterministic

Pulse Width Jitter

Final measurements are calculated

by looking at the left hand side of

the PDF curve


Recommended Bandwidth for PCI Express 3.0

Balance instrument bandwidth with application requirements

– Noise increases with bandwidth, too much bandwidth reduces the

accuracy and the margin of your measurements

– PCIe requires the analysis of signals with amplitudes as low as 34mV for

compliance testing

– Ensure enough bandwidth to capture the high frequency content of the

signal

– Need to consider how the channel effects the harmonic content and rise time

of the signal

– De-embedding requires bandwidth limit to reduce the effect of high frequency

noise amplification

– Flexibility for different tasks

– Characterization and debug vs. compliance

Recommended bandwidth

– 16 GHz best balance for PCI Express 3.0 Measurements

– Minimum: 12 GHz


Storage PHY TX solution


Storage Timelines and Solutions Development Today

2008 2009 2010 2011

Gen 3- Silicon Phase

6G Integration Phase

– Product

Development

– SATA IO Unified

Test Definition 1.4

– First official testing of

Gen3 products in

June 2009

Draft Spec

6G Deployment Phase

Public Spec 6G Release

– Commercial

Gen3 product

deployment.

Gen 2- Silicon Phase

6G Integration Phase

Draft Spec

6G Deployment Phase Public Spec

Release

– Commercial

product

deployment. Gen 3 (12Gb/Sec)

- Silicon Phase

– SCSI Trade

Association Gen2

Plugfest (UNH IOL)

– STA test

specification of

SAS released.

2012

IW#9/PF#14 Taipei 11/16

SAS3 first Spec Draft

IW#10/PF#15 Milpitas CA

05/16


2013 2014

IW#13/PF#18 Milpitas CA 10/14


8G SATA-Express Integration Phase

SATA 3.2 First Interop SATA-

Express

8G (Spec 3.2) SATA-Express Deployment Phase

IOL SAS (12) Interop

Integration Phase 12G Deployment Phase


12G+ Design Problem: 1000mV, FFE, Crosstalk, DFE, 50mV

Crosstalk and signal loss problems are the largest design challenge today.

Significant advances in high tap count Decision Feedback Equalization are key to operating at 12G+.


NEW Measurement for Crosstalk/ISI Evaluation

SAS3_EYEOPENING* Measurement for accurate analysis of ISI and

crosstalk effects

Provides measure of relative vertical eye opening after reference

equalization

*Note, this measurement is similar to the SAS-2 Waveform Distortion Penalty (WDP) measurement but also includes Tx

EQ in addition to DFE. The code was provided and distributed through the T10 Technical Committee and permission has

been granted for Tektronix to reuse.

Source: 12-244r3


SAS-3 PHY Transmitter Solution – Option SAS3

Test0 Parameter Conformance Min/Max 5.1.1 Maximum Noise During OOB IDLE < 120 mV

5.1.2 OOB Burst Amplitude > 240 mV

5.1.3 OOB Offset Delta +/- 25 mV

5.1.4 OOB Common Mode Delta +/- 50 mV

5.2.1 SSC Modulation Type Center-, No- and Down-spreading

5.2.2 SSC Modulation Frequency 30 kHz < SSCfreq < 33 kHz

5.2.3 SSC Modulation Deviation +/- 1000 ppm (center), 0 ppm (no spread) or +0/-1000 ppm (down)

5.2.4 SSC DFDT 850 ppm/µs

5.3.1 Physical Link Rate Long Term Stability

+/- 100 ppm

5.3.2 Common Mode RMS Voltage < 30 mV

5.3.3 Common Mode Spectrum Mask Hits

Below Spectrum Limit Lines (0.1 to 6 GHz)

5.3.4 Peak to Peak Voltage 850 mV < Vpk-pk < 1200 mV

5.3.5 VMA > 80 mV

5.3.6 Rise Time > 20.8 ps

5.3.7 Fall Time > 20.8 ps

5.3.8 Random Jitter 0.15 UI (12.5 ps)

5.3.9 Total Jitter 0.25 UI (20.8 ps)

5.3.10 SAS3_EYEOPENING > 55 %

5.3.11 Pre Cursor Equalization 1 V/V < Rpre < 1.67 V/V

5.3.12 Post Cursor Equalization 1 V/V < Rpost < 3.33 V/V

SAS3 12 Gb/s Tx Test Software

Common Mode Spectrum Measurement


SAS Receptacle Test Adapter

Sdd21 (1x Thru) => -3dB@26 GHz


Test Fixture De-embedding

Why de-embed?

– Tx measurements referenced to

die (ET)

– Improve margin with removal of

fixture effects

S-Parameters acquired from

calibration fixture or model

extraction

Use inverse response to

compensate for loss

Before After

Before

De-Embed

After

De-Embed

Eye

Height 711 mV 770 mV

Rise Time 57 37


Bandwidth Considerations SAS PRBS11 12G NRZ Power Spectrum


Recommended Equipment

The following components are required for performing SAS12 Tx

measurements

DSA/DPO/MSO70K(C/D) Series Oscilloscope with Opt. 5XL or higher

(Min. 20 GHz BW, ≥25 GHz recommended*)

DPOJET Advanced (DJA) - Prerequisite

Option SAS3

Test Fixtures:

– TF-SAS-TPA-R SAS Gen3 Receptacle Adapter (drive form factor) or

– TF-SASHD-TPA-R miniSASHD 12G SAS Receptacle (mini SAS HD 4i/x

cables) or

– Set of TF-SASHD-TPAR-P miniSASHD 12G SAS (Right Side) Plug and

TF-SASHD-TPAL-P miniSASHD 12G SAS (Left Side) Plug (x8)

PMCABLE1M or equivalent Phase Matched Cable Set (qty: 2)


Basics of Serial ATA PHY Testing

• Configure

• Calibrate Startup

• Acquire

• Analyze Validate

• Save data

• Scorecard Report


11/1/2012

SATA UTD 1.4 TSG/PHY/OOB Measurements

PHY TRANSMITTED SIGNAL

GROUP REQUIREMENTS (TSG 1-12)

Different test program and

degrees of regression

testing user selectable.

Debug and diagnostic tools

(Informative measurements)

Updated SATA Gen3

measurements New OOB patterns

TSG ECN additions

70 数字接口的发送端测试方案

AWG Device State Control

DUT control a significant challenge

BIST-L (loopback) required for

compliance

AWG has a successful track record of

DUT control

Initiates loopback while seamlessly

transitioning to Tx/Rx testing

3rd party tools available (Drivemaster,

serial port control)

BIST-L

Initiator

Sequence

Stress

Patterns

Diagnostic

Patterns


Embedded Applications SATA BGA

Today, SATA is expanding in specialized low power, compact and high performance areas with BGA and SATA-Express Solutions recently approved by SATA-IO.

The SATA Ecosystem: Now

SATA-Express SSD’s


PCB

PCIe Conn.

PCIe/SATA Conn.

PCB

Accept only a x2

PCIe, or a

x1 PCIe cable

Keys that reject the SATA cables

Accept a x2 PCIe, or a x1 PCIe, or two

SATA cables

Desktop Connector Concept

Enabling the New SATA Express Ecosystem


Desktop Cables Concept

PCIe Cable

Existing SATA Cable

PCIe Cable

PCB

PCB PCIe/SATA Conn.

PCIe Conn.

SATA devices will coexist with next

generation PCIe devices

SATA cost/performance benefits

Requires a connector that supports both

PCIe and SATA

Allows a single motherboard (backplane)

connector to support both interfaces

HDD-compatible form factors to be

defined for PCIe devices

Enables system-level mechanical

compatibility

Preserves high-capacity storage

SATA-IO CabCon has been chartered to develop SATA compatible connectors and form factors for PCIe SSD/hybrid drives

Enabling the New SATA Express Ecosystem


Physical Connections

Source: SATA Express Specification (Technical Proposal)

Note, additional PCIe Ref Clk pins optional 11/1/2012 75 数字接口的发送端测试方案

SATA Express = PCIe PHY Layer

Tx Test parameters

– Voltage

– Package Loss

– Transmitter Equalization

– Jitter

NEW Ref Clock Spec definition

– Independent Ref Clock model

– 2nd Order transfer function for SSC harmonics attenuation


Clocking Architectures – PCIe vs. SATA

SATA

– Supports SSC

– Embedded clock

PCIe

– Three different synchronization methods

– Forwarded Ref clock

– Data clocked Ref clock

– Separate Ref clock

Client PCIe application

-> no need for "refclk“*

Independent Ref clock model for SATA Express * PCI-SIG proposal under review


Tektronix Solutions for SATA Express Measurements

DPOJET-based SATA

Express setup (requires

option PCE3)

Support for Base/CEM

spec measurements

Supports all versions of

PCI Express and

includes SATA Express

PLL configurations


SATA Express Signal Access

Recommend Luxshare-ICT Dual

Port SAS fixtures (SFF-8482)

Similar dimensions but different

pinout

For device testing use plug fixture

(TF-4R21) to mate with SATAe plug

– Both ports accessible (29 pin)

For cable testing use receptacle

fixture (TF-4P22) to mate with

SATAe receptacle

– Only port A is accessible (22 pin)

SAS Dual Port Plug Test Fixture

SAS Dual Port Receptacle Test Fixture

http://www.luxshare-ict.com/


Thunderbolt & DisplayPort TX solution


Thunderbolt Overview High Speed Data Bus for PC’s

– Brought to market by Intel/Apple in 2011

– Interoperable with DisplayPort

Thunderbolt signaling is dual NRZ (64/66b Encoded)

– 10.3125 Gb/s data rate

– It utilizes SFP+ technology with 2 diff Tx and Rx pairs.


Thunderbolt Electrical Validation

Thunderbolt (.5 Spec

Revision)

10.3125Gbps

Tektronix DPOJET

Thunderbolt .5 MOI

Manual Test

}

}

Tektronix DP12

Full test

automation

Display Port DP1.2

RBR (1.6Gbps), HBR (2.7Gbps) HBR2 (5.4Gbps)

Thunderbolt

(future Interop)

DP++

7

7


Dual Port Device Compliance Test Summary

Physical Layer Testing – (Rev 0.7 Spec)

1.TBT Transmitter MOI

2.TBT Receiver MOI

3.TBT Return Loss MOI

4.DP Source MOI

5.DP++ (HDMI) Source MOI

6.Power Delivery MOI

Functional Testing – Thunderbolt Functional CTS

Rev 3.0.1 1. ROM Validation

2. Basic Device Functionality

3. EFI

4. Downstream Device Functionality

5. Downstream Display Functionality

6. Extended Test Functionality

7. Complex Topology

8. DUT Specific Verification

9. Negative Testing

10. Firmware Update Validation

CTS – Compliance Test Specification

MOI – Method of Implementation (Test Procedure)


Single Port Device Compliance Test Summary

Physical Layer Testing – (Rev 0.7 Spec)

1.TBT Transmitter MOI

2.TBT Receiver MOI

3.TBT Return Loss MOI

4.Power Consumption

Functional Testing – Thunderbolt Functional CTS

Rev 2.4 (IBL 488434) 1. ROM Validation

2. Basic Device Functionality

3. EFI

4. DUT Specific Verification

5. Negative Testing

6. Firmware Update Validation

CTS – Compliance Test Specification

MOI – Method of Implementation (Test Procedure)


Power Delivery Testing Setup


HDMI Test Setup

DSA70804C or higher

SMA Differential Probes

– Provides 3.3V bias

HT3 HDMI Compliance SW

Mac or equivalent tool used

to control downstream port

on a 2 port device

Both ports tested


Automated Thunderbolt Tx Testing

Recommended Equipment

• DPO/DSA/MSO71604 (≥ 16 GHz BW)

• BSA125C (crosstalk source)

• Option DJA (DPOJET)

• Option TBT-TX (TekExpress)

• TF-TB-TPA-P (Plug fixture) &

TBT-TPA-UH (port microcontroller)


Option TBT-TX Compliance Automation Software

Automates scope setup & compliance

measurements per the Tek Thunderbolt MOI

Fast test execution

Simultaneous two lane testing

Automated DUT state control for devices

User-selectable tests

Creates complete test report


DEMO


DisplayPort 1.2 Overview

The DisplayPort PHY Compliance

Test Specification establishes a test

regimen to determine compliance of

DisplayPort devices - segmented into: – Source

– Receiver

– Copper Cable

– Hybrid devices

– Tethered devices

90

Test Point Definitions

– TP1: at the pins of the transmitter

device.

– TP2: at the test interface on a test

access fixture

– TP3: at the test interface on a test

access

– TP3_EQ: TP3 with equalizer applied.

– TP4: at the pins of a receiving device


Display ports newest signaling spec operates at 5.4Gbsec (HBR2) and the

version 1.2 CTS outlines 17 Tx validation tests which are typically evaluated

with a 12.5 GHz or higher bandwidth oscilloscope.

Source Test Suite – 1. EYE Diagram

– 2. Non Pre-Emphasis Level Verification

– 3. Pre-Emphasis Level and Post Cursor2

– 4. Inter-pair Skew

– 5. Intra-Pair Skew

– 6. Differential Transition Time

– 7. Single Ended Rise and Fall Time Mismatch

– 8. Overshoot and Undershoot Test

– 9. Frequency Accuracy

– 10. AC Common Mode Noise

– 11. Non ISI Jitter Measurement

– 12. Total Jitter and Random Jitter Measurement

– 13. Unit Interval

– 14. Main Link Frequency Compliance Stability

– 15. Spread Spectrum Modulation Frequency

– 16. Spread Spectrum Deviation

– 17. dF/dt Spread Spectrum Deviation HF Variation

DisplayPort 1.2 Source (Tx) Test Overview

DUT Configuration – 1. Bit Rates: RBR, HBR or HBR2

– 2. Patterns: D10.2,PRBS7, COMP,

PLTPAT,PCTPAT

– 3. FFE (Pre-Emphasis): 0dB, 3.5dB,

6dB, 9.5dB

– 4. Output Levels: 400mV, 600mV,

800mV, 1200mV

– 5. SSC (Spread Spectrum): On/Off

– 6. Post-Curser2: Level 0,1,2,3

– 7. Lane Width, 1,2,4


Eye Diagram Test using Eye Compliance Pattern

An Eye diagram test for 800mV , 0dB pre-emphasis at TP2,TP3, TP3-EQ.


DisplayPort 1.2 CTLE Properties

1.2 CTS requires adaptive application of one of three reference equalizers

to the far end signal, to find a passing condition.


DisplayPort Auxiliary Channel Controller (DP-AUX)

Speeds Up Test Time - No User Interaction is Required to Change Source Output Signal

or Validate Sink Silicon State or Error Count

No Need to Learn Vendor-specific Software - A Single GUI Supports All Vendors

View & Log Decoded AUX Traffic and Hot Plug Detect (HPD) Events from the Device

under Test to the DP-AUX DisplayPort AUX Controller

Ability to Read and Write DPCD Registers Supports Debug Activities

Tektronix DP-AUX can serves as a DP1.2 Sink - Enables source to transmit the required

patterns for testing.

Aux Channel

HPD

94

Why use Aux channel controller in physical layer testing?


Automation: DisplayPort testing is a large task!

Combination Parameters For DP1.2 Testing

Data Rate - 3

Lanes - 4

Pre-Emphasis - 4 Levels

Voltage Swing - 4 Levels

Post Cursor2 - 4 Levels

SSC - 2 Levels(SSC On and Off)

Patterns - 5 Supported Patterns

Combination of Tests

1. Differential Tests

2. Single Ended Tests

Test

Waveforms

(SSC, 4 Lanes Possible Combinations)

Eye Diagram Test 80

Pre-Emphasis Test 240

Non-Pre-Emphasis 32

Total Jitter 80

~432 Acquired signals for DP1.2 Normative Measurements per lane.

X4 lanes results in 1728 Automated Acquisitions per DUT.


TekExpress DisplayPort 1.2 Automation

Comprehensive Display Port Version 1.2 Physical Layer Conformance and Compliance Verification Tool

96

– All Core DP1.2 measurements

– Keithley RF Switch and DP-AUX fully automated solution.

– Selected measurements can be applied across all test permutations (SSC,CTLE’s, swing, rates, pre-emphasis, etc.) translates to 1728 measurements. DP12 will provide full user intervention free, automated testing. This is the killer value proposition.

– Factory Automation API for full product control in silicon automation systems.

– Complimentary Fixtures and Compliance Interconnect Channel HW defined by VESA make this package a full customer solution with no compromises.


Conventional Display Port Fixtures + CIC

Partnership with Wilder Technologies to design and channel high performance

DP fixtures

Wilder TF-DP-TPA-PRC fixtures and CIC and fixtures

available directly from Tektronix


Embedded (eDP) Fixturing

20-Pin eDP Connector for CCFL Backlight (1 or 2 Lane eDP)

30-Pin eDP Connector for LED Backlight w/o LED Driver on PCB (1 or 2 Lane eDP

30-Pin eDP Connector for LED Backlight with LED Driver on PCB (1 or 2 Lane eDP

40-Pin eDP Connector for LED Backlight with LED Driver on PCB (up to 4 Lane eDP)


Tektronix Optical Solution Overview


Introducing the DSA8300 Digital Serial Analyzer More Performance and Versatility


Industry’s best native time-base jitter

performance, 425 fs RMS typical ( <200 fs

RMS when equipped with the 82A04 Phase

Reference module )

16,000 point native record length

300 kSa/s TDR mode maximum sample

rate

16 bits of vertical resolution

Optional fully integrated pattern

synchronization (replaces 80A06)

4X Pattern Sync throughput performance

Clock Pre-scalar maximum input frequency

20 GHz typical

3 GHz Intel Core 2™ Duo CPU

New user interface look and feel leveraging

MS Windows 7 Ultimate Operating System

XVGA (1024 X 768) 10.4 inch display

Supports all 8K Sampling and Accessory * Modules

• Except 80A06 which is replaced with

available fully integrated ADVTRIG option

DSA8300 Digital Serial Analyzer DSA8300 Optical Module Portfolio

Multi-mode, Broad Wavelength (750 - 1650 nm) Modules

80C07B Supports rates to 2.7 Gb/s, high sensitivity, optional integrated clock

recovery

80C08D Supports all of the 8/10 Gb/s applications, high sensitivity, optional

integrated clock recovery, optional Integrated CR

80C12B Supports rates from 155 Mb/s – 11.3 Gb/s, high sensitivity - data

pick-off for external CRU e.g. CR125A

80C14 Supports rates from 8.5 Gb/s – 14.063 Gb/s, high sensitivity – data

pick-off for external CRU e.g. CR175A

Single-mode, Long Wavelength (1100 - 1650nm) Modules

80C11B Optical bandwidth to 30GHz, supports 10Gbit/s up to14G+

standards, optional Integrated CR

80C10C

Optical bandwidth to 80GHz, supports all 25, 40 and 100 Gb/s (4 x

25 Gb/s) standards, optional CR trigger pickoff for e.g. CR286A

CRU


155Mbps to100Gbps Optical Compliance Testing DSA8300 ALL-IN-ONE Solution


The 80C12B Optical Modules provides:

– Support for all major rates from 155 Mb/s

to 12.5 Gb/s

– Low-noise, wide dynamic range

– Excellent optical sensitivity

– Broad wavelength

– Both single and multi-mode support

The DSA8300 ALL-IN-ONE Solution

provides

– Support for all major rates from

155 Mb/s to 44.5 Gb/s

Integrated and calibrated clock

recovery – Tektronix CR286A up to 28.6 Gb/s

– Third party CRU to 44.5 Gb/s

Standard Line Rate 80C12

B

80C10C

Opt F1

OC-3/STM-1 155 Mb/s

OC-12/STM-4 622 Mb/s FC1063 1.0625 Gb/s

ENET1250 1.250 Gb/s

FC2125 2.125 Gb/s

OC48//STM48, GBE, INF2500 2.488 Gb/s

2.500 Gb/s

FEC2.666 2.666 Gb/s

!0GBASE-X4, FC3188 3.125 Gb/s

3.188 Gb/s

FC4250 4.250 Gb/s

INF5000 5.000 Gb/s

OBSAI6144 6.144 Gb/s

CPRI7373 7.373 Gb/s

FC8500*8, OC-192/STM-64, 8GFC,

10GBASE-W, 10GBASE-R,

40GBASE-R4, 100GBASE-R10,

10GFC, FEC10.66, FEC10.71,

FEC11.10, FC11317

8.500, 9.95,10.31,

10.51,10.66,10.71,11.1,

11.3 Gb/s ORR Filters

plus Unfiltered bandwidth

path (typically 12 GHz)

100GBase-LR4, 100GBase-ER4

Infiniband EDR (LW) 4 x 25.781 Gb/s

OTU4 4 x 27.952 Gb/s

40GBase-FR 41.25 Gb/s

OC-768 / STM-256, VSR-2000 39.813 Gb/s

OTU3 (OC-768 + G.709 FEC),

VSR-2000 , 4x10G LAN-PHY (OTU3)

43.018 Gb/s

44.50 Gb/s

Optical SRS Testing (40GBASE-LR4, 100GBASE-LR4, ER4 )

1. CFP Module is used for 40/100GbE

2. Stressed Receiver Sensitivity (SRS)

testing of 40GBASE-LR4 and

100GBASE- ER4/LR4 testing is on four

separate 1300nm WDM channels:

a) 40GBASE-LR4 is at 10.3125Gb/s

b) 100GBASE-LR4, ER4 are both at

25.78125Gb/s

3. Use of 4 channel WDM complicates

testing 2 3 4

1


The Complete BER Analysis Tool 100G PHY Testing BER, Clock Recovery, Jitter and Failure Analysis

CR286A 28.6G Clock Recovery Module Versatile Precision Clock Recovery and

Analysis

Generation Guaranteed 1 to 28.6Gbps

Coverage

Industry-best Jitter Noise Floor

− Rj (Wide-Band) < 300fSec RMS

− DDj < 4pSec

− Tj < 10pSec @ 10e12

Full Clock Management

− Full rate (28.6) stressed clock

− Clock to Data adj skew

(150pSec)

NEW! BSA286C 28.6G Bit Error Rate Analyzer The Confidence of a BERT with the Insight of an

Oscilloscope

Clock Recovery Industry’s only turnkey solution to

28.6Gbps

− No need for mux or 3rd party

Provides accurate “Golden PLL”

Clock Recovery Input Equalization

− Enables clock recovery on high ISI

signal

Error Detection Easy to Operate User

Interface

Industry’s only BERT with

Jitter mapping, SI and

component decomposition


100 GBASE-LR4/ER4 Optical Stressed Eye using Tektronix BERTScope

Measured 25.78125 Gb/s Optical

Stressed Eye for 100 GBASE-

ER4.

1. Jitter Tolerance test performed by introducing

the stressed eye to the DUT, then changing the

SJ amplitudes and frequencies to the

prescribed template, ensuring there are no

errors at each point.

2. Go beyond the required values to assess

design margin.


Recommended Test Equipment for 40GBASE-LR4, 100GBASE-LR4 Testing

ISI for Compliance

DSA8300 Series Sampling Scope

For Tx Eye Diagram

BERTScope CR286A

For Flexible Clock Recovery

BERTScope BSA286C

For Pat Gen and Error Detect


Eye Diagram for Transmitter Test Compliance

100 Gbps Optical Transmitter Test – Datacom / Telecom – Compliance for 25.781 Gb/s 100GBASE-R4 and 27.95243 Gb/s OTU4

40 Gbps Optical Transmitter Test – Datacom – Compliance for 41.25 Gb/s 40GBASE-FR

40 Gbps Optical Transmitter Test – Telecom – Compliance for OC-768 / STM-256 (39.8Gbps)

– Compliance for ITU-T G.709 FEC, 4x10G LAN PHY OTU3 (43.02 Gbps)


40Gb/s and 100Gb/s Optical Communication Details


.

Application Standards Modulation

Formats Bit Rate Physical Medium

40 Gb/s Datacom

(LAN)

IEEE P802.3ba

40GBase-SR4 NRZ 4 x 10.3125 Gb/s

Parallel MMF ribbon cable

(OM3) / 100m reach

40GBase-LR4 NRZ 4 x 10.3125 Gb/s CWDM SMF / 10km

40GBase-LR

(future serial) NRZ 41.25 Gb/s SMF / 10km

100 Gb/s Datacom

100GBase-SR10 NRZ 10 x 10.3125 Gb/s parallel MMF ribbon cable

(OM3)

100GBase-LR4

100GBase-ER4 NRZ 4 x 25.781 Gb/s WDM on SMF

10km, 40km

40 Gb/s Telecom

(Metro, WAN, Long-haul)

ITU-T

OC768 / STM256 / OTU3

G.709

VSR-2000

NRZ, RZ

Duobinary

DPSK

39.813 Gb/s and

43.018 Gb/s (D)WDM SMF

DQPSK 2 x 20 Gb/s (D)WDM SMF

Nortel proprietary

(deployed)

DP-QPSK

(with coherent receiver) 4 x 10 Gb/s DWDM on SMF

Nortel proprietary (future) DP-BPSK (coherent

RX) 2 x 20 Gb/s DWDM SMF (ULH)

100 Gb/s Telecom

OIF (physical medium

layer)

DP-QPSK

(with coherent receiver) Up to 4 x 32Gb/s

DWDM on SMF (ULH)

>1000km reach

ITU-T (higher layers)

OTU-4 not specified

112 Gb/s

(aggregate) DWDM SMF

ADVA proprietary (R&D) DPSK-3ASK 2.5 x 40 Gb/s Metro DWDM

40 - 600km

Other early R&D OFDM, APSK, nQAM SMF

Long Haul Optical Communication

Solution


Complex Modulation Formats


Optical modulation methods


0 1 0 1 1 0

0 1 0 1 1 0

Pure AM (OOK)

Pure PSK

Optical modulation methods cont.

11/1/2012 112

0 1 0 1 1 0

01 11 10 10 11 00

Typical BPSK

Typical QPSK

2-bits/ symbol


Optical modulation methods cont.

11/1/2012 113

01 11 10 10 11 00

01 11 10 10 11 00

DP-QPSK

4-bits/symbol

QPSK

2-bits/ symbol

QPSK

2-bits/ symbol


Dual-polarization QPSK Modulator


Coherent detection

Real-time acquire

and analysis

High sample

rate:100GS/s

11/1/2012 115

LO

optical signal phase/

polarization

diversity

hybrid

(all passive)

photo-

detectors

A/D

converters

RAM

processor display


Complete and open solutions to complex

measurement challenges in long-haul fiber-optic

communications

Advanced dual-polarization in-phase and

quadrature receiver with integrated signal and

reference tunable laser sources

Open-architecture MATLAB-based computational

engine offers powerful phase-recovery analyses

with polarization, bit-error rates, and

record/playback

Intuitive graphical user interface controls

frequently-used instrument functions:

– Laser control

– Modulation schemes

– PRBS or user-generated data

Accessories available to easily verify optical

calibration

OM4106D 33 GHz Coherent Lightwave Signal Analyzer for > 100 Gb/s Analysis


OM4106D support for the DSA8300 Sampling Scope

The OM4106D and the OM1106 software have

been modified to support the DSA8300 sampling

scope.

Any existing OM4106D is capable of supporting

both DSA/DPO70k real-time scopes and the

DSA8300 sampling scopes with a software upgrade.

Using the sampling scope for acquisition provides greater vertical

resolution at a lower total system price compared to real-time

solutions.

– 16 bits vertical resolution and 450uV rms noise floor at 60 GHz provide

added dynamic range and accuracy.

– Up to 60 GHz sampler bandwidth on four channels provides future-proof

capability for next-gen baud rates.

– Timing jitter as low as 450fs RMS lets you see signal jitter.

(as low as 200fs when using the 82A04 Phase Reference Module)

NEW


OFDM基本原理

正交频分复用OFDM（OrthogonalFrequencyDivisionMultiplex)是一种多载波调制方式，

通过减小和消除码间串扰的影响来克服信道的频率选择性衰落。它的基本原理是将信号分割为N个子信号，然后用N个子信号分别调制N个相互正交的子载波。由于子载波的频谱相互重叠，因而可以得到较高的频谱效率。近几年OFDM在无线通信领域得到了广泛的应用。


http://hanyu.iciba.com/hy/%E9%A2%91%E8%B0%B1%E6%95%88%E7%8E%87

Optical OFDM通信

光OFDM(O-OFDM)系统结合OFDM技术与光通信的特点，将OFDM

技术应用于光通信的一种新技术，构建出高速率、高容量、低成本的光传输网络并且具有较强的信道容量的可扩展性，可以在现有网络的基础上很好的升级与过渡，提供高速率、高容量、高质量的通信服务。O-

OFDM技术也可以作为全球微波互联接入(WiMAX)、无线局域网(WLAN)的一部分。

O-OFDM 能够有效地对抗光通信系统中的色度色散和偏振模色散引起的符号间干扰( ISI) , 而且循环前缀( CP) 的引入, 更进一步的增强了O-

OFDM通信系统的抗色散能力, 降低色散管理的复杂度, 同时对提高数据传输率和系统容量起到重要作用。另外,O-OFDM 系统中的各个子信道的不同频谱相互叠加,更有效的利用频谱资源, 提高了带宽利用率。除此之外, 该系统实现简单, 易于优化等优点, 使OFDM技术在光通信领域,

尤其是40Gbit/ s 以上的高速光通信领域具有很好的应用前景。


Optical OFDM通信优点

O-OFDM由于其独特的优势，在全世界范围内得到了深入的研究，在欧洲光通信展览会(OFC)2008、OFC2009和美国光电光纤通信展览会(ECOC)2007、ECOC2008会议上，O-OFDM传输理论与技术成为了会议的热点之一。

O-OFDM系统的优势主要表现在如下几个方面：

– O-OFDM系统在传输过程中不需要复杂的色散管理，这样既能实现高速的

数据传输，降低了网络的复杂度和建设、运行、维护的成本，也能适应动态变化的网络环境

– O-OFDM 系统可以最大限度的利用频谱资源，提高频谱效率

– O-OFDM系统与原有的波分复用(WDM)系统有很好的兼容性，可充分利用WDM系统在光纤链路和光放大器方面的巨大投资，只需要在发射和接收端进行适应性改造即能够完成升级。


泰克光OFDM通信系统测试解决方案

光OFDM通信系统测试系统构建

11/1/2012 121

MZM

CW Laser70 km SSMF

生成宽带OFDM电信号

验证和分析宽带OFDM电信号


泰克光OFDM通信系统完整的系统测试方案

一、超宽带信号源AWG－业内唯一能产生宽带OFDM信号的信号源

– 超高带宽（9.6G），超高采样率（24GS/s）

– 可以直接产生射频，中频，基带信号

– 基于AWG的高级OFDM信号仿真软件RFXpress，方便产生各种复杂的OFDM信号

– 对实际回波信号进行二次“改造” ：如加“噪声”加“干扰”

– 与各种软件兼容如:Matlab等

– 与泰克的宽带示波器搭成无缝环路

二、宽带示波器

– 带宽33GHz

– 采样率达到100GS/s

– DPOJET软件最专业的抖动眼图测试软件

– SignalVu OFDM分析软件

– 与各种软件兼容如:Matlab等

三、BERTScope误码分析仪

– 高达26Gbps码速率

– 专利的Dual ED构架，快速准确完成眼图、抖动测量 11/1/2012 122 数字接口的发送端测试方案

ANY QUESTIONS?


Thank You For Attending!


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