YSS951カタログ - Qobuzstatic.qobuz.com/info/IMG/pdf/YSS951.pdf · ・Data Bus Width 32 bits floating point (28 bits mantissa ... power-on sound and response sound ... Full-fledged

YSS951 PRELIMINARY

SPR-1 Sound Producer - 1

YSS951 Catalog CATALOG No.: LSI-4SS951A00

2008.08

■ Outline The YSS951 (SPR-1) is a sound processing LSI with built-in two DSP and one FM Synthesizer cores. This device designed for a sound processing system of TV, Karaoke, Digital Component, and so on.

■ Features ● Two DSPs (MDSP, SDSP) and one FM Synthesizer are on a chip. ● Sound Processing DSP (MDSP)

・Operating Frequency 49.152 MHz ・Data Bus Width 32 bits floating point (28 bits mantissa, 4 bits exponent) ・Program RAM (MPRAM) 40 bits × 1K words ・Coefficient RAM (CRAM) 16 bits × 1K words ・Work RAM WRAM0, WRAM1 32 bits × 1K words

WRAM2 (for delay) 16 bits × 14K words or 32 bits × 7K words (298 ms at Fs=48 kHz, 16 bits)

・Multiplier: 32bits (floating point) × 16 bits (fixed point) + 49 bits → 49 bits ● Sub DSP (SDSP)

・Operating Frequency 49.152 MHz ・Data Bus Width 24 bits (fixed point) ・High-performance asynchronous sampling rate converter

(ASRC: 2 channels, supports input frequency 8 to 192 kHz) ・10-band Parametric Equalizer (2 channels)

● FM Synthesizer ・Yamaha original FM synthesizer functions are mounted ・Built-in Sequencer is included ・Up to 4 Simultaneous sound generation (independent 4 tone color)

● Built-in ROM(Preset ROM) 8 bits × 64K words ・Various signal processing programs for MDSP and coefficients of created sound are included ・Music, power-on sound and response sound for FM synthesizer are included

● A signal processing program of MDSP is possible to change by downloading from micro-processor ● Audio I/O

・Digital Input up to 6 channels (some built-in firmware supports only 2 channels) ・Digital Output up to 4 channels.

● Supply Voltage: 3.0V to 3.6V (DVDD3), 1.65V to 1.95V (DVDD18) ● On-chip PLL ● Lead-free 48-pin LQFP package (YSS951-VZ)

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■ Application Flat-panel Television Simple Karaoke System Digital Component, PC Speaker, etc.

■ Block Diagram

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■ Comparison of Yamaha audio DSP Here shown the difference from Yamaha’s former audio DSP.

Chip Name DAP1 EVE SPR-1Function YSS950 YSS944 YSS943 YSS940 YSS920B YSS951Dolby Digital Decoding N N NDolby Digital EX Decoding N N NAAC Decoding N N NPCM Input Playback Y (up to 16ch) Y (up to 16ch) Y (up to 6ch）Dolby Pro Logic II Decoding Y N NDolby Pro Logic Iix Decoding Y N NDTS Decoding N Y Y N N NDTS 96/24 Decoding N Y Y N N NDTS-ES Decoding N Y N N N NDTS Neo:6 Decoding N Y N N N NTone Control Y Y YBass Management Y Y Y (Crossover filter)Volume Control Y Y YNoise Generation Y Y NImpulse Generation Y Y NDynamic range controller Y (multiple usable) Y Y (DRC, DRC3)Nch surround Y (Mixer) Y (Channel Distributer) NSound field Y Y Y (Reverb/Echo,Early reflection)Virtual surround Y Y Y (Phantom 3D)Headphone surround Y N Y (Phantom 3D)Parametric equalizer Y (8ch x 8Band x N) Y (5ch x 3Band) Y (2ch x 3Band) + (2ch x 10Band)Graphic equalizer

Y (implemented in PEQ)

Y(2ch x 10Band) Y (2ch x 5Band)Channel divider Y Y Y (clossover filter)Automatic Acoustic Calibration Y N YVoice cancel N N N YKey control N N N YMicrophone Level Detection N N N YSmooth volume Y N N YPower limiter N N N YDown Mixing Y (Mixer) Y NMixer Y N Y NDown Sampling Y (16ch) N N (implemented in SRC)Modification of Firmware Placement

Y N N NMultiple Firmware Calls Y N N NUser Programmability Y (design with module) N Y (Assembler) Y (Assembler)

Precision of Calculation32-bit floating floating point

(28-bit mantissa, 4-bit exponent, Coefficinet: 16-bit fixed point)

MDSP: 32-bit floating floating point format(28-bit mantissa, 4-bit exponent, Coefficinet: 16-bit fixed point format)SDSP: 24-bit fixed point format

Microprocessor Interface I²CFirmware Download Y Y Y

24 bits(Fixed) or 28bit (Fixed) or 24bit (Fixed)32 bits(Floating) ×

16ch32bit (Floating) × 16ch Input: 6ch，Output: 4ch

TDM (4ch or 8ch) (Some built-in FW supports only 2ch)Audio Data Channel Switching Y (Input/Output) N YBypass Y Y (implemented in FW) Y (implemented in FW)User Mute Y (Input/Output) Y (Output) Y (Output)External Memory Interface for delay N DRAM or SRAM (4Mbit) NInput Delay (Lip Sync) Y Y YOutput Delay Y Y NStream Determination N N NAuto Mute Y N NStatus Port Auto mute，Interrupt Zero detection etc. NGeneral-purpose I/O Port

4 16 Maximum 9 to minimum 0(Shared with Audio Interface)

FM Synthesizer N N N YSRC N N N YInternal Operation Clock Generator Y Y YPower-down Mode Y N NOperating Frequency 165.888 MHz 50MHz 49.152MHz

2.5V (Core) 1.8V (Core)3.3V (Pins) 3.3V (Pins)

Power Consumption 130 mW 165mW TBDPackage SQFP64 SQFP100 LQF48Lead-free Y Y YY

8

YY

211mW (at Dolby Digital)

178.176MHz

YY

Y (Output)

Y

Y

Y (8ch x 5Band x 2)Y (implemented in PEQ)

YYY

Y

ADAMB

LQFP144

Har

dwar

e

Digital Audio Interface

Firm

war

e

Supply Voltage1.2V (Core)，3.3V (Pins)

Y (up to 8ch)

YY

Y (2ch)

32-bit floating point format (24-bit mantissa, 8-bit exponent，

Coefficient: 32-bit floating point format)

YYYYY

Y

Y

YYY

4-wire Serial InterfaceY

Y

Zero detection，Auto mute，Interrupt

SRAM (4Mbit)

YY

24 bits(Fixed) × 8ch

Y (Output)

[Note 1] Y: workable, N: Unworkable

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■ Pin Assignment

DVSS

NC

NC

NC

NC

Xin

Xout

PLLAVSS

PLLAVDD

SDA

SCLDVDD18

TEST

DVDD3

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

DVDD3

NC

NC

NC

13

14

15

16

48

47

46

45

44

42

41

40

39

38

37

43

DVSS

17

18

19

20

21

22

23

24

< 48-pin LQFP top view >

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■ Pin Function Category Pin Number Pin Name I/O Function I2C 19 SCL Is I2C Clock Interface 18 SDA Is/Od I2C Data General-purpose Input and Output

9 GPIO0 I/O General–purpose inputs and outputs or digital audio signals

8 GPIO1 I/O 7 GPIO2 I/O 5 GPIO3 I/O 4 GPIO4 I/O 3 GPIO5 I/O 2 GPIO6 I/O 47 GPIO7 I/O 46 GPIO8 I/O 45 GPIO9 I/O 44 GPIO10 I/O 43 GPIO11 I/O

When not used, connect these pins to DVDD3 or Ground.

System 10 IC_N Is Reset 16 Xin I Clock Input 15 Xout O Clock Output Test 21 TEST I Test Pin 27 TESTI I Connect these pins to Ground. Power 17, 48 DVDD3 － Pin digital power supply (Typ.3.3V) 6, 42 DVDD18 － Core digital power supply (Typ.1.8V) 1, 20, 41 DVSS － Digital Ground 13 PLLAVDD － PLL analog power supply (Typ.3.3V) 11 PLLDVDD － PLL digital power supply (Typ.1.8V) 14 PLLAVSS － PLL analog ground 12 PLLDVSS － PLL digital ground Unused 22, 23, 24, 25, 26,

28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40

NC － Not used. Connect these pins to Ground.

[Note 1] I/O symbols

I : Input Is : Schmitt trigger input O : Output I/O : Input and output Is/Od : Input and output (Schmitt trigger input, open-drain on output) － : Power supply pin, Ground pin

[Note 2] Xin pin input frequency MDSP firmware in the built-in ROM is designed with 24.576MHz of Xin.

[Note 3] Example of circuit connected to crystal oscillator

The resistor and capacitor values vary depending on a crystal oscillator. Be sure to meet the specifications of the crystal oscillator to be used.

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■ Function Details

〔1〕 SDSP SDSP is a 24-bit fixed point DSP used for realizing the following functions:

・ Sampling Rate Converter (SRC) ・ 10-band Parametric Equalizer (PEQ) ・ De-emphasis Filter ・ DC-cut Filter

(a) SRC SRC is an asynchronous sampling rate converter which has the following principal characteristics. ・ Number of channels 2 channels ・ Total Harmonic Distortion + Noise (1kHz sign wave I/O) -108 dB ・ S/N Ratio 114 dB ・ DPLL lock time

Input Sampling Frequency 32kHz↔48kHz switching 120 ms (Typ.) Input Sampling Frequency 48kHz→192kHz switching 220 ms (Typ.)

・ Number of Delay Samples (Interpolation) 23 × SRC input side sampling period (Decimation) 8 × SRC output side sampling period

・ Input Sampling Frequency 8 kHz to 192 kHz ・ Output Sampling Frequency 44.1 kHz, 48 kHz ・ Gain -0.28dB

(b) De-emphasis Filter The de-emphasis filter that has the following frequency characteristics is available.

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(c) PEQ This is a 10-band parametric equalizer that is used for frequency characteristics correction of a speaker chassis and so on. Coefficient and data precisions are shown below:

Bans Coefficient Data 0 to 5 Signed 24 bits Signed 47 bits 6 to 9 Signed 47 bits Signed 47 bits

The signal flow in PEQ is shown below.

1) Band 0 to 5 In band 0 to 5, coefficients are signed 24-bit precision and data are signed 47-bit precision. A center frequency should be set to 400Hz or higher.

shift

shift

shift

shift

shift

shift

shift

2) Band 6 to 9 In Band 6 to 9, coefficients and data are signed 47-bit precision.

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〔2〕 MDSP MDSP is a DSP specialized for processing sound field. It realizes various functions by executing firmware (preset pattern) stored in the built-in ROM. And also, it is possible to modify these functions by downloading firmware coefficients from a microprocessor. For details of the built-in firmware, see “SPR-1 Firmware Manual”. The figure below shows the block diagram of the MDSP hardware.

(a) Internal Firmware The firmware, using MDSP, is implemented in the built-in ROM. This firmware has various functions that control and improve the speaker sound of TV system, mini component system, etc. Use to switch the following three modes according to your product specification.

1) Basic Mode Basic DSP functions (Lip Sync, Equalizer, and Crossover filter) are realized.

2) Audio Video Mode (A/V Mode) Surround effect that creates spatial reflected sound is realized in addition to basic functions.

3) Karaoke Mode Full-fledged Karaoke functions as microphone echo and key control are realized in addition to basic functions.

This firmware handles 2ch audio signals and supports sampling rate of 48 kHz. In Karaoke mode, a microphone input signal is handled in additional 1ch. The functional descriptions of the built-in firmware are shown in the table below.

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Operation Mode Firmware Name Abbr.

Basic A/V KaraokeFunctional Description

Top - ✓ ✓ ✓ Realizes the runtime transfer function.

Lip sync LPS ✓ ✓ ✓ Delays audio signals up to 149ms.

Level detect LD ✓ Detects a microphone signal level.

Voice cancel VC ✓ Decreases vocal element from audio signal.

Key control KC ✓ Shifts a pitch of audio signal.

Early reflection ER ✓ ✓ Creates early-reflected sound.

Reverb/Echo RE ✓ ✓ Creates rear reverberant sound or microphone echo.

Phantom 3D P3D ✓ ✓ ✓ Enhances spatial effect and realistic sensation of a source signal with

virtual 3D processing.

Parametric equalizer PEQ ✓ ✓ Controls sound quality by using the 3-band parametric equalizer.

Dynamic range compressor DRC ✓ Makes sound clear to listen by compressing the dynamic range.

Dynamic range compressor 3 DRC3 ✓ Makes sound clear and natural to listen by compressing the dynamic

range independently in 3 bands.

Graphic equalizer GEQ ✓ ✓ ✓ Controls sound quality with tone control and 5-band graphic equalizer.

Smooth volume SV ✓ ✓ ✓ Master volume changes smoothly. Loudness function is also included.

Crossover filter CF ✓ ✓ ✓ Configures 1-way, 2-way, or 2.1 digital networks.

Power limiter PWL ✓ ✓ ✓ Limits a peak value of the signal according to speaker’s performance.

(b) Firmware Coefficient Easy-to-use and typical firmware coefficients are mounted in the built-in ROM. A host processor can transfer in whole or part of the firmware coefficients in to CRAM (MDSP coefficient RAM) by specifying a preset pattern. And also, host processor can transfer own coefficients to CRAM. In this case, as having SRC built-in, it is not necessary to hold coefficients for each sampling rate which an existing DSP requires; a host processor holds coefficients only corresponding to a sampling rate of 48 kHz.

(c) Preset Pattern The firmware and firmware coefficients are stored in the built-in ROM as preset pattern. One preset pattern corresponds to one ROM block number. A host processor can immediately set the relevant firmware and firmware coefficients to MPRAM (MDSP instruction RAM) and CRAM (MDSP coefficient RAM) by calling the block number. YSS951 has 668 preset patterns stored in the built-in ROM.

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(d) Firmware Block Diagram Firmware block diagrams in each mode are shown below:

1) Basic Mode Lip sync

CHI4/5

CHI6/7

CHI2/3

Phantom 3D

Dynamic range compressor

Graphic equalizer

Smooth volume

Crossover filter

Power limiter

CHO2/3

CHO0/1

CHO4/5

CHI8/9

FMI

AB

C

E

D

2) Audio Video Mode

Lip sync

CHI4/5

CHI6/7

CHI2/3

Phantom 3D

Dyna

mic range

compressor 3

Graphic equalizer

Smooth volume

Crossover filter

Power limiter

CHO2/3

CHO0/1

CHO4/5

CHI8/9

FMI

AB

C

E

D

Parametric equalizer

Early reflection

Reverb/Echo

3) Karaoke Mode

Lip

syncCHI4/5

CHI6/7

CHI2/3

Pha

ntom

3D

Gra

phic

equ

aliz

er

Sm

ooth

vol

ume

Cro

ssov

er fi

lter

Pow

er li

mite

r

CHO2/3

CHO0/1

CH

O4/

5

CH

I8/9

FM

I

AB

C

E

D

Par

amet

ric e

qual

izer

Ear

ly r

efle

ctio

nR

ever

b/E

cho

Voi

ce c

ance

l

Key

con

trol

Leve

l det

ect

[Cautions] A to E indicates the following each path. A: External lip sync device output path B: Line output path C: Volume interlock line output path D: Main output path

E: SDSP 10-band PEQ processing path

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(e) Examples of Preset Patterns “Position” classified into the following three types is stored as preset pattern in the ROM in order to give surround effects as required.

1) DTV The following six different patterns are prepared for TV audio.

Operation Mode No. Name

Basic A/V KaraokeFunction

0 DTV Theater ✓ Realizes theater sound for a large screen

1 DTV Movie ✓ Realizes a sound field having scale and spatial effect suitable for a large screen, regardless of genre.

2 DTV Drama ✓ Realizes effect that makes wide realistic sensation of TV drama by giving spatial effect and reality to voice.

3 DTV Sports ✓ Realizes sound field effects for more enjoying sports program by giving reality to commentary and feverish reality sensation to cheering.

4 DTV Variety Music ✓ Gives realistic sensation suitable for variety or music program.

5 DTV Game ✓ Relizes sound field effects with the sense of virtual reality regardless of game genre.

2) Music The following five different patterns are prepared for music sources such as CD etc.



0 Music Large Hall 0 ✓ Realizes the realistic sensation that makes you feel as if listening to a performance in a wide hall.

1 Music Large Hall 1 ✓ Realizes sound field in a large hall which has beautiful natual sound.

2 Music Small Hall ✓ Realizes a sense of unity with a stage that makes you feel as if instruments are closely placed to you in a small hall.

3 Music Shoe Box ✓ Realizes rich sound and spatial sense peculiar to a shoe box.

4 Music Opera House ✓ Realizes the sense of inflection that gives air of excitement of a performance on a stage from popular to classic music as felt in an opera house.

3) Karaoke The following five different patterns are prepared for Karaoke Sources.



0 Karaoke Echo ✓ Realizes the microphone echo typically for microphone signal, and real and mellow sound field effects to audio signals.

1 Karaoke Super Echo ✓ Realizes the microphone echo with spatial effects for microphone signal, and real and mellow sound field effects to audio signals.

2 Karaoke On Stage ✓ In addition to the three-dimensional microphone echo, this coefficient effect adds acoustic effects as felt in a stage to a microphone signal. And, it realizes real and mellow sound field effects for audio signals.

3 Karaoke Pro ✓ In addition to the three-dimensional microphone echo, this coefficient effect adds acoustic effects as felt in a concert hall to microphone signals. And, it realizes real and mellow sound field effects for audio signals.

4 Karaoke Super Pro ✓ In addition to the three-dimensional microphone echo, this coefficient effect adds acoustic effects as felt in a full-scale concert hall to microphone signals. And, it realizes real and mellow sound field effects for audio signals.

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〔3〕 FM Synthesizer ・Yamaha original FM synthesizer functions are mounted ・Built-in Sequencer is included ・Up to 4 Simultaneous sound generation (independent 4 tone color) ・A variety of Music, power-on sound and response sound are had in the built-in ROM ・Capable of playback original music, power-on sound and response sound by writing them from a

microcomputer (For details of the usage, please contact our sales department.)

FM synthesizer contents in the ROM are shown below.

No. Built-in ROM Block Number

Contents Name Description Remarks

0 32 Power_On_Short_01 Power-on Sound 1 European premium accent by Synth Pad 1 33 Power_Off_Short_01 Power-off Sound 1 European premium accent by Synth Pad 2 34 Power_On_Short_02 Power-on Sound 2 An image of “Wake-Up” by arpeggio 3 35 Power_On_01 Power-on Sound 3 (ethnic music) Indian ethnic sound 4 36 Power_On_02 Power-on Sound 4 An image of “spirit of innovation” 5 37 Power_On_03 Power-on Sound 5 Synth Pad and like 6 38 Power_On_04 Power-on Sound 6 An image of “Heavy-hitting sound” 7 39 Power_On_Short_03 Power-on Sound 7 (ethnic music) Chinese sound 8 40 Power_On_Short_04 Power-on Sound 8 (ethnic music) Japanese-inspired sound 9 41 Operation_01 Button operation sound 1 Traditional operation sound 10 42 Operation_02 Button operation sound 2 Operation sound with futuristic image 11 43 Operation_03 Button operation sound 3 Operation sound with an image of “Chan” 12 44 Operation_04 Button operation sound 4 Operation sound with atmosphere of a car horn13 45 Set_01 Confirmation Sound Traditional sound effects 14 46 Alert_01 Alert Sound Traditional alert sound 15 47 Pafopafo_01 Karaoke Effect 1 Bugle sound like “puff-puff” 16 48 Chime_01 Karaoke Effect 2 Chime for success 17 49 Booing_01 Karaoke Effect 3 An image of booing or “wrong answer” 18 50 Comical_01 Karaoke Effect 4 Comical sound effects 19 51 ARIB_01 Flash Chime 1 －

20 52 ARIB_02 Flash Chime 2 －




24 56 ARIB_06 Button operation sound 5 －








32 64 ARIB_14 Alert Sound 1 －



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■ Registers and Internal Memories

〔1〕 Registers

(a) Register List The register is managed in byte length (8 bits) for each address. The address map is shown below.

Address Byte Name Access Default bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

[Note 1]

0x00 POEN0 R/W 0x00 0 0 0 0 POEN[11:8]

0x01 POEN1 R/W 0x00 POEN[7:3] 0 0 0

0x02 PIDT0 R 0x00 0 0 0 0 PIDT[11:8]

0x03 PIDT1 R 0x00 PIDT[7:3] 0 0 0

0x04 PODT0 R/W 0x00 0 0 0 0 PODT[11:8]

0x05 PODT1 R/W 0x00 PODT[7:3] 0 0 0

0x06 SYSMD R/W 0x00 0 0 0 0 0 DEVMD 0 HANGUPR

0x07 AIFMD R/W 0x10 0 0 PI PIO AIFMD[3:0]

0x08 AIFIFMT R/W 0x00 0 0 SDIFMT[1:0] SDIBIT[1:0] SDIWCKP SDIBCKP

0x09 AIFOFMT R/W 0x00 0 0 SDOFMT[1:0] SDOBIT[1:0] SDOWCKP SDOBCKP

0x0A MDSPMD R/W 0x00 0 0 0 0 0 0 WRAMRTMD WRAMMD

0x0B SDSPMD R/W 0x00 0 0 0 0 0 0 DEMON DCM

0x0C 0x62 0 1 1 0 0 0 1 0

0x0D 0x01 0 0 0 0 0 0 0 1

0x0E FSM R/W 0x00 0 0 0 0 0 0 FSM[1:0]

0x0F RAMCLR R/W 0x00 0 0 0 0 0 0 WRAMCLR SWRAMCLR

0x10 MUTE R/W 0x00 0 0 0 0 0 FMMUTEN MDSPMUTEN SDSPMUTEN

0x11 DSPSTART R/W 0x00 0 0 0 0 0 0 MDSPSTART SDSPSTART

0x12 DSPREG R/W 0x00 0 0 0 0 0 0 0 DSPREG

0x13 MDSPREQ R/W 0x00 MDSPREQ[7:0]

0x14 MDSPDAT R/W 0x00 MDSPDAT[7:0]

0x15 MIREQ R/W 0x00 MIREQ[7:0]

0x16 MIDAT R/W 0x00 MIDAT[7:0]

0x17 DPLLFS R 0x20 DPLLFS[7:0]

0x18 ZDET R 0x00 ZDET[7:0]

0x19 ID R 0x00 ID[7:0]

0x1A 0 0 0 0 0 0 0 0

0x1B MDSPST R/W 0x00 0 0 0 0 0 0 0 MDSPERR

[Note 2] 0x1C OVPC0 R 0x00 MDSPOVF 0 0 0 0 0 OVPC[9:8]

0x1D OVPC1 R 0x00 OVPC[7:0]

0x1E STEP0 R 0x00 STEP[15:8]

0x1F STEP1 R 0x00 STEP[7:0]

0x20 SDSPST R/W 0xF0SDIERR [Note 2]

1 1 UNLOCK

[Note 2] FSIERR [Note 2]

FSERR [Note 2]

SDSPOVF

[Note 2] SDSPERR [Note 2]

0x21 0 0 0 0 0 0 0 0

0x22 0 0 0 0 0 0 0 0

0x23 PLLERR R/W 0x00 0 0 0 0 0 PLLERRE PLLERRS PLLERR[Note 2]

0x24

～

0x28

0x00 0 0 0 0 0 0 0 0

0x29 0x04 0 0 0 0 0 1 0 0

0x2A 0x2E 0 0 1 0 1 1 1 0

0x2B

～

0x3F

0x00 0 0 0 0 0 0 0 0

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Accessible area in normal operation mode. Reserved area. Write “0” in a write operation. “0” is read in a read operation. Accessible area regardless of PLL operation.

[Note 1] “Access” column indicates access privileges from a microprocessor. [Note 2] This indicates an error register or status register with data holding function. This register holds an error or status until a

microprocessor clears it.

(b) Register Access These registers can be read or written by using a register access command or register quick access command.

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〔2〕 Built-in RAM

(a) Address Map The built-in RAM is managed in word length (16, 24, or 32 bits) for each address. The address map is shown below.

Address WRAMMD=0 WRAMMD=1 0x0000 WRAM0 [See Note 1]

32 bits × 32 words WRAM0 [See Note 1]

32 bits × 32 words

0x0020 WRAM1 [See Note 1]

32 bits × 992 words WRAM1 [See Note 1]

32 bits × 992 words

WRAM2 [See Note 1] 32 bits × 7K words

0x0400

WRAM2 [Note 1] 16 bits × 14K words

0x3C00

0x4000 CRAM [See Note 1] 16 bits × 1024 words

CRAM [See Note 1] 16 bits × 1024 words

0x4400

MPRAM [See Note 2] 40 bits × 1024 words

MPRAM [See Note 2] 40 bits × 1024 words

0x4800 QBUS [See Note 1 32 bits × 64 words

QBUS [See Note 1] 32 bits × 64 words

0x4840

0x8000

PEQ Coefficient RAM 24 bits × 128 words

PEQ Coefficient RAM 24 bits × 128 words

0x8080

0xC032 FM Synthesizer Parameter

[See Note 2] 16 bits × 1 word

FM Synthesizer Parameter


0xC033 0xC039 FM Synthesizer Parameter


FM Synthesizer Parameter


0xC03A

0xFFFF

Indicates the bits not implemented Indicates reserved area [See Note 3]

[Note 1] WRAM0 to 2, CRAM, MPRAM and QBUS are built-in RAM areas controlled by MDSP.

[Note 2] MPRAM (0x4400-0x47FF) are not able to read a value. And FM synthesizer parameters (0xC032, 0xC039) are not also read. When reading these areas, values are 0.

[Note 3] Writing a data to reserved area is prohibited. And continuous reading including the reserved area is prohibited too.

(b) Accessing the built-in RAM This RAM can be read or written by using a RAM access command or RAM quick access command.

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〔3〕 Built-in ROM The ROM data is stored in block unit. Accessing to the ROM should be set in block unit.

i. Startup of the initial Setting Default setting of the LSI is stored in block 0 on the built-in ROM. This default setting is automatically started when IC_N is changed from L to H.

ii. Startup by issuing the built-in ROM access command When an ROM access command (PRESETROM0 to 3) is received, series of ROM access commands stored in the built-in ROM are executed. Four kinds of access commands and one-byte argument (address table [7:0]) specify a block number.

Built-in ROM Access Command Block Number to Access Block Number Setting

PRESETROM0 0 to 255 Address Table [7:0] + 0




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■ Microprocessor Interface

〔1〕 Microprocessor Commands Access to registers and built-in memories in this LSI is executed by transmitting a command from microprocessor. After sending an 8-bit command to this LSI, set one or more arguments in 8-bit unit. A command is sent to this LSI via I2C bus.

(a) Command Type The table below shows the command type. When a command is received other than these commands, this LSI returns the NACK(ACK=1) and wait a next command.

Command Type Command Name 7 6 5 4 3 2 1 0

Register Access REGADDR 0 0 ADDR[5:0]

DSPSTART 0 1 0 0 0 0 0 0 Register Quick Access

DSPSTOP 0 1 0 0 0 0 0 1

PRESETROM0 0 1 1 1 0 0 0 0

PRESETROM1 0 1 1 1 0 0 0 1

PRESETROM2 0 1 1 1 0 0 1 0

PRESETROM3 0 1 1 1 0 0 1 1

Built-in ROM Access

PRROMSTOP 0 1 0 0 0 0 1 1

Built-in RAM Access READ/WRITE 1 0 0 0 0 0 0 0

R/W_WORK0 0 1 1 0 0 1 0 0

R/W_WORK1 0 1 1 0 0 1 0 1

R/W_WORK2 0 1 1 0 0 1 1 0 Built-in RAM Quick Access

R/W_WORK3 0 1 1 0 0 1 1 1

(b) Acknowledge Control At receiving a command, this LSI returns an Acknowledge (ACK or NACK). When receiving an undefined command, this LSI returns the NACK (ACK=1) to inform the microprocessor that data has not been received.

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〔2〕 I2C Bus A microprocessor can control this LSI via I2C bus. Connect the SCL and SDA pins to I2C pin of host processor. This will allows host processor to access to registers and built-in memory in this LSI.

[Note 1] The I2C bus is the serial interface defined by Philips. For details of I2C specification, see “I2C Bus Specification” issued by Philips.

[Note 2] This LSI supports standard and fast modes. But High-speed Mode (Hs mode) is not supported.

(a) I2C Bus Device Address The I2C bus device address, allocated to this LSI, is [7’b110_1100].

A6 A5 A4 A3 A2 A1 A0 1 1 0 1 1 0 0

[Note] YDA155 (DD-1), YDA156 (DD-1SP), and YSS951 (SPR-1) have the same device address; therefore,

two or more these devices cannot be connected on the same I2C Bus.

(b) I2C Bus Data Transfer Format The data is transmitted or received in MSB first. After this description, the symbols are defined as follows: S: START Condition Sr: Repeated START Condition P: STOP Condition ACK: Acknowledge (ACK=0) NACK: Not acknowledge (ACK=1) Gray color: Outputting Data from this LSI

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1) Writing to this LSI (Transmission) After “START Condition” is generated, 7-bit device address, R/W̄(=0), command and argument are transmitted to this LSI:.

2) Reading from this LSI (Data Request) a. After “START Condition” is generated, device address, R/W̄(=0), command and argument are transmitted to

this LSI:. b. Generate “Repeated START Condition” and transmit device address and R/W̄(=1) to this LSI. c. Data is continuously output from this LSI. d. This LSI Stops to output data when the master device returns NACK. e. Master device transmits “STOP Condition”.

After transmitting a command and argument to this LSI, “START Condition” can be generated again after generating “STOP Condition”.

3) An example of implementation of built-in RAM Quick Read Here shows an example of implementation of built-in RAM Quick Read.

After transmitting a command to this LSI, “START Condition” can be generated again after generating “STOP Condition”.

S

SPR-1Device Addr[6:0]

0RWORK0 - 3

CommandSDA PArgument 0

[7:0]

R/W

AC

K

AC

K

AC

K

1 1 0 1 1 0 0

PRead Data 0

[7:0]S

SPR-1Device Addr[6:0]

1Read Data 1

[7:0]Read Data 2

[7:0]Read Data 3

[7:0]SDA

R/W

AC

K

AC

K

AC

K

AC

K

NA

CK

1 1 0 1 1 0 0

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■ Audio Interface

〔1〕 Audio Interface Setting GPIO pin can be used for audio interface by setting AIFMD[3:0] and PIO registers. The relation between register setting and pin function is shown in the table below.

• AIFMD[3:0] can select input signal from SDI0, SDI1, or SDI2 by setting 1, 2, or 3. (The outline characters on a colored background signals are not connected to an internal circuit.)

• Described “GPIO*” pins can be used as general-purpose input and output pins PIO. • The firmware implemented in the built-in ROM is at PIO register=0.

(a) PIO Register = 0

AIFMD[3:0] 0 1 2 3

Mode Name 2ch SDI + 4ch SDI 2ch SDI Selection 2ch SDI Selection 2ch SDI Selection

Operation Master Master Master Master

GPIO0 WCK input WCK input 0 WCK input 0 WCK input 0

GPIO1 BCK input BCK input 0 BCK input 0 BCK input 0

GPIO2 SDI0 SDI0 SDI0 SDI0

GPIO3 SDI1 WCK input 1 WCK input 1 WCK input 1

GPIO4 SDI2 BCK input 1 BCK input 1 BCK input 1

GPIO5 GPIO5 SDI1 SDI1 SDI1

GPIO6 GPIO6 WCK input 2 WCK input 2 WCK input 2

GPIO7 MCK output BCK input 2 BCK input 2 BCK input 2

GPIO8 SDO1 SDI2 SDI2 SDI2

GPIO9 SDO0 SDO0 SDO0 SDO0

GPIO10 WCK output WCK output WCK output WCK output

GPIO11 BCK output BCK output BCK output BCK output

[Note 1] [Note 2] [Note 3]

(b) PIO Register = 1

AIFMD[3:0] 0 1 2 3

Mode Name 2ch SDI +4ch SDI 2ch SDI Selection 2ch SDI Selection 2ch SDI Selection

Operation Master Master Master Master

GPIO0 WCK input WCK input 0 WCK input 0 WCK input 0

GPIO1 BCK input BCK input 0 BCK input 0 BCK input 0

GPIO2 SDI0 SDI0 SDI0 SDI0


GPIO4 GPIO4 BCK input 1 BCK input 1 BCK input 1



GPIO7 GPIO7 BCK input 2 BCK input 2 BCK input 2


GPIO9 GPIO9 GPIO9 GPIO9 GPIO9



[Note 1] [Note 2] [Note 3]

[Note 1] Connect GPIO[2:0] to SRC. [Note 2] Connect GPIO[5:3] to SRC. [Note 3] Connect GPIO[8:6] to SRC.

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〔2〕 Audio Signal Flow Here shows the flow of audio signals in YSS951.

(a) AIF Mode = 0

FMSynthesizer

AIF

SRC+De-emphasis

10bands PEQ

SDSP MDSP

CHI6/7

CH

I2/3

CH

I4/5

CHI8/9FMI

CH

O0/

1

CHO4/5

CH

O2/

3

SDI0

SDI1

SDI2 SDO1

SDO0GPIO2

GPIO3

GPIO4

GPIO9

GPIO8

YSS951

(b) AIF Mode = 1, 2, or 3

FMSynthesizer

AIF

SRC+De-emphasis

10bands PEQ

SDSP MDSP

CHI6/7

CH

I2/3

CH

I4/5

CHI8/9FMI

CH

O0

/1

CHO4/5

SDI0

SDI1

SDI2

GPIO2

GPIO5

GPIO8

YSS951

‘0’‘0’

SDO0 GPIO9

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〔3〕 Input Format

The audio data are input in accordance with the following format when AIFMD[3:0] register value is 0, 1, 2, or 3. 24-bit 2-chanel (L/R) data are input into GPIO pin which has been set in SDI function.

SDIWCKP=0

SDIWCKP=1

SDIBCKP=0

SDIBCKP=1

GPIO* SDIFMT[1:0] = 00SDIBIT[1:0] = xx

MSB

SDIFMT[1:0] = 10SDIBIT[1:0] = xx

SDIFMT[1:0] = 01SDIBIT[1:0] = 00

SDIFMT[1:0] = 01SDIBIT[1:0] = 01

SDIFMT[1:0] = 01SDIBIT[1:0] = 10

SDIFMT[1:0] = 01SDIBIT[1:0] = 11

1 frame (1/fs = 64 BCKs)

Rch(n)

Rch(n)

Rch(n)Rch(n-1)

Rch(n)Rch(n-1)

Rch(n)Rch(n-1)

Rch(n)Rch(n-1)

23 22 21 20

Lch(n)

Lch(n)

Lch(n)

Lch(n)

Lch(n)

Lch(n)

32 BCKs 32 BCKs

3 2 1 0

LSB

MSB

23 22 21 20 7 6

LSB

MSB

23 22 21 20

MSB

23 22 21 20

MSB

23 22 21 20 9 8 7 6 5

3 2 1 0

3 2 1 0

LSB

3 2 1 0

LSB

3 2 1 0

LSB

3 2 1 0

LSB

Don't care Don't care





4

MSB

23 22 21 20 9 87 6 5 3 2 1 0

LSB

4

9 8 5 4

MSB

23 22 21 20 7 69 83 2 1 0

LSB

5 4

7 69 8 5 4

MSB

23 22 21 20 7 69 8 5 4

7 69 8 5 4

MSB

23 22 21 20 3 2 1 0

LSB

7 69 8 5 4

9 8 7 6 5 4

MSB

23 22 21 20 3 2 1 0

LSB

9 8 7 6 5 4

MSB

23 22 21 20 3 2 1 0

LSB Don't care Don't care

9 8 7 6 5 4

MSB

23 22 21 20 3 2 1 0

LSB

9 8 7 6 5 4

Word Clock

Bit Clock

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〔4〕 Output Format

The audio data are output in accordance with the following format when AIFMD[3:0] register value is 0, 1, 2, or 3. 24-bit 2-chanel (L/R) data are output from GPIO pin which has been set in SDO function.

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■ Examples of System Configuration ● TV

Lip SyncIC

YSS951

SRCTV Audio

Codec-DSP

Microprocessor

DSP

WCK,BCK,MCK

2ch

I2C

WCK,BCK Digital Amplifier

2ch

FM Synthesizer

WCK,BCK

2ch

2ch

External lip sync LSI is able to be connected when requiring delay time is longer than YSS951 delay setting.

● SET TOP BOX with Karaoke capability

● Speaker System

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■ Electrical Characteristics

〔1〕 Absolute Maximum Ratings Parameter Symbol Condition Min. Typ. Max. Unit

Supply voltage 1 (3.3V system) DVDD3 [Note 1] -0.5 4.6 V

PLLAVDD

Supply voltage 2 (1.8V system) DVDD18 [Note 1] -0.5 2.5 V PLLDVDD

Input voltage 1 VI1 [Note 1,2] -0.3 5.5 V

Input voltage 2 VI2 [Note 1,3] -0.3 4.1 V

Input voltage 3 VI3 [Note 1,4] -0.3 DVDD3+0.3 V

Storage temperature TSTG -65 150 °C

[Note 1] All ground pins are tied to 0V. [Note 2] Applies to GPIO11-0 and IC_N pins. Do not input any voltage to these pins when power-off. [Note 3] Applies to SDA and SCL pins. [Note 4] Applies to Xin pin.

〔2〕 Recommended Operating Conditions Parameter Symbol Condition Min. Typ. Max. Unit

Supply voltage 1 (3.3V system) DVDD3 [Note 1] 3.0 3.3 3.6 V

PLLAVDD

Supply voltage 2 (1.8V system) DVDD18 [Note 1] 1.65 1.8 1.95 V

PLLDVDD

Operating ambient temperature Ta -40 25 85 °C

[Note 1] All ground pins are tied to 0V.

〔3〕 Consumption Current Parameter Symbol Condition Min. Typ. Max. Unit

Power consumption [Note 1] TBD TBD mW

DVDD3 + PLLAVDD [Note 1] TBD TBD mA

DVDD18 + PLLDVDD [Note 1] 55 80 mA

[Note 1] Typical values are measured under the typical value of the above recommended operating conditions. And maximum values are measured under the maximum value of recommended operating conditions. However, high-level input voltage of input pins is DVDD3 and a low-level input voltage is DVSS.

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〔4〕 DC Characteristics Parameter Symbol Condition Min. Typ. Max. Unit

High level input voltage 1 VIH1 [Note 1] 2.0 5.25 V

Low level input voltage 1 VIL1 [Note 1] 0.8 V

High level input voltage 2 VIH2 [Note 2] 0.7×DVDD3 V

Low level input voltage 2 VIL2 [Note 2] 0.3×DVDD3 V

High level output voltage VOH [Note 3] 2.4 V

Low level output voltage 1 VOL1 [Note 4] 0.4 V

Low level output voltage 2 VOL2 [Note 5] 0.4 V

Schmitt width ISH [Note 6] 0.05×DVDD3 V

Input leakage Current II ±2 μA

Input Pin Capacitance CI 5 pF

[Note 1] Applies to GPIO11-0 and IC_N pins. [Note 2] Applies to SDA, SCL and Xin pins. [Note 3] Applies to GPIO11-3 pins; however IOH=-1.0mA. [Note 4] Applies to GPIO11-3 pins; however IOL=1.0mA. [Note 5] Applies to SDA pin; however IOL=3.0mA. [Note 6] Applies to SDA and SCL pins.

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〔5〕 AC Characteristics

(a) Power-on/off / Clock / Hardware Reset

Parameter Symbol Condition Min. Typ. Max. Unit

Power-on and Power-off time between 3.3V system and 1.8V system

tV3V1 -1 1 sec

Xin clock frequency fXin 22.5792, 24.576

MHz

Xin clock duty ratio dXin 40 60 －

Internal clock frequency fDCLK 2 × fXin －

IC_N time 1 tIC1 TBD ms

IC_N time 2 tIC2 1 μs

IC_N time 3 tIC3 0 sec

[Note] The time lag between 3.3V and 1.8V power supplies must be within one second at turning on and off. If only one power keep on supplying, LSI would be damaged.

1) Power-on/off

2) Normal Operation

The Xin input and power supply must be stabilized.

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(b) Microprocessor Interface

1) Input Condition


SCL input clock frequency fSCL [Note 1] 0 400 kHz

“START” condition hold time tHD;STA [Note 1] 0.6 μs

SCL input clock “L” period tLOW [Note 1] 1.3 μs

SCL input clock “H” period tHIGH [Note 1] 0.6 μs

Repeated “START” condition Setup time tSU;STA [Note 1] 0.6 μs

Data input hold time tHD;DAT [Note 1] 0 μs

Data input setup time tSU;DAT [Note 1] 100 ns

SDA,SCL input rise time tr [Note 1] 300 ns

SDA,SCL input fall time tf [Note 1] 300 ns

“STOP” condition setup time tSU;STO [Note 1] 0.6 μs

Bus free time between “STOP” and “START” conditions

tBUF [Note 1] 1.3 μs

Capacitive load in each bus line Cb [Note 1] 400 pF

[Note 1] The AC characteristics of the microprocessor interface are measured under the following conditions: Input Conditions : VIH = 0.80×DVDD3, VIL = 0.20×DVDD3 Measurement point : VIH = 0.70×DVDD3, VIL = 0.30×DVDD3

VOH= 0.70×DVDD3, VOL= 0.30×DVDD3

2) Output Condition


SDA “L” output delay time tDSDAL Capacitor load=400pF, IOL= +3.0mA 1.15 μs

Data output hold time tHD;DAT Capacitor load=400pF, IOL= +3.0mA 0 0.9 μs

S: START Condition, Sr: Repeated START Condition P: STOP Condition

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(c) Audio Interface The AC characteristics of the audio interface are measured under the following conditions:

Input Conditions : VIH = 2.4V, VIL = 0.4V Measurement point : VIH = 2.0V, VIL = 0.8V

VOH= 2.0V, VOL= 0.8V

1) AIFMD[3:0] Register = 0

i. Word Clock Input


WCK input frequency fIWCK fXin=22.5792MHz, 24.576MHz 8 192 kHz

WCK input duty ratio dIWCK 50 %

ii. Audio Input 1


BCK input frequency fIBCK 64×fIWCK －

BCK input duty ratio dIBCK 50 %

BCK input rise time tIBCKR 15 ns

BCK input fall time tIBCKF 15 ns

WCK input, SDI0 setup time tSDIS1 10 ns

WCK input, SDI0 hold time tSDIH1 10 ns

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iii. Word Clock Output


WCK output frequency fOWCK 44.1, 48 kHz

WCK output duty ratio dOWCK 50 %

WCK Output

fOWCK

dOWCK dOWCK

iv. Audio Input 2 and Audio Output


SDI2-1 setup time tSDIS2 65 ns

SDI2-1 hold time tSDIH2 10 ns

BCK output frequency fOBCK 64×fOWCK －

BCK output duty ratio dOBCK 50 %

BCK output rise time tOBCKR CL=20pF 15 ns

BCK output fall time tOBCKF CL=20pF 15 ns

WCK, SDO1-0 output delay time tSDOD CL=20pF -45 45 ns

v. Master Clock Output


MCK output frequency fOMCK 256×fOWCK －

MCK output duty ratio dOMCK 50 %

MCK output rise time tOMCKR CL=20pF 10 ns

MCK output fall time tOMCKF CL=20pF 10 ns

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2) AIFMD[3:0] Register = 1, 2, or 3

i. Word Clock Input


WCK input 0, 1, 2 frequency fIWCK fXin=22.5792MHz, 24.576MHz 8 192 kHz

WCK input 0, 1, 2 duty ratio dIWCK 50 %

ii. Audio Input


BCK input 0, 1, 2 frequency fIBCK 64×fIWCK －

BCK input 0, 1, 2 duty ratio dIBCK 50 %

BCK input 0, 1, 2 rise time tIBCKR 15 ns

BCK input 0, 1, 2 fall time tIBCKF 15 ns

WCK input 0, 1, 2, SDI0, 1, 2 setup time

tSDIS1 10 ns

WCK input 0, 1, 2, SDI0, 1, 2 hold time

tSDIH1 10 ns

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iii. Word Clock Output


WCK output frequency fOWCK 44.1, 48 kHz

WCK output duty ratio dOWCK 50 %

iv. Audio Output


BCK output frequency fOBCK 64×fOWCK ー

BCK output duty ratio dOBCK 50 %

BCK output rise time tOBCKR CL=20pF 15 ns

BCK output fall time tOBCKF CL=20pF 15 ns

WCK output，SDO0 delay time tSDOD CL=20pF -45 45 ns

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■ Package Dimension

YSS950

Documents

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