Cell-Based IC Design Concepts
Graduate student: Yu-Fan Lai (賴昱帆)Advisor: Prof. Yeong-Kang Lai
Multimedia & Communication IC Design Lab, NCHU-EE
2009/11/19
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Outline
Introduction to IC designIntroduction to IC designCell-based IC design flow conceptDesign flow example Lab
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IC Design and Implementation
Idea
Chip
[1] Yu-Wen Huang , et al., “A 1.3TOPS H.264/AVC single-chip encoder for HDTV applications,” GIEE, NTU, ISSCC2005
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Transform/scal./quant.
motionestimation
Entropycoding
Input videosingal
predictionerror
motionvector
Control data
texturecoding
motioncoding
-
+
Scaling &inv. transform
Deblockingfilter
Split intomacroblock
Coder control(Rate Control & R-D Optimization)
Decoder
Outputvideo signal
Buffer
motioncompensation
Intra-frameprediction
Intra/Inter
System Spec.
[1] Yu-Wen Huang , et al., “A 1.3TOPS H.264/AVC single-chip encoder for HDTV applications,” GIEE, NTU, ISSCC2005
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Algorithm Analysis and Architecture Design
Algorithm level
Architecture level
Transform/scal./quant.
motionestimation
Entropycoding
Input videosingal
predictionerror
motionvector
Control data
texturecoding
motioncoding
-
+
Scaling &inv. transform
Deblockingfilter
Split intomacroblock
Coder control(Rate Control & R-D Optimization)
Decoder
Outputvideo signal
Buffer
motioncompensation
Intra-frameprediction
Intra/Inter
[1] Yu-Wen Huang , et al., “A 1.3TOPS H.264/AVC single-chip encoder for HDTV applications,” GIEE, NTU, ISSCC2005
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IME
FME
LumaRef0Pels
SRAMs
Luma Ref1-3 Pels SRAMs
Luma Ref1-3 Pels SRAMs
IP
EC
DB
SRAMs
SRAMs
SRAMs
Cell-Based ASIC
Fixed blocks (Macros)
Standard-cell area
[1] Yu-Wen Huang , et al., “A 1.3TOPS H.264/AVC single-chip encoder for HDTV applications,” GIEE, NTU, ISSCC2005
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Outline
Introduction to IC designCellCell--based IC design flow conceptbased IC design flow concept
Design flowDesign flowHDLHDLStandard cell libraryStandard cell library
Design flow example Lab
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Cell-Based Design FlowSpecification
SPW/CoCentric
RTL Coding
Functional VerificationVerilog-XL, ModelSim
Logic SynthesisAmbit, Synopsys
Timing VerificationVerilog-XL, ModelSim
Place & RouteSoc Encounter ,
IC Compiler
Post SimulationTimeMill, Star-Sim
PrototypingFPGA, Aptix
System intergration and S/W test
Debussy
Debussy
Cell Library(Avant! 0.18um/Artisan 0.13um/Faraday
90nm)
RTL Coding & Functional Verification
Logic Synthesis & Gate-level Verification
R&R & Post-layout Simulation
RTL Level
Gate Level
TransistorLevel
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Verilog HDL vs. VHDL
vital
System
Algorithm
RTL
Logic
Gate
Verilog
VHDL
Synthesizable RTL Code
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Standard Cell Library
Core cells (for random logic)Combinational elementsSequential elements
I/O cellsInputOutputPower/ground
Hard macro generators (for regular logic)RAMROMRegister fileHard IP
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General Core Cells
Combinational cellsBuffers - buffer, inverted buffer, balanced buffer, 3-state buffer, clock bufferGates - AND, OR, NAND, NOR, XOR, XNOR, …, etcAdders / Multiplexers
Sequential cellsFlip-flopsLatchesScan flip-flops / scan latches
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General I/O Cells
I/O padsCMOS, TTLInput only, output only , bi-directionalw/wo pull-up/pull-down resister, 3-stageAnalog input pads
Power padsAC padDC padCore pad
Special padsCrystal oscillator pads, core-driven clock buffer pads
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Memory Compilers
Synchronous/Asynchronous SRAM Synchronous/Asynchronous SRAM compilercompiler
Single-port – one read or writeTwo-port – one read and one write simultaneouslyDual-port – two read or write simultaneously
RegisterRegister--File compilerFile compiler (TSMC 0.13m/ 0.18m only)
Single-port – one read or writeTwo-port – one read and one write simultaneously
ROM compiler (TSMC 0.13m only)
Please Read Documents & Datasheet First !!!
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CIC Provided Cell Libraries (1/2)
Avant! 0.35m cell librariestsmc 0.35m 1P4M CMOS process Not support now/avanti/CIC/Compass06/CIC_CBDK35_V3
Artisan 0.25m cell librariestsmc 0.25m 1P5M CMOS process Not support now/avanti/CIC/Artisan25
TSMC 0.35m polycide cell librariestsmc 0.35m 2P4M process/avanti/CIC/CBDK035_TSMC_TSMC
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CIC Provided Cell Libraries (2/2)
TSMC/Artisan 0.18TSMC/Artisan 0.18m cell librariesm cell librariestsmc 0.18m 1P6M CMOS process/avanti/CIC/CBDK018_TSMC_Artisan
TSMC/Artisan 0.13TSMC/Artisan 0.13m cell librariesm cell librariestsmc 0.13m 1P8M CMOS process Support ARM 922T/avanti/CIC/CBDK013_TSMC_Artisan
UMC/Faraday 90UMC/Faraday 90nnm cell librariesm cell librariesumc 90nm 1P9M CMOS process/avanti/CIC/CBDK90_UMC_Artisan
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Outline
Introduction to IC designCell-based IC design flow concept IP design conceptDesign flow exampleDesign flow example
EDA tools will be used in this courseEDA tools will be used in this courseDesign flow exampleDesign flow example
Lab
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EDA Tools ─ RTL Level
SimulatorVerilog XLVerilog XLNC VerilogModelSim
LinterDebussy nLintDebussy nLintSynopsys LEDA
Verification (code coverage)TransEDA VNTransEDA VN--Cover & VNCover & VN--OptimizeOptimize
DebuggerDebussyDebussy
nWave – Waveform viewer
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EDA Tools ─ Gate Level
Logic synthesisLogic synthesisSynopsys design compilerSynopsys design compiler
Design compiler (dc)Design compiler (dc)Design vision (dv) Design vision (dv) –– synthesis GUIsynthesis GUIDesign vision xg mode (dvDesign vision xg mode (dv--xg) xg) –– synthesis GUIsynthesis GUI
Design for testability (DFT)Synopsys DFT compiler for scan chainSynopsys DFT compiler for scan chainSynopsys TetraMax for ATPG patternSynopsys TetraMax for ATPG patternSynTest for memory BIST
STA & Power AnalysisPrimeTimePrimePower
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EDA Tools ─ Physical Design
Auto place&route (APR) toolCadence SOC EncounterCadence SOC EncounterSynopsys IC Compilier
DRC/LVSDRC/LVSCalibreCalibre DRC/LVSDRC/LVS
Post layout gate-level simulationPost layout transistor-level simulation
Nanosim
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Design Flow ExampleRTL Code
IndividualUnit
Correct?
Motion EstimatorRTL Verification
Correct?
Yes
No
No
Yes Motion Estimatorwith DFT Gate
Level Verification
Correct?
No Yes
Motion EstimatorPost-layout Gate LevelVerification
Correct?
Yes
No
Verilog-XLLEDA, nLint
Debussy nWave
Verilog-XLLEDA, nLint
Debussy nWaveTransEDA VN
Verilog-XLSynopsys Design Compiler
Synopsys DFT CompilerTetraMax
Verilog-XLCadence SOC Encounter
Synopsys AstroCalibre DRC/LVSCadence Virtuoso
P&R
Motion EstimatorPost-layout Simulation
Nanosim
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Outline
Introduction to IC designCell-based IC design flow concept IP design conceptDesign flow exampleLabLab
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Reference
1. Yu-Wen Huang, Tung-Chien Chen, Chen-Han Tsai, Ching-Yeh Chen, To-Wei Chen, Chi-Shi Chen, Chun-Fu Shen, Shyh-Yih Ma, Tu-Chih Wang, Bing-Yu Hsieh, Hung-Chi Fang,and Liang-Gee Chen, “A 1.3TOPS H.264/AVC single-chip encoder for HDTVapplications,” IEEE Solid-State Circuit Conference., pp. 128-130, Feb. 2005
2. 國家晶片系統設計中心, “CIC訓練課程: Cell-Based IC Design Kit Training Manual,”Feb. 2005