GaN系電子デバイス
水谷孝
名古屋大学工学研究科
ワイドギャップ半導体スクール2007.11.3
内容
• GaNの特徴
• 電子輸送特性と電流利得遮断周波数
• 電流コラプス
• 過渡応答と電流DLTS• SiNパシベーションとMISHEMTs• ノーマリオフFET
GaNの特徴、電子輸送特性と電流利得遮断周波数
AlGaN
GaN
G
PSP
PSP
PPE
S D
AlGaN/GaN HEMTs
Wide gap: 3.4 eVHigh peak velocity: 2.8 x 107 cm/sPolarizationHigh 2DEG density: 1x 1013 cm-2
Breakdown field: 3 MV/cm
Charge neutrality: surface donor
J. Ibbetson et al. Appl. Phys. Lett. 77 (2000) 250
分極のAl組成依存性
O. Ambacher et al. J. Appl. Phys. 85 (1999) 3222
移動度
n-GaN
25,3815
50
106
3 nm
電子移動度の温度依存性
1.極性光学フォノン散乱 a/T2+b/T6
2.音響フォノン散乱(変形ポテンシャル、ピエゾ分極) T-1
3.イオン化不純物散乱(遠隔) 低温でT依存なし、 nS-(1-1.5)(律則移動度: 4.5E5 cm2/Vs)
4.界面ラフネス散乱 低温でT依存なし n2に比例して増加5.(無秩序)合金散乱 低温でT依存なし n2に比例して増加nS
I. Smorchkova et al. J. Appl. Phys. 86 (1999) 4520
AlN中間層による合金散乱の抑制
L. Shen et al. IEEE EDL 222 (2001) 457
0
1
2
3
0 1 2 3
電子
速度
(×10
7 cm/s )
電界 (×10 5 V/cm)
GaN
GaAsSi
SiC
電子速度の電界依存性
光学フォノンエネルギ大(90meV:GaAs系の3倍))→
飽和速度大(約1.7倍)
結合力大が多くの特徴を作っている。
光学フォノンエネルギー、エネルギバンドギャップ、エッチング速度 etc
0 10 205
10
15
20
187℃
103℃
23℃
全遅
延時
間( p
s )
1/ ドレイン電流(mm・A-1)
0 5 10 15 200
5
10
15
23℃103℃187℃
電流利
得遮
断周
波数
(GH
z)
ドレイン電圧(V)
fTおよび全遅延時間のバイアス依存性
真性電流利得遮断周波数、fT: gm0/2πCg
0 50 100 150 2000
5
10
15
Cut
off F
requ
ency
, fT (
GH
z )
Temperature ( ℃ )
0.0
0.5
1.0
1.5
( 107 cm
/s )
←fT
veff→
Effe
ctiv
e E
lect
ron
Vel
ocity
, vef
f
50 100 150 2000.00
0.25
0.50
0.75
1.00
veff移動度
veff↑
電界( kV/cm )180 100 50 25 15 室
温の値で規格化した電子速度、移動度
温度(℃) ℃
fT, veffの温度依存性
M. Akita et al. Phys. Stat. sol (a) 188 (2001) 207
ddcceff
i vl τττ ++=
( )∫=l
xvdx
0τ
( )DSGDDS
DS
m
GDGS
m
GDGS
T
RRCR
RRg
CCg
CCf
+++
⋅+
++
==002
1π
τ
遅延時間解析
真性遅延時間 τi 寄生抵抗に起因 ミラー効果に対応
速度の遅い(低電界)領域の寄与大
いずれもコンタクト抵抗の大きいGaN系デバイスでは効く
Without recess
Two-step recess
Inclined recess
Evaluation for 4 types of devices.(Electric field, Electron velocity and Device characteristics)
i-AlGaN 50 nm
i-GaN
DS
2μm1μmG
1μm 2μm1μmG
1μm
i-AlGaN 50 nm
i-GaN
DSi-AlGaN 50 nm
i-GaN
2μm1μmG
1μm
DS
Well recess
2μm1μmG
1μm
i-AlGaN 50 nm
i-GaN
DS
used in device simulationDevice Structure
Y. Aoi et al. Jpn. J. Appl. Phys. 45 (2006) 3368
0
2
4
6
8
10
0 1 2 3 4
pote
ntia
l (V
)
Distance (μm)
VDS
= 10 V
VG= Vth + 2 V
● without recess● well recess● two-step recess● inclined recess
Source Drain
Gate
Potential Distribution
Potential drop under the gate becomes larger for the device with inclined-gate-recess.
-10
0
10
20
30
108 109 1010 1011
Gai
n (d
B)
● with recessfT= 7.94 GHz
VDS
=10V
● without recessfT= 6.40 GHz
Frequency (Hz)
Cut-off Frequency
Higher fT was obtained for the device with inclined-gate-recess structure.
ゲート長:2μm
ゲート長60 nmの微細T型ゲート
短チャネル効果抑制:AlGaN障壁層を薄くする寄生抵抗を小さくする:SiN表面保護膜形成
高いfTの実現:152 GHz東脇(情報通信研究機構)
電流コラプス
-202468
101214
0 5 10 15 20
I D (m
A)
VDS
(V)
ゲート長:1.5μmゲート幅:20μm
VGS
step:1 V
VGS
=3 V
VGS
=-3 V
電流コラプス
ドレインに電圧に依存した特性 ゲートバイアスストレスによるID減少
0
2
4
6
8
10
-5 -4 -3 -2 -1 0 1I D
(mA
)
VGS (V)
VDS = 10 VV
GS; -5 > +1 > -5 (V)
before stress
after stress(10 s @ P)P
Drain Current Collapse by Gate Bias Stress
・Current collapse・Counter clockwise hysteresis
Carriers from the gate
・No VTH shift・No side-gate effect
Deep levels in AlGaN and in the buffer : X
Surface states: ○0
2
4
6
8
10
-5 -4 -3 -2 -1 0 1
I D (m
A)
VGS (V)
VDS = 10 VV
GS; -5 > +1 > -5 (V)
before stress
after stress(10 s @ P)P
T. Mizutani et al. IEEE Trans. ED 50 (2003) 2015
Effect of Illumination Position
0
2
4
6
8
10
-5 -4 -3 -2 -1 0 1
I D (m
A)
VGS (V)
VDS
= 10 V
VGS
; -5 > +1 > -5 (V)
tH=10 sP
Q1
Q2
illuminating on
D-G
G-S
G-D: Large current recovery
Surface states on G-D region
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
-4 -3 -2 -1 0 1 2 3 4
I D(Q
) (m
A)
x (μm)
VDS
= 10 V, VGS
= 1 V
DGS
resolution
Dependence of the Collapsed Current on the Stress Voltage
Threshold-like behavior of the current collapse
0
2
4
6
8
10
-7 -6 -5 -4 -3 -2 -1 0 1
I D(Q
) (m
A)
VG_Stress
(V)
VDS = 10 V
Importance of a large field for injecting electrons from the gate
Transient of the Current Recovery
Stress: VGS = -5 V, 10 s
Long recovery time
4.0
4.5
5.0
5.5
6.0
6.5
7.0
0 50 100 150 200 250 300
I D (m
A)
Time (s)
90 %
35 s
VDS
= 10 V
VGS
= 0 V
コラプスのストレス時間依存性
0
2
4
6
8
10
0 5 10 15 20 25 30 35 40
I D(Q
) (m
A)
tStress (s)
VDS
= 10 V
VG_Stress
= -5 V
Long injection time:small surface electron mobiity
Current Collapse Model
1. Electron injection from the gate & capture by the surface states.
2. Virtual gate.3. Long recovery time.
GaN
Source Gate Drain
RS (V -V )GS th
AlGaN
-- - -- - - -0 V -5 V 10 Vvirtual gate
EC
EV
ET1ET2
3.4 eV
Gate
捕獲
放出
Drain
IDB
表面伝導のモデル
ホッピング
表面における電子の伝導
捕獲は放出に比べ、時間が短いため遅い過渡応答には寄与しない
表面での電子移動が遅い
VGS
VDS
S G D
G D
φS Measurement by KFMcantilever
Scan speed2 s/800 nm (H. direction)
126 s/800 nm (V. direction)
VDS= 5 VVGS= 0 V
2 s
64 lines 126 s
LGS = 2 μmLGD = 2 μm Measurements before & after the bias stress.
VGS=-10 V, VDS=5 V, 120 s
KFM: electrostatic force
0.7
0.8
0.9
1
1.1
1.2
1.3
Distance (nm)
Potential (V)
Time (s)0
0 400 800
30 60 90 120
after stress0.7
0.8
0.9
1
1.1
1.2
1.3
Potential (V)
Time (s)0 30 60 90 120
0 400 800
Distance (nm)
GG
Potential Profile / Time Dependenc (G-D)300 nm 300 nm
90 %
75 s
Nakagami et al. Appl. Phys. Lett. 85 (2004) 6028
W/O stress
0.7
0.8
0.9
1
1.1
1.2
1.3
Distance (nm)
Potential (V)
Time (s)0
0 400 800
30 60 90 120
VDS = 5 V
VGS = 0 V
5.0
4.5
4.0
5.5
ID (mA)
Time Dependence of ID & Potential
Time Dependence of ID & Potential
Drain current
Surface potential
Times necessaryto recover to 90% :
75s for surface potential50s for drain current
KFM Image
Low Potential Regions
Pits
Correlation
Y. Eguchi et al. Jpn. J. Appl. Phys. 40 (2001) L589
HEMTのEL分布の比較
GaN HEMTのEL GaAs HEMTのEL
ドレイン電極端で発光を観測 ゲート電極端(ドレイン側)で発光を観測
T. Nakao et al. Jpn. J. Appl. Phys. 41 (2002) 1990
高電界領域形成に及ぼす表面電荷の影響
•理想的なHEMT
高電界: ゲート端(空乏層)
•負の表面電荷をもつHEMT
空乏層電荷(+)を補償
高電界: ドレイン端
GaN
Source Gate Drain
AlGaN+ + ++ + +++ + + ++ + + ++ + + ++
-- -- - - - -
2DEG
--- -
Potential
n
-- - ---- -
-- - -- ---
- -
表面準位の影響
-1
0
1
2
3
4
5
6
3 4 5 6
Pote
ntia
l (V)
x (μm)
Gate Drain
0
5
1
3
2
2.5
NS (x1012 cm-2)
表面トラップ密度 (NS) ≿ 3×1012 cm-2
高電界 ドレイン端
表面トラップの影響大
表面トラップの電子(-)が空乏層電荷(+)を補償
チャネル内電位分布の計算結果
Electroluminescence
w/o Si3N4passivation
Si3N4passivation
Change in the EL location by surface passivation suggesting the change in the field distribution.
Y. Ohno et al. Appl. Phys. Lett. 84 (2004) 2184
フィールドプレートによる電流コラプスの抑制
AlGaN
GaN
GS D
フィールドプレート: 電界集中の緩和と
ゲート電極からの電子注入抑制(NEC)
HEMT with Si3N4 Passivation
DrainSi3N4 100 nm
SourceAl0.3Ga0.7N 5 nmn- Al0.3Ga0.7N 10 nmAl0.3Ga0.7N 5 nm
GaN 3 μm
AlN 40 nmSapphire substrate
Gate
0
2
4
6
8
10
-5 -4 -3 -2 -1 0
w/o Si3N4
with Si3N
4
I D (m
A)
VGS
(V)
before stress
after stress
before & afterstress
VDS
= 10 V
電流コラプス/過渡応答抑制はもぐらたたき
深い準位表面準位、界面準位バルク中準位
へのキャリアトラップと放出
1.深い準位の低減2.システムサイドからの要求に合わせた
デバイス設計
過渡応答の評価と解析
Temperature Dependence of the Drain Current Noise
T. Mizutani et al. Jpn. J.Appl.Phys. 42 424 (2003)
1/f
(Noise Power Spectral Density) x Frequency
Frequency Dispersion of GDS
T. Mizutani et al. Jpn. J. Appl. Phys. 42 (2003) 424
2 2.5 3 3.5 4
low-frequency noisedrain condactance
τ×
T2 (s・
K2)
1000/T (1/K)
1
10
102
103
1/τ~σT2exp(-Ea/kT)
0.47 eV0.43 eV
Comparison of Arrhenius Plots
VDS
ATransient current
VG
DLTS
ID DLTS Measurement Setup
T
ID(t1) - ID(t2)
LT
HTt1 t2
t
t
ID(t)
tID(t)
ID(t)
ID Transient
TP= 10 ms VP = 1 V
Ea#1 0.29 eV#2 0.61 eV#3 0.55 eV
Measured Results
Negative peak #2 : Electron trapPositive peak, #1 & #3: Hole-like trap
10
100
1000
104
2 2.5 3 3.5 4 4.5τ・
T2(s・
K2)
1000/T (K-1)
#3#2
#1
-8
-6
-4
-2
0
2
4
100 200 300 400 500 600T (K)
DLT
S S
igna
l, b1
(μ A
)
#1 #3
#2
T. Mizutani et al. phys. Stat. sol. (a) 200 (2003) 195
Negative Peak: Electron Trap
VG: Positive
VG: Negative
VG
ID
EF
EF
ET
ET
Electron capture at bulk traps
Electron emission at bulk traps
正側のピーク: ホールトラップ的
AIDB
VG
tA1
tA2
表面準位での電子の捕獲・放出
表面準位での電子の放出
(a) t A1
S G D S G D
(b) t A2
IDはAのように徐々に増加
S G D
(c) t B1 (d) t B2
S G D
表面準位での電子の注入・捕獲
IDBB
VG
tB1
tB2
正側のピーク: ホールトラップ的表面準位での電子の捕獲・放出
IDはBのように徐々に減少
Comparison of Arrhenius Plots
1
10
100
1000
104
0 2 4 6 8 10
τ・T2
(s・
K2 )
1000/T (K-1)
#1
#2#3
[1]
[2]
[1] P. Hacke JAP 0.59 eVHVPE/MOCVD GaN
[2] W. Lee APL 0.49 eVMOCVD GaN
[3]
[4]
#2: Commonly observed defects in GaN
[3] T. Mizutani 0.49 eV LF noise/f-dispersion
[4] H. Makihara 0.31eVLF noise
#1: Close to the surface-related LF noise
SiNパシベーションとMISHEMTs
HEMT with Si3N4 Passivation
DrainSi3N4 100 nm
SourceAl0.3Ga0.7N 5 nmn- Al0.3Ga0.7N 10 nmAl0.3Ga0.7N 5 nm
GaN 3 μm
AlN 40 nmSapphire substrate
Gate
0
2
4
6
8
10
-5 -4 -3 -2 -1 0
w/o Si3N4
with Si3N
4
I D (m
A)
VGS
(V)
before stress
after stress
before & afterstress
VDS
= 10 V
-4
0
4
8
12
100 200 300 400 500 600
DLT
S Si
gnal
, b1 (μA
)
T (K)
-4
0
4
8
12
100 200 300 400 500 600T (K)
DLT
S Si
gnal
, b1 (μA
)
Effects of Si3N4 Passivation
w/o Si3N4 with Si3N4
Surface state related hole-trap-like signal disappeared.
Device Structure
Lg=1.5 µmWg=20 µm
・Si3N4 filmECR sputtering
( µ-wave: 500 W, RF: 500 W )
Gate insulator &Surface Passivation film
n=6×1018 cm-3DrainSi3N4 (10 nm)
Source
Al0.3Ga0.7N 3 nm
n- Al0.3Ga0.7N 7 nm
Al0.3Ga0.7N 3 nm
GaN 3 µm
AlN 40 nm
Sapphire substrate
Gate
M. Ochiai Jpn. J. Appl. Phys. et al. (2003) 2278
IG-VGS Characteristics
10-13
10-11
10-9
10-7
10-5
-8 -6 -4 -2 0 2
I G (A
)
VGS
(V)
w/o Si3N
4
with Si3N
4
・Gate leakage current decrease aboutthree orders of magnitude.
ゲートリーク電流
温度依存性なし→トンネル電流
C2F6プラズマ処理によるゲートリークの減少とVTシフト(1.2 V)
S. Mizuno et al. Jpn. J. Appl. Phys. 41 (2002) 5125
H. Hasegawa et al. J. Vac. Sci. Technol. B 21 (2003) 1844
Thin surface barrier model
-202468
101214
0 5 10 15 20
I D (m
A)
VDS
(V)
ゲート長:1.5μmゲート幅:20μm
VGS
step:1 V
VGS=3 V
VGS
=-3 V
電流コラプス
HEMT ID-VDS特性 MIS-HEMT(P-CVD法)ID-VDS特性
MIS構造により電流コラプスの抑制
SiNx膜が表面保護膜の効果
-202468
101214
0 5 10 15 20I D
(mA
)V
DS (V)
ゲート長:1.5μmゲート幅:20μm
VGSstep:1 VVGS=3 V
VGS=-7 V
ID-VGS Characteristics after the Gate Bias Stress
0
1
2
3
4
5
6
7
8
-5 -4 -3 -2 -1 0
before stress
after stress
I D (m
A)
VDS
= 10 V
VGS
(V)
before/after stress
MIS-HEMTHEMT
・Drain current was measured after a stress of VGS = -5 V for 10 s
・Suppression ofthe current collapse in MIS-HEMTs.
Si3N4 film:・Gate insulator・Passivation film
The Effect of Si3N4 Passivation on LF Noise
-200
-180
-160
-140
-120
-100
-80
1 10 100 1000 104 105 106
Noise power spectral density
(dBm/Hz)
frequency(Hz)
∝1/f
∝1/f2
w/o Si3N4
VDS=10V
VGS=0V
with Si3N4
M. Ochiai Jpn. J. Appl. Phys. et al. (2003) 2278
HfO2 AlGaN/GaN MISFETs
020406080
100120140160180
-5 -4 -3 -2 -1 0 1 2 3
w/o HfO2
as fabricated300℃350℃SiNx MIS-HEMT
g m(m
S/m
m)
VGS
(V)
VDS
(10V)
SiNx
w/o, 300 °C
as fab, 350 °C
Ni/Pt/Au
(0001) Sapphire substrateAlN buffer
i-GaN 3μm
Ti/Al
n-Al0.30Ga0.70N 7 nmi-Al0.30Ga0.70N 3 nm
HfO2(10nm)
i-Al0.30Ga0.70N 3 nm
Large transconductance in HfO2 MISFET
ノーマリオフ型FET
AlGaN/GaN HEMTs
Background
Suitable for high-power & high-frequency applications.
-Issues-
・Large parasitic resistance・Precise etching control
Normally-off HEMTs are required for implementing high-power switching system.
W. Saito et a.l, IEEE Trans. Electron Devices, 53 (2006) 356
RC
i-GaN
Source Drain
Gate RC
RGDRGS RREC RREC
10
8
6
4
2
0-1.6 -1.2 -0.8 -0.4 0 0.4
RO
NA
(mΩ
cm2 )
Threshold Voltage Vth (V)
■:Experiment (Wg=3 mm)●:Experiment (Wg=0.6 mm)Lgd=5 μm
AlGaN
・Small forward VGS
ECEF
AlGaN GaNMetal
GaN
ECEF
InGaN AlGaNMetal
+ -
Polarization-induced field in the InGaN cap layer is expectedto raise the conduction band.
AlGaN
GaN
InGaN
G
PSP
PSP
PSP
PPE
PPE
S D
AlGaN/GaN HEMTs with Thin InGaN Cap Layer
T. Mizutani et al. IEEE EDL 28 (2007) 549
-0.08
-0.06
-0.04
-0.02
0
0.02
0 0.1 0.2 0.3 0.4 0.5P
olar
izat
ion
(C/m
2 )In-composition
InxGa1-x
N/GaN
Polarization in InGaN cap layer structure
AlGaN
GaN
InGaN
G
PSP
PSP
PSP
PPE
PPE
S
The piezo-electric polarization (PPE) is much larger than the spontaneous polarization (PSP) in the InGaN cap layer.
D
PSP
PPE+
-
+
Comparison between deviceswith and without InGaN Cap
0
50
100
150
200
-2 -1 0 1 2Gate voltage (V)
Tran
scon
duct
ance
(mS
/mm
) VDS
= 5V
●:w/o InGaN cap□:with InGaN cap (before etching)
0
0.05
0.1
0.15
0.2
0.25
0.3
-2 -1 0 1 2
VDS
= 5V
●:w/o InGaN cap□:with InGaN cap (before etching)
Gate voltage (V)
Dra
in c
urre
nt (A
/mm
)
⊿Vth = 1.9 V
・Confirmation of normally-off operation.・Smaller gmmax: due to a large parasitic resistance caused by the InGaN cap layer in the access region.
Devices with InGaN cap layer
145 mS/mm
85 mS/mm
Transfer characteristics before and after InGaN etching at the access region
0
0.05
0.1
0.15
0.2
0.25
0.3
-1 -0.5 0 0.5 1 1.5 2
VDS
= 5 V●:before etching□:after etching
Gate voltage (V)
Dra
in c
urre
nt (A
/mm
)
0
50
100
150
200
-1 -0.5 0 0.5 1 1.5 2
VDS
= 5 V●:before etching□:after etching
Gate voltage (V)Tr
ansc
ondu
ctan
ce (m
S/m
m)
130 mS/mm
85 mS/mm
before etching : 85 mS/mmafter etching : 130 mS/mm
0
50
100
150
200
-1 -0.5 0 0.5 1 1.5 2
VDS = 5 V●:before annealing□:after annealing
Gate voltage (V)
Tran
scon
duct
ance
(mS/
mm
)
Transfer characteristicsbefore and after annealing
145 mS/mm130 mS/mm
before annealing : 130 mS/mmafter annealing : 145 mS/mm
(250ºC in N2 atmosphere for 20 min)
0
0.05
0.1
0.15
0.2
0.25
0.3
-1 -0.5 0 0.5 1 1.5 2Gate voltage (V)
Dra
in c
urre
nt (A
/mm
)
VDS = 5 V●:before annealing□:after annealing
Ito et al. ICNS 2007
GaN MOSFET Approach
Decrease in input capacitance Decrease in gm
Issue of MOSFET
K. Matocha et al. , IEEE Trans. Electron Devices, 52, (2005) 6
Highest gm_max= 6 mS/mm
HfO2 gate insulator with a large dielectric constant.
Gate metal overlap over S/D electrodes. i-GaN 1 μm
Ti/Pt/Au
n+ n+
Dopant:Mg=2×1017cm-3
Ti/Al/Ni/Au HfO2(100nm)
p-GaN 1 μm
Transfer Characteristics ofEnhancement-Mode MOSFET
-10
-5
0
5
10
15
20
25
30
0 5 10 15 20Gate voltage (V)
Tran
scon
duct
ance
(mS/
mm
)
VDS
= 8V
Vth=8 V, VGS_max=20 VImax=320 mA/mmgm_max=23 mS/mm μFE=70-90 cm2/Vs
Validity of the present MOSFET technologyStill room for improvements in μ and gm
0
10
20
30
40
50
60
70
80
0 2 4 6 8 10
Cap
acita
nce
(pF)
HfO2:50 nm
εr=17.3
Gate voltage (V)0
50
100
150
200
250
300
350
0 5 10 15 20
VDS
= 8V
Gate voltage (V)
Dra
in c
urre
nt (m
A/m
m)
S. Sugiura et al. Electron. Lett. 43 (2007) 952
IG-VGS Characteristics of Enhancement-Mode MOSFET
10-12
10-10
10-8
10-6
10-4
10-2
-10 -5 0 5 10
HEMT
SiO2 MOSFET
HfO2 MOSFET
SiNX MISFET
Gate voltage (V)
Gat
e cu
rrent
(A/m
m)
Lg=2.5 μm
0
1 10-5
2 10-5
0 2 4 6 8 10
HEMT
SiO2 MOSFET
HfO2 MOSFET
SiNX MISFET
Gate voltage (V)G
ate
curre
nt (A
/mm
)
Lg=2.5 μm
HfO2 : better than other dielectrics in respect to the gate leakage current.
p-GaN 1 μm
i-GaN 1 μm
Ti/Pt/Au
n+ n+
Ti/Al/Ni/Au HfO2(100 nm)
i-GaN 3 μm
Ti/Pt/Au
n+ n+
Ti/Al/Ni/Au
i-AlGaN
HfO2(100 nm)
12 nm
2DEG
-idea-high quality interface higher performance
EC
EF
EC
EFmetal HfO2 p-GaN metal HfO2 i-GaNi-AlGaN
AlGaN/GaN Heterostructure
S. Sugiura et alICNS 2007, Las Vegas
0
100
200
300
400
500
600
700
800
0 2 4 6 8 10Drain voltage (V)
Dra
in c
urre
nt (m
A/m
m)
VGS
=9VVGS
= 0~9V, 1Vstep
VGS
= 0V
Lg=2.5 μm
0
100
200
300
400
500
600
700
800
0
50
100
150
200
-2 0 2 4 6 8 10
VDS
= 8V
Gate voltage (V)
Dra
in c
urre
nt (m
A/m
m)
Tran
scon
duct
ance
(mS/
mm
)
I-V characteristics of the fabricated AlGaN/GaN MOSFETs
Vth=3 V ID_max=730 mA/mmgm_max=185 mS/mmμFE=900~1500 cm2/Vs
Vth=8 VID_max=320 mA/mmgm_max=45 mS/mmμFE=70~90 cm2/Vs
Ref. p-GaN MOSFET
Validity of the present MOSFET technology using HfO2 as a gate oxide and AlGaN/GaN heterointerface as a channel
S. Sugiura et al. Electron. Lett. 43 (2007) 952
Fluoride-based plasma treatment
LG = 1.5 μm LDS = 5.5 μm
i-Al0.25Ga0.75N 35 nm
i-GaN
CF4 plasma
S D
Sapphire substrate
Fabrication process1. Isolation, Ohmic contact2. Gate pattern delineation3. Fluoride-based plasma treatment
using CF4 RIE4. Gate electrode formation, Lift-off5. Annealing
Conditions of the plasma treatmentFlow rate:CF4 (30 sccm), Pressure:7.0 Pa
RF power:200 W, Time:90, 120 s
gm-VGS & ID-VGS characteristics
0
20
40
60
80
100
120
140
-8 -6 -4 -2 0 2 4
No treatment90sec120sec
g m [m
S/m
m]
VGS
[V]
VDS:10VLg:1.5μmWg:20μm
0
100
200
300
400
500
600
700
-8 -6 -4 -2 0 2 4
No treatment90sec120sec
I D [m
A/m
m]
VGS
[V]
VDS:10VLg:1.5μmWg:20μm
CF4 plasma Vth (gm-VGS) [V] Vth (ID-VGS) [V]
No treatment –4.7 –3.8
90 s –1.7 –1.2
120 s –0.7 –0.1
DLTS signals
ET1 at 200 K disappeared and ET3 appeared at ~500 K by the plasma treatment
Fluorine atoms formed a new deep level?
Increase of ET3 peak height at deep negative bias
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
100 200 300 400 500 600
w/ow/
DLT
S si
gnal
b1
[pF]
T [K]
ET1 ET2
ET3
-1.2
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
100 200 300 400 500 600
VR = -0.3V
VR = -1.0V
VR = -2.0V
DLT
S si
gnal
b1
[pF]
T [K]
ET3
plasma-treated samplew/ & w/o plasma treatment
ET3 1.51eV 9.9×10−13cm2
Mizuno et al. IWN 2006, Kyoto
Thermal stability
Condition:200°C in a N2atmosphere
Vth shift was not observed even for the devices with plasma treatment.
-5
-4
-3
-2
-1
0
1
0 20 40 60 80 100
Vth
[V]
Keeping time [day]
w/o
w/
オン抵抗と耐圧との関係
10-1
100
101
102
102 103 104
Breakdown voltage (V)
Spe
cific
On-
Res
ista
nce
Ron
A (m
Ωcm
2 )
Si Limit
GaN Limit
Si Super Junction MOSFET
GaN HFET (normally-off)
GaN GIT
Si IGBT (commercial)
SiC Limit
直線は横型FETの計算値
GaN FET
今後の研究開発
1.システムサイドからの要求に合わせたデバイス設計
2.深い準位の低減
高周波応用:ノーマリオン型実用段階
電力応用:ノーマリオフ型が必須更なるオン抵抗低減更なる高耐圧化