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MICROPROCESSORS
(Common to CSE & ISE)
SYLLABUS
Subject Code: 10CS45 I.A. Marks: 25
Hours/Week: 05 Exam Hours: 03
Total Hours: 52 Exam Marks: 100
PART A
UNIT – 1 [7 Hours]
Introduction, Microprocessor Architecture – 1: A Historical Background, the Microprocessor-
Based Personal Computer Systems. The Microprocessor and its Architecture: Internal
Microprocessor Architecture, Real Mode Memory Addressing.
UNIT – 2 [7 Hours]
Microprocessor Architecture – 2, Addressing Modes: Introduction to Protected Mode Memory
Addressing, Memory Paging, Flat Mode Memory Addressing Modes: Data Addressing Modes,
Program Memory Addressing Modes, Stack Memory Addressing Modes.
UNIT –
3 [6 Hours]
Programming – 1: Data Movement Instructions: MOV Revisited, PUSH/POP, Load-Effective
Address, String Data Transfers, Miscellaneous Data Transfer Instructions, Segment Override
Prefix, Assembler Details. Arithmetic and Logic Instructions: Addition, Subtraction and
Comparison, Multiplication and Division.
UNIT - 4 [ 6 Hours ]
Programming – 2: Arithmetic and Logic Instructions (continued): BCD and ASCII Arithmetic,Basic Logic Instructions, Shift and Rotate, String Comparisons. Program Control Instructions:
The Jump Group, Controlling the Flow of the Program, Procedures, Introduction to Interrupts,
Machine Control and Miscellaneous Instructions.
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PART B
UNIT - 5 [6 Hours ]
Programming – 3: Combining Assembly Language with C/C++: Using Assembly Language
with C/C++ for 16-Bit DOS Applications and 32-Bit Applications Modular Programming,
Using the Keyboard and Video Display, Data Conversions, Example Programs.
UNIT - 6 [7 Hours ]
Hardware Specifications, Memory Interface – 1: Pin-Outs and the Pin Functions, Clock
Generator, Bus Buffering and Latching, Bus Timings, Ready and Wait State, Minimum versus
Maximum Mode. Memory Interfacing: Memory Devices
UNIT –
7 [ 6 Hours ]
Memory Interface – 2, I/O Interface – 1: Memory Interfacing (continued): Address Decoding,
8088 Memory Interface, 8086 Memory Interface. Basic I/O Interface: Introduction to I/O
Interface, I/O Port Address Decoding.
UNIT 8 [7 Hours ]
I/O Interface – 2, Interrupts, and DMA: I/O Interface (continued): The Programmable
Peripheral Interface 82C55, Programmable Interval Timer 8254. Interrupts: Basic Interrupt
Processing, Hardware Interrupts: INTR and INTA/; Direct Memory Access: Basic DMA
Operation and Definition.
TEXT BOOK:
1. Barry B Brey: The Intel Microprocessors , 8th Edition, Pearson Education, 2009. (Listed topics only
from the Chapters 1 to 13)
REFERENCE BOOKS:
1. Douglas V. Hall : M icroprocessors and I nterfacing, Revised Editi on, TMH, 2006.
2. K. Udaya Kumar & B.S. Umashankar : Advanced Microprocessors & IBM -PC Assembly
Language Programming, TMH 2003.
3. James L. Antonakos: The Intel M icroprocessor F amily: H ardware and Software Principles and
Applications, Cengage Learning, 2007.
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TABLE OF CONTENTS
UNIT - 1 Introduction, MicroprocessorArchitecture-I.
Page No.
1.1
Introduction: A Historical Background
06-32
1.2 The Microprocessor-Based Personal ComputerSystems.
1.3 The Microprocessor and its Architecture
1.4 Internal Microprocessor Architecture
1.5 Real Mode Memory Addressing.
1.6 Real Mode Memory Addressing.
1.7 Introduction toProtected Mode Memory Addressing
UNIT - 2 Microprocessor Architecture – 2, Addressing Modes2.1 Memory Paging
33-58
2.2 Flat Mode Memory
2.3 Addressing Modes: Data Addressing Modes
2.4 Addressing Modes: continued
2.5 Program Memory AddressingModes
2.6Stack Memory Addressing Modes
2.7Practice of examples
UNIT-3 Programming – 13.1 Data Movement Instructions: MOV Revisited, PUSH/POP
59-97
3.2 Load-Effective Address, String Data Transfers,
3.3 Miscellaneous Data Transfer Instructions
3.4 Segment Override Prefix, Assembler Details.
3.5 Arithmetic and Logic Instructions: Addition, Subtractionand Comparison
3.6 Arithmetic and Logic Instructions: Multiplication andDivision.
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UNIT – 4 : Programming – 2:
4.1 Arithmetic and Logic Instructions (continued): BCD
98-116
4.2 ASCII Arithmetic, Basic Logic Instructions
4.3 Shift and Rotate, String Comparisons.
4.4 Program Control Instructions: The Jump Group,Controlling the Flow of the Program
4.5 Procedures, Introduction to Interrupts
4.6Machine Control and Miscellaneous Instructions.
UNIT – 5 Programming – 3:
5.1 Combining Assembly Language with C/C++
117-123
5.2 Using Assembly Language with C/C++ for 16-Bit DOS Applications
5.3 3 32-Bit Applications Modular Programming,
5.4 Using the Keyboard and Video Display,
5.5 Data Conversions, Example Programs
5.6 Practice of simple examples
UNIT - 6 Hardware Specifications, Memory Interface –
1:
6.1 Pin-Outs and the Pin Functions,
124-144
6.2 Clock Generator
6.3 Bus Buffering and Latching
6.4 Bus Timings
6.5Ready and Wait State
6.6Minimum versus Maximum Mode.
6.7Memory Interfacing: Memory Devices
UNIT - 7 Memory Interface –2, I/O Interface – 1:
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7.1 Memory Interfacing (continued): Address Decoding
145-159
7.2 8088 Memory Interface
7.3 8086 Memory Interface
7.4 Basic I/O Interface: Introduction to I/O Interface
7.5 I/O Port Address Decoding.
7.6 practice
UNIT - 8 I/O Interface – 2, Interrupts, and DMA:
8.1 /O Interface (continued):
160-175
8.2
The Programmable Peripheral Interface 82C558.3
Programmable Interval Timer 8254.
8.4 3 Interrupts: Basic Interrupt Processing.
8.5Hardware Interrupts: INTR and INTA/.
8.6 Direct Memory Access: Basic DMA Operation and
Definition.
8.7 DMA , and practice
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UNIT 1
INTRODUCTION, MICROPROCESSOR ARCHITECTURE – 1
The internal arrangement of a microprocessor varies depending on the age of the design
and the intended purposes of the processor. The complexity of an integrated circuit is bounded
by physical limitations of the number of transistors that can be put onto one chip, the number of
package terminations that can connect the processor to other parts of the system, the number of
interconnections it is possible to make on the chip, and the heat that the chip can dissipate.
Advancing technology makes more complex and powerful chips feasible to manufacture.
A minimal hypothetical microprocessor might only include an arithmetic logic unit
(ALU) and a control logic section. The ALU performs operations such as addition, subtraction,
and operations such as AND or OR. Each operation of the ALU sets one or more flags in a
status register, which indicate the results of the last operation (zero value, negative number,
overflow. or others). The logic section retrieves instruction operation codes from memory, and
initiates whatever sequence of operations of the ALU required to carry out the instruction. A
single operation code might affect many individual data paths, registers, and other elements of
the processor.
As integrated circuit technology advanced, it was feasible to manufacture more and
more complex processors on a single chip. The size of data objects became larger; allowing
more transistors on a chip allowed word sizes to increase from 4- and 8-bit words up to today's
64-bit words. Additional features were added to the processor architecture; more on-chip
registers speeded up programs, and complex instructions could be used to make more compact
programs. Floating-point arithmetic, for example, was often not available on 8-bit
microprocessors, but had to be carried out in software. Integration of the floating point unit first
as a separate integrated circuit and then as part of the same microprocessor chip, speeded up
floating point calculations.
Occasionally the physical limitations of integrated circuits made such practices as a bit
slice approach necessary. Instead of processing all of a long word on one integrated circuit,
multiple circuits in parallel processed subsets of each data word. While this required extra logic
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to handle, for example, carry and overflow within each slice, the result was a system that could
handle, say, 32-bit words using integrated circuits with a capacity for only 4 bits each.
With the ability to put large numbers of transistors on one chip, it becomes feasible to
integrate memory on the same die as the processor. This CPU cache has the advantage of faster
access than off-chip memory, and increases the processing speed of the system for many
applications. Generally, processor speed has increased more rapidly than external memory
speed, so cache memory is necessary if the processor is not to be delayed by slower external
memory.
Microprocessor History and Background
The CPU ("central processing unit," synonymous with "microprocessor," or even simply"processor") is often referred to as the "brain" of the computer.
Choosing the correct processor is vital to the success of your homebuilt computer project.
Here's a little background about the history of microprocessors.
1.1 A Historical Background
In historical background, our aim is to study about the events that led to the
development of microprocessors especially the modern microprocessors, namely, 80x86,
Pentium, Pentium pro, Pentium 3 and the Pentium 4. The historical background can be studied
in three different accounts:
1.The Mechanical Age
2. The Electrical Age
3. The Microprocessor Age
1.1.1 The Mechanical Age: The idea for a system that can compute (calculate) has been
around for a long time, even before the modern electrical and electronic devices came into
existence.
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ABACUS- the Babylonians invented the abacus sometime during 500 BC. The abacus is the
oldest known mechanical calculator. The working mechanism of abacus is quite simple, it used
strings of beads to perform calculations. The abacus was not improved until 1642 when a
mathematician named Blaise Pascal invented a calculator that was constructed of gears and
wheels. Each gear contained 10 teeth that after one complete revolution advanced a second gear
one place. The first practical, geared mechanical machines that could automatically compute
information arrived in the 1800's. This was much before humans knew anything about
electricity or light bulb.(Picture- Abacus).
ANALYTICAL ENGINE- In 1823 The Royal Astronomical Society of
Great Britain commissioned Charles Babbage to produce a programmable calculating machine.
This machine was supposed to generate navigational tables for the Royal Navy. Charles
Babbage was aided by Augusta Ada Byron , the countess of Lovelace. Charles Babbage named
this machine 'Analytical Engine'. The Analytical Engine which he conceived had the following
features- it could store 1000 20 digit decimal numbers and a variable program that could
modify the function of this engine. The input to the analytical engine was through punched
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cards, Charles Babbage borrowed the idea of punched cards from Joseph Jacquard, who used it
to program the weaving machine he invented in 1801. After many years of work, Charles
Babbage realised that it's not possible to make the analytical engine as the machinists of his era
where unable to produce the parts needed for his work. (Picture- Analytical Engine).
1.1.2. The Electrical Age The Electrical age began with the invention of electric motor by Michael Faraday. With
it came a multitude of motor driven adding machines all based on the mechanical calculator
developed by Blaise Pascal. These electrically driven mechanical calculators where common
office equipment until the early 1970's when small handheld calculators began to appear, first
introduced by Bomar.
In 1889 Herman Hollerith developed a punched card for storing data, he also made a
mechanical calculator driven by the electric motors. His machine counted, sorted andcollated(to arrange in proper sequence) the data stored in the punched card. The United States
governmnet commissioned Herman Hollerith to use his punched card system to store and
tabulate information for the 1890 census. In 1896 Herman Hollerith started a company called
the Tabulating Machine Company which developed machines that used punched cards for
tabulation. After a number of merges, this Tabulating Machine Company was formed into the
International Business Machines Corporations now known as the IBM. (Picture- Tabulating
machine developed by Herman Hollerith)
The first electronic calculating machine , something which did not require an electric
motor was developed by the German Inventor named Konrad Zuse. His Z3 calculating
computer where used in aircraft and missile design during World War 2.
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It has been recently discovered through declassification of British Military documents
that the first electronic computer was put into operation in the year 1943 to break secret
German Military codes. This electronic computer was invented by Allan Turing. It used
vacuum tubes to perform calculations. He called this electronic computer Colossus. Colossus
was successful in breaking down the secret German military codes generated by the Enigma
machine. The disadvantage with Colossus was that it was not programmable. Colossus was a
fixed program computer system ,which we call today as a special purpose computer. (Picture-
Konrad Zuse with Z3 computer).
The first general purpose, programmable electronic computer was developed in 1946 at
the University of Pennsylvania. This first modern computer was called the ENIAC (Electronic
Numerical Integrator and Calculator). The ENIAC was a huge machine weighing more than 30
tons and used 17000 vacuum tubes and 500 miles of wires. The ENIAC could perform only
100,000 operations per second. The ENIAC was programmed by rewiring it's circuits. The
ENIAC thrust us into the age of computers. (Picture- ENIAC).
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1.1.3. The Microprocessor Age
Bell labs developed the transistor in 1948, this was closely followed by the development
of Integrated circuits by Jack Kilby of Texas Instruments in 1958. The integrated circuits led to
the development of digital integrated circuits in the 1960's and finally the development of
microprocessor by Intel Corporation in 1971.
Microprocessor is a programmable controller on a chip. The world's firstmicroprocessor is the Intel 4004. It was a 4-bit microprocessor that could address only 4096 4-
bit wide memory locations. (Bit is either a 0 or 1 , 4-bit wide memory location can also be
called a nibble). The Intel 4004 instruction set contained only 45 instructions. It was fabricated
with the then current state of the art P-channel MOSFET technology. Hence it could only
execute 50 Kilo instructions per second.
The 4004 microprocessor was readily accepted by the people ,as a result applications
abounded for this device. It was mainly used in early video games and small microprocessor
based applications. The main problems with the early microprocessors where their speed, word
width and memory size. Intel later released the 4040 microprocessor, this was just an update to
the 4004 with improved speed but it did not have any improvement in word width or memory
size. Other companies, particularly Texas instruments also produced 4-bit microprocessors
(TMS 1000) at this time. The 4-bit microprocessors still survives today in low end applications
like microwave ovens and small control systems.
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In 1971, Intel developed the 8008 microprocessor, an extended 8-bit version of the 4004
microprocessor. This addressed an expanded memory size (16 K bytes) and also had additional
instructions (48 in total) which enabled it's use in more advanced systems. (byte is an 8-bit wide
binary number and K is 1024) .
As engineers demanded more from 8008, it's slow speed , small memory size and
instruction set limited it's use. As an welcoming answer to these demands, Intel developed the
8080 microprocessor, the first modern 8-bit microprocessor in 1973. The 8080 addressed an
expanded memory of 64 K bytes which is four times more than the 8008. The 8080 also could
execute instructions 10 times faster than the 8008. An addition instruction which took 20
microseconds(50,000 instructions per second) in 8008 took only 2 microseconds(500,000
instructions per second) in 8080. It also had additional instructions. The 8080 was compatible
with TTL (Transistor-Transistor logic) hence it made it's interfacing easier.
1.2 The Microprocessor Based Personal Computer System
The introduction of microprocessors had a huge impact in the way we use computers.
Computers that once took large areas where reduced to the size of small desktops. Although
these desktop computers are small and compact, they possess computing power more than that
of the large size computers of the previous generation.
Here, in this section, we are going to learn about the structure of a microprocessor based
personal computer system. The block diagram of a personal computer system is shown in the
figure.
This block diagram also applies to any computer system, from the early mainframe computers
to the modern microprocessor based systems. The block diagram consists of three main blocks,
connected to each other with the help of buses.
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Figure 1.2 The memory map of a personal computer.
It should be noted that the Extended memory system is not available in those computers
based on 8086 or 8088. In these old computers the TPA and System area exists but not the
Extended memory system. The TPA is of size 640 Kb and System area is of size 384Kb. The
TPA and System area together forms the real or conventional memory which is of size 1024Kb
or 1 Mb. It's called as real or conventional memory because each Intel microprocessor is
designed to function in this area using its real mode of operation.
Those computer systems that uses the any of the microprocessors, Intel 80286 through
Pentium 4, has the 640 Kb of TPA and 384 Kb of system area, In addition , these systems also
have an Extended memory. Hence IBM designates these systems as AT class machines (AT-
Advanced class computer systems). These systems are also called as ISA (Industry standard
architecture) or EISA (Extended ISA).
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The extended memory available in the computer systems using the 80286- 80386SX
microprocessors is 15Mb. While the amount of extended memory available in the computer
systems using 80386DX - Pentium microprocessors are 4095Mb, excluding the 1Mb real or
conventional memory. The Computer systems having Pentium pro - Pentium 4 microprocessors
can have 1Mb less than 4Gb to 64GB extended memory. (Note- Modern day computer systems
based on Pentium 4 systems have an extended memory more than 180Gb.)
Recently, a new bus known as the Peripheral Component Interconnect (PCI) bus has been
introduced in the Pentium- Pentium 4 based systems. The older computers based on 8086/8088
used an 8 bit peripheral bus to interface with 8 bit devices. The ISA machines or AT class
machines which used 80286 or above microprocessors used 16 bit peripheral bus for interface.
The EISA machines that used 80386DX and 80486 microprocessors used 32 bit peripheral bus
for interface. All the new buses were compatible with the older devices. That is, an 8 bit
interface card is compatible with an 8-bit bus , 16-bit bus or a 32 bit bus. Similarly a 16 bit
interface card is compatible with a 16 bit bus and 32 bit bus.
Another bus type found in the 80486 based computer systems is the VESA local bus or VT bus.
This local bus helps to interface disk and video to the microprocessor. Two new buses have
also been introduced, one is the USB or Universal Serial Bus and the other is the AGP (
Advanced graphics port)- The Advanced graphics port transfers data between the video card
and the microprocessor at very high speeds.
The Transient Program area (TPA)
The transient program area or TPA holds the DOS operating system and other programs that control the
computer system. The TPA also holds other active or inactive application programs. We know that the
TPA is 640Kb and since it holds DOS on it a part of this 640 Kb is used up by DOS operating system. Th
size of the TPA available for other application programs is 628Kb if MS-DOS version 7.X is used as the
operating system. The older versions of DOS used to take up large spaces of TPA leaving only less than530Kb for other applications. PC-DOS is another operating system that is found in computer systems.
Both PC-DOS and MS-DOS are compatible with each other, hence both functioned similarly with
application programs. Windows and OS/2 are other operating systems compatible with DOS and allows
DOS programs to execute.
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Figure 1.3 The memory map of the TPA in a personal computer.
The memory map of the TPA is shown in the figure. The memory map shows how different
areas of the TPA are allotted to the system programs, data and drivers. To the left of each area
is a hexadecimal number that shows the memory address that begin and end each data area.
1. Interrupt Vectors - The interrupt vectors which occupy the area between 00000 and 00400
is responsible for accessing various features of the DOS, BIOS and other application programs.
2. BIOS communication area and DOS communication area - BIOS is nothing but Basic
Input/Output System. BIOS is a collection of programs that is stored in the ROM or flash
memory that is used to control the Input/Output devices that is connected to the computer
system. The BIOS and DOS communication areas have transient data that can be used by
programs to access the I/O devices or other parts of the computer system.
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3. IO.SYS - The IO.SYS is a program that loads into the TPA from the disk when the computer
system using MSDOS or PCDOS are switched ON. The programs in the IO.SYS enables the
DOS programs to use the keyboard, the display, printer and other I/O devices.
4. MSDOS - MSDOS occupies two parts of the TPA. One is at the top of TPA which is
considerably small and 16 bytes in length. The other is at the bottom and is larger. The memory
size occupied by the DOS depends on the version of the DOS installed. Older versions usually
needed larger areas of TPA compared to the newer versions.
5. Device Drivers- Drivers are those files with an extension .SYS such as MOUSE.SYS.
Drivers are programs that control the installable devices like mouse, hand scanner and also
other installable application programs. The size of the driver and the number of drivers vary
from one computer to the another.
6. COMMAND.COM- The COMMAND.COM helps to control the computer system using
the keyboard when operated in DOS mode. The COMMAND.COM program processes the
DOS commands as they are typed from the keyboard.
7. Free TPA- The free TPA holds the active DOS application programs. These DOS
application programs can be exemplified as the word processor , spreadsheet and CAD
programs. In addition to these, free TPA also holds the TSR (Terminate and Stay Resident)
programs. These remain in the free TPA in an inactive state until initiated by a hot-key or an
interrupt. An example of TSR is the calculator program that is activated upon the ALT+C
hotkey.
SYSTEM AREA
The System area which is smaller than the TPA is considerably important. It contains programs
for data storage and these programs are stored in ROM or flash memory and also in some areas
of the RAM. The system area map is shown in the figure.
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Figure 1.4The system area of a typical personal computer.
On the left side memory addresses of the particular regions are given in hexadecimal
format. The first area of the system space extends from A0000H to C7FFFH and has the video
display RAM and video control programs. The Video display RAM is stored in two parts, first
from A0000H to A7FFFH and is for the graphical data, second from B0000H to B7FFFH and
stores the text data. The video BIOS contains programs that control the video display of the
computer and is located on ROM or falsh memory. It's area in system space is from C0000H to
C7FFFH. The size and amount of the memory used depends upon the type of video display
adapter used.
The area C8000H - DFFFFH is free system area and is called the open system area. It is mostly
used as the extended memory system in PC and XT machines ( PC and XT machines means
those computers based on 8086/8088 microprocessor) and as an upper memory system in AT
class machines (Computers using 80286 or above microprocessors).
Memory locations E0000H-EFFFFH contains the cassette BASIC language on ROM found in
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the older IBM based systems. In almost all the newer systems this particular area is kept open
or free and is also used as RAM to aid the faster operation of DOS application programs.
The system area F0000H to FFFFFH is used by the System BIOS ROM, but this System BIOS
ROM only operates the I/O devices and is not responsible for the controlling of the video
display system which is done by the separate system BIOS ROM at the location C0000H. The
system BIOS at the top is divided into two parts, first part is in the area F0000H to F7FFFH and
contains programs that set up the computer. The second part contains procedures that control
the I/O devices.
MICROPROCESSOR
Microprocessor can be called as the heart of the microprocessor based personal computersystem. The microprocessor is also known by the names CPU or Central Processing Unit and
controls the working of the computer system. The microprocessor connects to the memory and
I/O devices through the buses.
The microprocessor follows three simple steps in its working-
1. Transfers data from memory to itself or to the I/O devices.
2. Performs arithmetic and logical calculations.
3. Performs a program via simple decisions.
Even though these processes are simple, the microprocessor is able to solve all types of
problems using this approach. The strength of the microprocessor lies in its ability to execute
millions of instructions per second from the software or programs. Software and programs are
nothing but a collection of instructions. These software or program is stored in the memory.
This stored program concept makes the microprocessor or in the main, a computer system itself
very efficient.
The arithmetic and logical instructions executed by the microprocessor are
1. Addition2. Subtraction3. Multiplication4. Division5. AND6. OR
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7. NOT8. NEG9. Shift10. Rotate
Data is stored in the memory or the internal registers. The width of the data is either a byte (8- bits), word (16-bits) or a double word (32-bits). Only the 80386 and above versions are able toexecute all three. 8086 to 80286 could directly manipulate 8-bit and 16-bit data but not 32-bit
data.
A Co-processor called the numeric processor is with the 80486 to aid in arithmetic calculationsdealing with floating point arithmetic. This numerical processor was an additional component
in the older 8086- 80386 processors.
1.3 The Microprocessor and its Architecture: Internal
Microprocessor ArchitectureThe Microprocessor Called the CPU (central processing unit).The controlling element in a
computer system. The controlling element in a computer system. Controls memory and I/O
through connections called buses.
* buses select an I/O or memory device, transfer data between I/O devices or memory and the
microprocessor control I/O and memory systems microprocessor, control I/O and memory
systems
* Memory and I/O controlled via instructions stored in memory, executed by the stored in
memory, executed by the microprocessor.
Microprocessor performs three main tasks:
◦ data transfer between itself and the memory or I/O systems
◦ simple arithmetic and logic operations
◦ program flow via simple decisions
Power of the microprocessor is capability to execute billions of millions of instructions per
second from a program or instructions per second from a program or software (group of
instructions) stored in the memory system.
◦ stored programs make the microprocessor and computer system very powerful devices.
Another powerful feature is the ability to make simple decisions based upon numerical
◦ a microprocessor can decide if a number is zero, positive and so forth positive, and so forth
These decisions allow the microprocessor to modify the program flow so programs to modify
the program flow, so programs appear to think through these simple decisions.
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The block diagram of 8086 CPU architecture is shown in the figure.
Figure 1.5 8086 CPU Architecture Data registers- The registers AX, BX, CX and DX are called as the data registers. They are 16
bits wide and can store both the operands and the results. Each of the data registers can either
be accessed as a whole or the higher byte and the lower byte can be accessed separately.
Example- The whole 16 bits in the register AX can be used together or the higher byte and
lower byte can be accessed separately as AH and AL. The registers BX, CX and DX also are
used in other functions in addition as being used as the arithmetic registers.
BX is used as a base register in address calculations.
CX is used as an implied counter by some instructions.DX is used to hold the I/O address during some I/O operations.
Pointer and Index registers- The pointer and index group include the SP, BP, SI, DI and IP.
The SP and IP are essentially the stack pointer and instruction pointer. The instruction pointer is
also called as the program counter. The complete stack and instruction address is formed by
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adding the contents of the SP and IP with the contents in CS and SS. BP or base pointer is used
to address the beginning of a stack. It is used in combination with other registers and/or with a
displacement. SI and DI are the index registers, they are used in combination with the BX or
BP and/or a displacement. The SP and BP can be used to store the operands but not the IP.
Formation of Effective address (EA)- The data address formed by adding together, a
combination of ,BX or BP register contents, SI or DI register contents and a displacement is
called as an effective address or offset.
Displacement- The word displacement is used to indicate any quantity that is added to the
register contents to form an effective address.
Segment registers- The segment registers are CS, SS, DS and ES. The registers that are used
for addressing, SP, BP, SI, DI and IP are 16-bits wide and hence the effective address or offset
will be 16 bits wide but the address that is required on the address bus called the physical
address is 20 bits wide.
Figure 1.6 Formation of physical address
Formation of physical address- We have seen that the address required on the address bus is 20
bits wide but a problem persists as the effective address formed is only 16 bits wide. Hence the
formation of the physical address requires the addition of the contents of the effective address
with the contents of any of the segment registers. To generate the extra 4 bits , we have to
append four 0 bits to the right most digit of the number in the segment register. Example if CS
= 123A and IP = 341B , the physical address formed by the addition of these two will be
3 4 1 B +
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Figure 1.7 overlapping segments
1 2 3 A 0
1 5 7 B B
Overlapping segments- The use of segment registers divides the memory space into
overlapping segments with each segment being 64 Kb wide and beginning at a memory
location that is divisible by 16.
Segment address- Contents of a segment register are called as 'segment address'.
Beginning segment address - Segment address multiplied by 16 is known as 'beginning segment
address'.
Advantages of using segment registers.
1. It allows the memory capacity to be 1Mb even though the individual instructions are only 16
bits wide.
2. It allows the instruction, data and stack portion to be 64Kb wide by facilitating the use of more
than one instruction, data and stack segment.
3. Facilitates the program, data and stack to have separate memory portions.
4. Allows the program and its data to be stored in separate parts of memory while execution of the
program is performed.
8086 PSW
The 8086 PSW is 16 bits, but only 9 of its bits are used. Each bit of 8086 PSW is called a flag.
The flags are divided into two groups, these are conditional flags and control flags. The
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conditional flags reflect the condition involving a previous instruction execution. The control
flags controls the functioning of certain instructions.
Conditional Flags
1. SF (Sign flag)- It is equal to MSB of the result. In 2's compliment a 1 in the MSB shows that
the result is a negative number and a 0 in the MSB shows that the result is a non-negative
number. Hence the sign flag is used to determine whether the result is positive or negative.
2. ZF (Zero flag) - 1 in the zero flag shows that the result is zero and a 0 in the zero flag shows
that the result is a non-zero number.
3. PF (Parity flag) - The PF will become 1 if there are even number of one's in the lower 8-bits of
the PSW.
4. CF (Carry flag) - There are two cases here involving addition and subtraction. In addition a
carry out of the MSB causes this flag to be set. In subtraction if the MSB borrows then this flag
is set.
5. AF (Auxillary carry flag)- In addition the carry out of a bit 3 causes this flag to be set. In
subtraction a borrow by bit 3 causes this flah to be set.
6. OF (Overflow flag)- The overflow flag is set when the result is out of range. More specifically,
in addition, if there is a carry into the MSB and the MSB has no carry out and in addition, if the
MSB needs to borrow and there is no borrow from MSB.
Figure 1.8 8086 PSW
Control flags-
1. DF (Direction flags)- Used by string manipulation instructions. If clear, the string is processed
from the beginning, starting with the first element with the lower address If set, the string is
processed from the higher address to the lower most address.
2. IF (Interrupt enable flag)- If enabled it helps the CPU to recognize the maskable interrupt else
these interrupts are ignored.
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3. TF (Trap flag)- If set a trap is executed after each instruction.
Buses
A common group of wires that interconnect components in a computer, Transfer address, data,& control information between microprocessor memory and I/O between microprocessor,
memory and I/O.
Three buses exist for this transfer of information: address, data, and control.
Figure 1 – 10 shows how these buses interconnect various system components.
The address bus requests a memory location from the memory or an I/O location from the I/O
from the memory or an I/O location from the I/O devices
◦ if I/O is addressed, the address bus contains a 16-bit I/O address from 0000H through
FFFFH.
◦ if memory is addressed the bus contains a memory ◦ if memory is addressed, the bus contains
a memory address, varying in width by type of microprocessor.
64-bit extensions to Pentium provide 40 address pins allowing up to 1T byte of memory to be
pins, allowing up to 1T byte of memory to be devices.
accessed.
The data bus transfers information between the microprocessor and its memory and I/O address
microprocessor and its memory and I/O address space.
Data transfers vary in size, from 8 bits wide to 64 bits wide in various Intel microprocessors.
◦ 8088 has an 8-bit data bus that transfers 8 bits of data at a time
8086 80286 80386SL 80386SX d 80386EX f ◦ 8086, 80286, 80386SL, 80386SX, and
80386EX transfer 16 bits of data 80386DX 80486SX d 80486DX 32 bit ◦ 80386DX, 80486SX,
and 80486DX, 32 bits◦ Pentium through Core2 microprocessors transfer 64 bits of data bits of data.
Advantage of a wider data bus is speed in applications using wide data.
In all Intel microprocessors family members, memory is numbered by byte. Pentium through
Core2 microprocessors contain a 64-bit-wide data bus.
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Control bus lines select and cause memory or I/O to perform a read or write operation to
perform a read or write operation. In most computer systems, there are four control bus
connections:
MRDC (memory read control)
MWTC (memory write control)
IORC (I/O read control)( )
IOWC (I/O write control).
Over bar indicates the control signal is active low; over bar indicates the control signal is
active-low;(active when logic zero appears on control line)
The microprocessor reads a memory location by sending the memory an address through the
sending the memory an address through the address bus.
Next, it sends a memory read control signal to cause the memory to read data.
Data read from memory are passed to the microprocessor through the data bus.
Whenever a memory write, I/O write, or I/O read occurs, the same sequence ensues.
1.4 The Programming Model of 8086• 8086 through Core2 considered program visible.
– registers are used during programming and are specified by the instructions
• Other registers considered to be program invisible.
– not addressable directly during applications programming
• 80286 and above contain program-invisible registers to control and operate protected memory.
– and other features of the microprocessor
• 80386 through Core2 microprocessors contain full 32-bit internal architectures.
• 8086 through the 80286 are fully upward-compatible to the 80386 through Core2.
• Figure 2 – 1 illustrates the programming model 8086 through Core2 microprocessor.
including the 64-bit extensions
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Figure 1 – 11 The programming model of the 8086 through the Core2 microprocessor including
the 64-bit extensions.
Mul tipurpose Registers• RAX - a 64-bit register (RAX), a 32-bit register (accumulator) (EAX), a 16-bit register (AX),
or as either of two 8-bit registers (AH and AL).
• The accumulator is used for instructions such as multiplication, division, and some of the
adjustment instructions.
Intel plans to expand the address bus to 52 bits to address 4P (peta) bytes of memory.
• RBX, addressable as RBX, EBX, BX, BH, BL.
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– BX register (base index) sometimes holds offset address of a location in the memory system in
all versions of the microprocessor
• RCX, as RCX, ECX, CX, CH, or CL.
– a (count) general-purpose register that also holds the count for various instructions
• RDX, as RDX, EDX, DX, DH, or DL.
– a (data) general-purpose register
– holds a part of the result from a multiplication
or part of dividend before a division
• RBP, as RBP, EBP, or BP.
– points to a memory (base pointer) location
for memory data transfers
• RDI addressable as RDI, EDI, or DI.
– often addresses (destination index) string destination data for the string instructions
• RSI used as RSI, ESI, or SI.
– the (source index) register addresses source string data for the string instructions
– like RDI, RSI also functions as a general-
purpose register
• R8 - R15 found in the Pentium 4 and Core2 if 64-bit extensions are enabled.
– data are addressed as 64-, 32-, 16-, or 8-bit
sizes and are of general purpose
• Most applications will not use these registers until 64-bit processors are common.
– the 8-bit portion is the rightmost 8-bit only
– bits 8 to 15 are not directly addressable as
a byte
Special -Purpose Registers• Include RIP, RSP, and RFLAGS
– segment registers include CS, DS, ES, SS, FS, and GS
• RIP addresses the next instruction in a section of memory.
– defined as (instruction pointer) a code segment
• RSP addresses an area of memory called
the stack.
– the (stack pointer) stores data through this pointer
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• RFLAGS indicate the condition of the microprocessor and control its operation.
• Figure 2 – 2 shows the flag registers of all versions of the microprocessor.
• Flags are upward-compatible from the 8086/8088 through Core2 .
• The rightmost five and the overflow flag are changed by most arithmetic and logic operations.
– although data transfers do not affect them
Figure 1.12 The EFLAG and FLAG register counts for the entire 8086 and Pentium
microprocessor family.
• Flags never change for any data transfer or program control operation.
• Some of the flags are also used to control features found in the microprocessor.
• Flag bits, with a brief description of function.
• C (carry) holds the carry after addition or borrow after subtraction.• also indicates error conditions
• P (parity) is the count of ones in a number expressed as even or odd. Logic 0 for odd parity;
logic 1 for even parity.
• if a number contains three binary one bits, it has odd parity
• if a number contains no one bits, it has even parity
• C (carry) holds the carry after addition or borrow after subtraction.
• also indicates error conditions
• P (parity) is the count of ones in a number expressed as even or odd. Logic 0 for odd parity;
logic 1 for even parity.
• if a number contains three binary one bits, it has odd parity; If a number contains no one bits, it
has even parity
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• A (auxiliary carry) holds the carry (half-carry) after addition or the borrow after subtraction
between bit positions 3 and 4 of the result.
• Z (zero) shows that the result of an arithmetic or logic operation is zero.
• S (sign) flag holds the arithmetic sign of the result after an arithmetic or logic instruction
executes.
• T (trap) The trap flag enables trapping through an on-chip debugging feature.
• I (interrupt) controls operation of the INTR (interrupt request) input pin.
• D (direction) selects increment or decrement mode for the DI and/or SI registers.
• O (overflow) occurs when signed numbers are added or subtracted.
• an overflow indicates the result has exceeded
the capacity of the machine
• IOPL used in protected mode operation
to select the privilege level for I/O devices.
• NT (nested task) flag indicates the current task is nested within another task in protected
mode operation.
• RF (resume) used with debugging to control resumption of execution after the next
instruction.
• VM (virtual mode) flag bit selects virtual mode operation in a protected mode system.
• AC, (alignment check) flag bit activates if a word or doubleword is addressed on a non-word or
non-doubleword boundary.
• VIF is a copy of the interrupt flag bit available to the Pentium 4 – (virtual interrupt)
• VIP (virtual) provides information about a virtual mode interrupt for (interrupt pending)
Pentium.
• used in multitasking environments to provide virtual interrupt flags
• ID (identification) flag indicates that the Pentium microprocessors support the CPUID
instruction.
• CPUID instruction provides the system with information about the Pentium microprocessor
Segment Registers• Generate memory addresses when combined with other registers in the microprocessor.
• Four or six segment registers in various versions of the microprocessor.
• A segment register functions differently in real mode than in protected mode.
• Following is a list of each segment register, along with its function in the system.
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• CS (code) segment holds code (programs and procedures) used by the microprocessor.
• DS (data) contains most data used by a program.
• Data are accessed by an offset address or contents of other registers that hold the offset address
• ES (extra) an additional data segment used by some instructions to hold destination data.
• SS (stack) defines the area of memory used for the stack.
• stack entry point is determined by the stack segment and stack pointer registers
• the BP register also addresses data within
the stack segment
• FS and GS segments are supplemental segment registers available in 80386 – Core2
microprocessors.
• allow two additional memory segments for
access by programs
• Windows uses these segments for internal operations, but no definition of their usage
is available.
1.4 REAL MODE MEMORY ADDRESSING
Two Real modes of addressing on 80x86
Pentium 4 comes up in the real-mode after it is reset. It will remain in this mode
unless it is switched to protected-mode by software.
• In real mode, the Pentium 4 operates as a very high performance 8086.
• Pentium 4 can be used to execute the base instruction set of the 8086 MPU
(backward compatibility).
In addition, a number of new instructions (called extended instruction set) have been
added to enhance its performance and functionality (such new instructions can be run in the
real-mode as well as the protected-mode). In real-mode, only the first 1 M bytes of memory
can be addressed with the typical segment:offset logical address. Each segment is 64K bytes
long.
• Notice that the Pentium 4 microprocessor has 36 bit address bus, which means it can
support up to 236 = 64G bytes of total memory (which cannot be addressed in real-mode but
can be addressed in protected mode).
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Real mode flat model means
o Strictly converting one address value into a physically meaningful location in the RAM.
Real mode segmented model means
o strictly converting two address values into a physically meaningful memory location.
o gives access to one megabyte (1,048,576 bytes) of directly addressable memory, known as real
mode memory.
a. Segment Registers
Segment registers are basically memory pointers located inside the CPU.
Segment registers point to a place in memory where one of the following things begin:
1. Data storage
2. Code execution.
Example: code segment register CS points to a 64K region of memory:
b. Real Mode Segmented Model
Segmented organization
o 16-bit wide segments
Two componentso Base (16 bits)
o Offset (16 bits)
Two-component specification is called logical address, also called effective address.
Logical address translates to a 20-bit physical address.
c. Real Mode Segmented Model, Cont.
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Addresses are limited to 20 bits:
220
=1,048,576 bytes.
Physical address is generated by adding a16-bit segment register, shifted left four bits
plus a 16 bit-offset.
Generating 20-bit physical address in Real Mode:
d. Problems Related to Segmentation
Segmentation often caused grief for programmers who tried to access large data structures:
o Since an offset cannot exceed 16 bits, you cannot increment beyond 64k.o Instead, program must watch out for a 64k boundary and then play games with the segment
register.
This nightmare was originally created to support CP/M-80 programs ported from 8080 chip to
8086.o Successful short-term thinking;
o Catastrophically bad long-term thinking that resulted in never-ending Windows 9x problems!
e. Address Space in Real Mode
Address space in real mode segmented model runs from
o 00000h to 0FFFFFh, within one megabyte of memory.
For compatibility reasons, Pentium CPU is capable of switching itself into real mode
segmented model, is effectively becoming a good old 8086 chip!
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UNIT-2
2.1 PROTECTED-MODE
• In the protected-mode, memory larger than 1 MB can be accessed.Windows XP operates in
the protected mode.
• In addition, segments can be of variable size (below or above 64 KB).
• Some system control instructions are only valid in the protected mode.
• In protected mode, the base:offset logical memory addressing scheme (which is used in real
mode) is changed.
• The offset part of the logical memory address is still used. However, when in the protected
mode, the processor can work either with 16-bit offsets (the 16-bit instruction mode) or with 32-
bit offsets (the 32-bit instructionmode). A 32-bit offset allows segments of up to 4G bytes inlength. Notice that in real-mode the only available instruction mode is the 16-bit mode (during
which accessing 32-bit registers requires the prefix 66h).
• However, the segment base address calculation is different in protected mode. Instead of
appending a 0 at the end of the segment register contents to create a segment base address (which
gives a 20-bit physical address), the segment register contains a selector that selects a descriptor
from a descriptor table. The descriptor describes the memory segment's location,length, and
access rights. This is similar to selecting one card from a deck of cards in one's pocket.
• Because the segment register and offset address still create a logical memory address, protected
mode instructions are the same as real mode instructions. In fact, most programs written to
function in the real mode will function without change in the protected mode .
DESCRIPTORS:
• The selector, located in the segment register, selects one of 8192 descriptors from one of two
tables of descriptors (stored in memory): the global and local descriptor tables. The descriptor
describes the location, length and access rights of the memory segment.
• Each descriptor is 8 bytes long and its format is shown below:
The 8192 descriptor table requires 8 * 8192 = 64K bytes of memory. The
main parts of a descriptor are:
Base (B31 – B0): indicates the starting location (base address) of the memory segment. This
allows segments to begin at any location in the processor's 4G bytes of memory .
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Limit (L19 – L0): contains the last offset address found in a segment. Since this field is 20 bits,
the segment size could be anywhere between 1 and 1M bytes. However, if the G bit
(granularity bit) is set, the value of the limit is multiplied by 4K bytes (i.e., appended with
FFFH). In this case, the segment size could be anywhere between 4K and 4G bytes in steps of
4K bytes.
Example,
Base = Start = 10000000h
Limit = 001FFh and G = 0
So, End = Base + Limit = 10000000h + 001FFh = 100001FFh
Segment Size = 512 bytes
Base = Start = 10000000h
Limit = 001FFh and G = 1
So, End = Base + Limit * 4K = 10000000h + 001FFFFFh = 101FFFFFh
Segment Size = 2M bytes
AV bit: is used by some operating systems to indicate that the segment is available (AV = 1) or
not available (AV = 0).
D bit: If D = 0, the instructions are 16-bit instructions, compatible with the 8086-80286
microprocessors. This means that the instructions use 16-bit offset addresses and 16-bit registers
by default. This mode is the 16-bit instruction mode or DOS mode. If D = 1, the instructions are
32-bits by default (Windows XP works in this mode). By default, the 32-bit instruction mode
assumes that all offset addresses and all registers are 32 bits. Note that the default for register
size and offset address can be overridden in both the 16- and 32-bit instruction modes using the
66h and 67h prefixes. In 16-bit protected-mode, descriptors are still used but segments are
supposed to be a maximum of 64K bytes.
Access rights byte: allows complete control over the segment. If the segment is a data segment,
the direction of growth is specified. If the segment grows beyond its limit, the microprocessor's
operating system program is interrupted, indicating a general protection fault. You can specify
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whether a data segment can be written or is write-protected. The code segment can have reading
inhibited to protect software. This is why It is called protected mode. This kind of protection is
unavailable in realmode.
.
SELECTORS:
Descriptors are chosen from the descriptor table by the segment register .
There are two descriptor tables:
Global descriptors table: contains segment definitions that apply to all programs (also called
system descriptors).
Local descriptors table: usually unique to an application (also called application descriptors).
Each descriptor table contains 8192 descriptors, so a total of 16,384 descriptors are available to
an application at any time. This allows up to 16,384 memory segments to be described for each
application. The Figure below shows the segment register in the protected mode. It contains:
13-bit selector field: chooses one of the 8192 descriptors from the descriptor table (213 = 8192).
Table indicator (TI) bit: selects either the global descriptor table (TI = 0) or the local descriptor
table (TI = 1).
Requested privilege level (RPL) field: requests the access privilege level of a memory segment.
The highest privilege level is 00 and the lowest is 11.If the requested privilege level matches oris higher in priority than the privilege level set by the access rights byte, access is granted.
Windows uses privilege level 00 (ring 0) for the kernel and driver programs and level 11 (ring 3)
for applications. Windows does not use levels 01 or 10. If privilege levels are violated, the
system normally indicates a privilege level violation.
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Example:
Real Mode: DS = 0008h, then the data segment begins at location 00080h and its length is 64K
bytes.
Protected Mode: DS = 0008h = 0000 0000 0000 1000, then the selector selects Descriptor 1 in
the global descriptor table using a requested privilege level of 00. The global descriptor table is
stored in memory as shown below.
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Descriptor number 1 contains a descriptor that defines the base address as 00100000h with a
segment limit of 000FFh. This refers to memory locations 00100000h – 001000FFh for the data
segment.
2.2 PROGRAM-INVISIBLE REGISTERS:
The global and local descriptor tables are found in the memory system . In order to specify the
address of these tables, Pentium 4 contains program invisible registers LDTR and GDTR (these
registers are not directly addressed by software).
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The GDTR (global descriptor table register), LDTR (local descriptor table register) and IDTR
(interrupt descriptor table register) contain the base address of the descriptor table and its limit.
The limit of these descriptor tables is 16 bits because the maximum table length is 64K bytes
(but of course, the table could be smaller than 64K byte, hence the need for the limit) .
Before using the protected mode, the interrupt descriptor table, global descriptor table along with
the corresponding registers IDTR and GDTR must be initialized. This is why the Pentium 4
boots in the real mode not protected mode, and why the maximum descriptor table size is 64K
bytes.
Each of the segment registers also contains a program-invisible portion used as a cache to store
the corresponding 8 byte descriptor to avoid repeatedly accessing memory every time the
segment register is referenced (hence the term cache).
These program-invisible registers are loaded with the base address, limit, and access rights each
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time the number in the segment register is changed.
The TR (task register) holds a selector, which accesses a descriptor that defines a task . A task is
most often a procedure or application program. The descriptor for the procedure or application
program is stored in the global descriptor table, so access can be controlled through the privilege
levels. The task register allows a context or task switch in multitasking systems in about 17s.
Notice: The memory system for the Pentium 4 is 4G bytes in size, but access to the area
between 4G and 64G is enabled with bit position 4 of the control register CR4 and is accessible
only when 4M paging is enabled. When in this paging mode, address lines A35 – A32 are
enabled with a special new addressing mode, controlled by other bits in CR4 .
2.3 Memory Paging
Paging is enabled when the PG bit in control register CR0 is set. The paging mechanism can
function in both the real and protected modes.
��When paging is enabled, physical memory is divided into small blocks (typically 4K bytes or
4M bytes) in size, and each block is assigned a page number . The operating system keeps a list
of free pages in its memory. When a program makes a request for memory, the OS allocates a
number of pages to the program.
A key advantage to memory paging is that memory allocated to a program does not have to be
contiguous, and because of that, there is very little internal fragmentation - thus little memory is
wasted.
THE PAGE DIRECTORY AND PAGE TABLE
��To convert a 32-bit linear address into a 32-bit physical address, we need to understand that
the most significant 20 bits of the linear address indicate the linear page number, while the
least significant 12 bits of the linear address indicate the offset within this page. The offset
should remain the same but the linear page number has to be converted into a physical page
number .
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Each page directory entry is a physical address pointing to a page table, which contains page
table entries. Each page table contains 1024 page table entries, each of which is 4 bytes (32
bits). This means that each page table is 4 K bytes long.
Each page table entry points to the starting physical address of a page in memory (i.e., the
physical page number).
This means that if we have one page directory and 1024 page tables, then we have a total of 1M
table entries or 1 M pages. Since each page is 4K bytes long, this will cover a total of 4G bytes
of maximum physical memory.
The figure below Part (a) shows the linear address (generated by the software) and how it selects
one of the 1024 page directory entries from the page directory (using the left most 10 bits) and
then selects one of the 1024 page table entries (using the next 10 bits). Part (b) of the figureshows the page table entry, which contains the physical number that must be associated with the
offset.
For example, the linear addresses 00000000h-00000FFFh access the first page directory entry,
and the first page table entry. Notice that one page is a 4K-byte address range. So, if that page
table entry contains 00100000h, then the physical address of this page is 00100000h-00100FFFh
for linear address 00000000h-00000FFFh. This means that when the program accesses a location
between 00100000h and 00100FFFh, the microprocessor physically addresses location
00100000h-00100FFFh.
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For example, the linear addresses 00000000h-00000FFFh access the first page directory entry,
and the first page table entry. Notice that one page is a 4K-byte address range. So, if that page
table entry contains 00100000h, then the physical address of this page is 00100000h-00100FFFh
for linear address 00000000h-00000FFFh. This means that when the program accesses a location
between 00100000h and 00100FFFh, the microprocessor physically addresses location
00100000h-00100FFFh.
The procedure for converting linear addresses into physical addresses:
2.4 8086 Addressing Modes for accessing data
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Addressing modes provide convenience in accessing data needed in an instruction.
8086 Addressing Modes for accessing data
Immediate Register addressing Memory addressing I/O port addressing
Addressing mode
(for source
operand only)
2.4.1 Immediate Addressing
Before After
Ex1: MOV DX, 1234H DX ABCDH 1234H
Before After
Ex2: MOV CH, 23H CH 4DH 23H
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2.4.2 Register Addressing
Before After
Ex1: MOV CX, SI CX 1234H 5678H
SI 5678H 5678H
Before After
Ex2: MOV DL, AH Dl 89H BCH
AH BCH BCH
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Memory Addressing
Direct Addressing Indirect Addressing
Memory Indirect Addressing
Register Based Addressing Indexed Based Based Indexed
Indirect with Addressing with Indexed addressing with
displacement displacement addressing displacement
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2.4.3 Memory Direct Addressing
Before After
Ex1: MOV BX, DS:5634H BX ABCDH 8645H
DS:5634H 45H LS byte
DS:5635H 86H MS byte
Before After
Ex2: MOV CL, DS:5634H CL F2H 45H
DS:5634H 45H
DS:5635H 86H
Ex3: MOV BH, LOC Before After
Program BH C5H 78H
.DATA
LOC DB 78H
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2.4.4.Register Indirect Addressing
Before After
Ex1: MOV CL, [SI] CL 20H 78H
SI 3456H
DS:3456H 78H
Before After
Ex2: MOV DX, [BX] DX F232H 3567H
BX A2B2H
DS:A2B2H 67H LS byte
DS:A2B3H 35H MS byte
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Before After
Ex3: MOV AH, [DI] AH 30H 86H
DI 3400H
DS:3400H 86H
Only SI, DI and BX can be used inside [ ] from memory addressing point of view. From user
point of view [BP] is also possible. This scheme provides 3 ways of addressing an operand in
memory.
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2.4.5 Based Addressing with displacement
Before After
Ex1: MOV DH, 2345H[BX] DH 45H 67H
2345H is 16-bit displacement BX 4000H
4000 + 2345 = 6345H DS:6345H 67H
Before After
Ex2: MOV AX, 45H[BP] AX 1000H CDABH
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45H is 8-bit displacement BP 3000H
3000 + 45 = 3045H SS:3045H ABH LS byte
It is SS when BP is used SS:3346H CDH MS byte
Base register can only be BX or BP. This scheme provides 4 ways of addressing an operand in
memory.
2.4.6 Indexed Addressing with displacement
Before After
Ex1: MOV CL, 2345H[SI] CL 60H 85H
2345H is 16-bit displacement SI 6000H
6000 + 2345 = 8345H DS:8345H 85H
Before After
Ex2: MOV DX, 37H[DI] DX 7000H B2A2H
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37H is 8-bit displacement DI 5000H
5000H+ 37H = 5037H DS:5037H A2H LS byte
DS:5038H B2H MS byte
Index register can only be SI or DI. This scheme provides 4 ways of addressing an operand in
memory.
2.4.7Based Indexed Addressing
Before After
Ex1: MOV CL, [SI][BX] CL 40H 67H
SI 2000H
BX 0300H
2000H + 0300H = 2300H DS:2300H 67H
Before After
Ex2: MOV CX, [BP][DI] CX 6000H 6385H
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BP 3000H
DI 0020H
2000H + 0300H = 2300H SS:3020H 85H LS byte
It is SS when BP is used SS:3021H 63H MS byte
This scheme provides 4 ways of addressing an operand in memory. One register must be a Base
register and the other must be an Index register .
For ex. MOV CX, [BX][BP] is an invalid instruction.
2.4.6 Based Indexed Addressing with Displacement
Before After
Ex1: MOV DL, 37H[BX+DI] DL 40H 12H
37H is 8-bit displacement BX 2000H
DI 0050H
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2000H + 0050H + 37H = 2300H DS:2087H 12H
Before After
Ex2: MOV BX, 1234H[SI+BP] BX 3000H 3665H
SI 4000H
BP 0020H
4000H + 0020H +1234 = 5254H SS:5254H 65H LS byte
It is SS when BP is used SS:5255H 36H MS byte
This scheme provides 8 ways of addressing an operand in memory.
2.4.7 Memory modes as derivatives of Based Indexed Addressing with Displacement
Addressing mode
Direct Addressing
Register Indirect
MOV DH, 2345H[BX} Yes No Yes Based Addressing with
Instruction Base
Register
MOV BX, DS:5634H No
Index Displace
Register ment
No Yes
MOV CL, [SI] No Yes No
MOV DX, [BX] Yes No No
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Displacement
MOV DX, 35H[DI] No Yes Yes Indexed Addressing with
displacement
MOV CL, 37H[SI+BX] Yes Yes No Based Indexed Addressing
MOV DL, 37H[BX+DI] Yes Yes Yes Based Indexed Addressing
with displacement
2.4.8 I/O port Addressing
I/O port Addressing
Fixed port addressing Variable port addressing
Or Direct Port addressing Or Indirect port addressing
Fixed Port Addressing
Before After
Ex. 1: IN AL, 83H AL 34H 78H
Input port no. 83H 78H
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Before After
Ex. 2: IN AX, 83H AX 5634H F278H
Input port no. 83H 78H
Input port no. 84H F2H
Before After
Ex. 3: OUT 83H, AL AL 50H
Output port no. 83H 65H 50H
Before After
Ex. 4: OUT 83H, AX AX 6050H
Output port no. 83H 65H 50H
Output port no. 84H 40H 60H
IN and OUT instructions are allowed to use only AL or AX registers . Port address in the range
00 to FFH is provided in the instruction directly.
2.4.9.Variable Port Addressing
I/O port address is provided in DX register . Port address ranges from 0000 to FFFFH. Data
transfer with AL or AX only.
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Before After
Ex. 1: IN AL, DX AL 30H 60H
DX 1234H
Input port no. 1234H 60H
Before After
Ex. 2: IN AX, DX AX 3040H 7060H
DX 4000H
Input port no. 4000H 60H
Input port no. 4001H 70H
Before After
Ex. 3: OUT DX, AL AL 65H
DX 5000H
Output port no. 5000H 80H 65H
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Before After
Ex. 4: OUT DX, AX AX 4567H
DX 5000H
Output port no. 5000H 25H 67H
Output port no. 5001H 36H 45H
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Unit - 3
3.1 8086 Instruction set
Abbreviations used
R8= AL/BL/CL/DL/ AH/BH/CH/DH
R16=AX/BX/CX/DX/ SI/DI/BP/SP R=R8/R16
SR=CS/DS/ES/SS AR=SI/DI/BX/BP
d16=16-bit data d8=8-bit data
a8=8-bit I/O port address
M8=contents of byte memory
M16=contents of word memory M=M8/M16
Conventions used:
R
MOV for MOV R, M andMOV M, R
M
PUSH/POP R16 for PUSH R16 and POP R16
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ROR R/M, 1/CL for ROR R,1 ROR M,1 ROR R,CL ROR M, CL
3.1.1 8086 Instruction set types
Instructions are normally discussed under:
Data Transfer instructions Ex. MOV BX, CX
Arithmetic instructions Ex. ADD BX, CX
Logical group of instructions Ex. AND BX, CX
Stack group Ex. PUSH DX I/O group Ex. IN AL, 30H
Branch group Ex. JNC LOCN
String instructions Ex. MOVS
Interrupt instructions Ex. INT 21H
Data Transfer group, Arithmetic group, Logical group, Stack group, and I/O group ofinstructions explained first. They occupy several chapters in books.
Here, I explain them under:
2-operand instructions Ex. ADD BX, CX
1-operand instructions Ex. PUSH SI
0-operand instructions: Ex. DAA
Branch group, String instructions, and Interrupt instructions are explained later .
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3.2Operand instructions
3.2.1Operand instructions involving R and R/M
MOV/XCHG Data transfer
ADD/ADC/SUB/SBB R Arithmetic
AND/OR/XOR/TEST/CMP R/M Logical
11 instructions x 210= 11264 opcodes
MOV instruction already discussed- see Instruction template
In data transfer instructions flags are not affected.
3.2.2 Exchange Instruction
Before After
XCHG DX, [BX] DX 1234H ABCDH
BX 1000H
DS:1000H ABCDH 1234H
DS:1002H
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3.2.3 Add instruction
Unlike in 8085, result of add/subtract can be in any register or memory location
Before After
ADD [BX], DX DX 1234H
BX 1000H
In 3234H, 34H has DS:1000H 2000H 3234H
three 1’s. So P flag =0 DS:1002H
Before After
ADC DH ,[SI] DH 30H 81H
Add with Carry Carry flag 1 0
SI 2000H
81H DS:2000H 50H
1000 0001B(Two 1’s) DS:2001H 60H
New flag values: Ac=0, S=1, Z=0, V=1, P=1
Before After
SUB DH, CL DH 30H 0BH
Subtract (without borrow)
CL 25H
0BH =
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0000 1011B(Three 1’s)
New flag values: Ac=1, S=0, Z=0, V=0, P=0, Cy=0
Before After
SBB DH, CL DH 20H FAH
Subtract (with borrow) Cy flag 1 1
CL 25H
FAH =1111 1010(Six 1’s)
2’s complement of FAH=0000 0110 = +06 So, FAH = -06
New flag values: Ac=1, S=1, Z=0, V=0, P=1, Cy=1
Discussion about Overflow (V) flag V
23H (+ve) 43H (+ve)
+ 46H (+ve) + 54H (+ve)
= 69H (+ve) = 97H (-ve)
V= 0, Cy = 0 V = 1, Cy = 0
Correct answer Wrong answer
Overflow used with signed numbers only
Carry flag used with unsigned numbers only
83H (-ve) F2H (-ve)
+ 94H (-ve) + F3H (-ve)
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= 17H (+ve) = E5H (-ve)
V= 1, Cy = 1 V = 0, Cy = 1
Wrong answer Correct answer
94H (-ve) F6H (-ve)
- 83H (-ve) - 43H (+ve)
= 11H (+ve) = B3H (-ve)
V= 0, Cy = 0 V = 0, Cy = 0
Correct answer Correct answer
94H (-ve) 66H (+ve)
- 23H (+ve) - 83H (-ve)
= 71H (+ve) = E3H (-ve)
V= 1, Cy = 0 V = 1, Cy = 1
Wrong answer Wrong answer
3.2.4 AND instruction
Before After
AND BH, CL BH 56H 06H
Subtract (with borrow) AND 1 1
0FH=0000 1111B CL 0FH
06H=0000 0110B
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Use: Selectively reset to 0 some bits of the destination
Bits that are ANDed with 0’s are reset to 0
Bits that are ANDed with 1’s are not changed
3.2.5 OR instruction
Before After
OR BH, CL BH 56H 5FH
56H=0101 0110B OR
0FH=0000 1111B CL 0FH
5FH=0101 1111B
Use: Selectively set to 1 some bits of the destination
Bits that are ORed with 1’s are set to 1
Bits that are ORed with 0’s are not changed
3.2.6 Ex-OR instruction
Before After
XOR BH, CL BH 56H 59H
56H=0101 0110B XOR
0FH=0000 1111B CL0FH
59H=0101 1001B
Use: Selectively complement some bits of the destination.
Bits that are XORed with 1’s are complemented
Bits that are XORed with 0’s are not changed
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3.2.7 TEST instruction
Before After
TEST BH, CL BH 56H 56H
56H=0101 0110B AND
0FH=0000 1111B CL 0FH 0FH
06H=0000 0110B
Only flages are affected Temp 45H 06H
TEST basically performs AND operation. Result of AND is not stored
in destination. It is stored in Temp register. Temp is not accessible to
programmer . There is no instruction like MOV Temp, 67H
3.2.8 Compare Instruction
Before After
CMP BH, CL BH 56H 56H
56H=0101 0110B
0FH=0000 1111B CL 0FH
Only flags are affected
Temp 45H 47H
CMP basically performs Subtract operation. Result of CMP is not
stored in destination. It is stored in Temp register. Temp is not
accessible to programmer .
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3.3 Operand Instructions involving immediate data
MOV
ADD/ADC/SUB/SBB R/M, d8/d16
AND/OR/XOR/TEST/CMP
8 byte registers + 8 word registers+ 24 byte
memory + 24 word memory = 64 opcodes
10 instructions x 64 = 640 opcodes
3.3.1 Move Immediate data to a Register/ Memory location
Before After
MOV DX, ABCDH DX 1234H ABCDH
Before After
MOV BH, 12H BH 56H 12H
3.3.2 Add Immediate data to a Register/ Memory location
Before After
ADD [BX], 12H BX 1000H
DS:1000H 20H 32H
DS:1001H
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Before After
ADD [BX], 1234H BX 1000H
DS:1000H 2000H 3234H
DS:1002H
3.3.3 Add with Carry Immediate data to a Register/ Memory location
Before After
ADC DH, 32H DH 30H 63H
Add with Carry Carry flag 1 0
63H= 0110 0011 It has f our 1’s
New flag values: Ac=0, S=0, Z=0, V=0, P=1
3.3.4 Subtract Immediate data from a Register/ Memory location
Before After
SUB DH, 40H DH 30H F0H
Subtract (without borrow)
F0H=1111 0000 B(Four 1’s)
New flag values: Ac=0, S=1, Z=0, V=0, P=1, Cy=1
3.3.5 Subtract with borrow Immediate data from a Register/ Memory location
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Before After
SBB DH, 25H DH 20H 06H
Subtract (with borrow) Cy flag 1 1
06H= 0000 0110B(Two 1’s)
New flag values: Ac=1, S=0, Z=0, V=0, P=1, Cy=1
3.3.6 AND Immediate data with a Register/ Memory location
Before After
AND BH, 0FH BH 56H 06H
56H = 0101 0110B AND
0FH = 0000 1111B Cy flag 1 1
06H = 0000 0110B(Two 1’s)
Use: Selectively reset to 0 some bits of the destination
Bits that are ANDed with 0’s are reset to 0
Bits that are ANDed with 1’s are not changed
3.3.7 OR Immediate data with a Register/ Memory location
Before After
OR BH, 0FH BH 56H 5FH
56H = 0101 0110B OR
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0FH = 0000 1111B CL 0FH
5FH = 0101 1111B
Use: Selectively set to 1 some bits of the destination
Bits that are ORed with 1’s are set to 1
Bits that are ORed with 0’s are not changed
3.3.8 Ex-OR Immediate data with a Register/ Memory location
Before After
XOR BH, 0FH BH 56H 59H
56H = 0101 0110B XOR
0FH = 0000 1111B CL 0FH
59H = 0101 1001B
Use: Selectively complement some bits of the destn.
Bits that are XORed with 1’s are complemented
Bits that are XORed with 0’s are not changed
3.3.9 Test immediate data with a Register/ Memory location
Before After
TEST BH, 0FH BH 56H 56H
56H=0101 0110B AND
0FH=0000 1111B Temp 45H 06H
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Note that there is no instruction to load an immediate data to a Segment
register .
No. of opcodes = 2 x 4 x (8+24) = 256
Before After
MOV DS, [BX] DS 1122H 2233H
BX 2000H
DS:2000H 2233H
3.4.2 Operand Instructions to perform Input operation
IN AL/AX, a8/DX 4 opcodes
Before After
IN AL, DX AL 50H 45H
DX 2111H
Input port no. 2111H 45H
Before After
IN AL, 30H AL 45H50H
Input port no. 30H 45H
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Out port no. 60H 45H 50H
Out port no. 61H 40H 30H
3.4.4 Operand Instructions to perform Shift/Rotate operation
ROR /ROL /RCR /RCL /SHR /SHL /SAR R/M, 1/CL
7 instructions x (16+48) x 2 = 896 opcodes
SHR and SHL: for shifting left / right unsigned numbers
SAR used Shifting right a signed number
SHL is also called as SAL, as method for shift left of signed or unsigned number is the same
ROR R/M, 1/CL�