BSDカーネルの設計と実装 読書会(7)5.11.1章 224〜226p ハードウェアキャッシュの設計

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BSDカーネルの設計と実装 読書会 (7) のときに僕が担当した部分の資料です.

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  • 1. BSD (7)5.11.1 224226p @miettal

2. 5.11.1 3. 0x21f0f0CACHELINES=4ab 012 3address a3f0 aaf7 ab07 ab17 10 21f0ec 435d 63ff78f6 d1 ba34cd 0d3d 65a0LINESIZE=8a0 7397 24ea datab0 3108 b5ff81 5e8a e4ff6d 5bc2 efffee 55d7 10f0 21f74a4ab0 4. 0x21f0 f0 CACHELINES=4ab012 3 (21f0 / 8) % 4 = 2 address a3f0 aaf7 ab07 ab17 1021f0 ec 435d 63ff 78f6 d1 ba34 cd 0d3d 65a0 LINESIZE=8 a0 7397 24eadata b0 3108 b5ff 81 5e8a e4ff 6d 5bc2 efff ee 55d7 10f021f7 4a 4a b0 5. 0x21f0 f0 CACHELINES=4ab012 3 (21f0 / 8) % 4 = 2 address a3f0 aaf7 ab07 ab17 1021f0 ec 435d 63ff 21f0 != 0b0778f6 d1 ba34 cd 0d3d 65a0 LINESIZE=8 a0 7397 24eadata b0 3108 b5ff 81 5e8a e4ff 6d 5bc2 efff ee 55d7 10f021f7 4a 4a b0 6. 0x21f0 f0 CACHELINES=4ab012 3 (21f0 / 8) % 4 = 2 address a3f0 aaf7 21f0 ab17 1021f0 ec 43ff 63ff 21f0 != 0b0778f6 34 ba34 cd 0da0 65a0 LINESIZE=8 a0 73ea 24eadata b0 31ff b5ff 81 5eff e4ff 6d 5bff efff ee 55f0 10f021f7 4a 4a b0 7. 0x21f0 f0 CACHELINES=4ab012 3 (21f0 / 8) % 4 = 2 address a3f0 aaf7 21f0 ab17 1021f0 ec 43ff 63ff 21f0 != 0b0778f6 34 ba34 cd 0da0 65a0 LINESIZE=8 a0 73ea 24ea 0xffdata b0 31ff b5ff 81 5eff e4ff 6d 5bff efff ee 55f0 10f021f7 4a 4a b0 8. 0x21f0 f0 CACHELINES=4ab012 3 (21f0 / 8) % 4 = 2 address a3f0 aaf7 21f0 ab17 1021f0 ec 43ff 63ff 21f0 == 21f078f6 34 ba34 cd 0da0 65a0 LINESIZE=8 a0 73ea 24eadata b0 31ff b5ff 81 5eff e4ff 6d 5bff efff ee 55f0 10f021f7 4a 4a b0 9. 0x21f0 f0 CACHELINES=4ab012 3 (21f0 / 8) % 4 = 2 address a3f0 aaf7 21f0 ab17 1021f0 ec 43ff 63ff 21f0 == 21f078f6 34 ba34 0xff cd 0da0 65a0 LINESIZE=8 a0 73ea 24eadata b0 31ff b5ff 81 5eff e4ff 6d 5bff efff ee 55f0 10f021f7 4a 4a b0 10. CACHELINESLINESIZE2^n CACHELINES*LINESIZE 0x21f0(21f0 / 8)%4 = 2 0x2210(2210 / 8)%4 = 2 11. 2 f0CACHELINES=4CACHELINES=4 013ab 2 012 3address a3f0 aaf7 21f0 ab17addressa3f0 aaf7 2210 ab17 10 21f0ec 43ff 63ec 43ab 63ff78f6 34 ba78f6 31 ba34cd 0da0 65cd 0ded 65a0LINESIZE=8LINESIZE=8a0 73ea 24a0 73ed 24ea datadatab0 31ff b5b0 31ed b5ff81 5eff e481 5eed e4ff6d 5bff ef6d 5bed efffee 55f0 10ee 55ed 10f0 21f74a24a3 b0 12. 4 address03CACHELINES=412 03CACHELINES=412f0a3f0 aaf7 21f0 ab17 addressLINESIZE=8a3f0 aaf7 2210 ab17LINESIZE=8 ec 43 ff63ec 43 ab 63ab data78 f634 badata78 f6 31 ba10 21f0 cd 0da0 65cd 0d ed 65ffaddress3 a0CACHELINES=473ea 240 aaf7 21f0 ab171 2 3 a00 CACHELINES=4731 ed 22434a3f0 31 addressLINESIZE=8a3f0 aaf7 2210 ab17LINESIZE=8 b0ffb5b0 31 ed b5 ec 43ff 63ec 43 ab 63a0 81 5e ffe481 5e ed e4 data78 f634 badata78 5bf6 31 baea 6d 5b ffef6ded ef cd ee 0d55a0f0 65 10cd ee 0d55 ed ed 6510ff a0 73ea 24a0 73 ed 24ff b0 31ff b5b0 31 ed b5ff 81 5eff e481 5e ed e4 6d 5bff ef6d 5b ed eff0 21f7 ee 55 f010ee 55 ed 104a44a5 b0 13. TLB(Translation Lookaside Buffer) ? 4.13 MMU 14. MMU CPU TLB PT MMUCPU TLB PT MMU 15. CACHELINES=40 12 3process tag 32 52 34 24 addressa3f0 aaf7 21f0 ab17 ec 43 ff 6381678f6 34 ba11 cd 0da0 65LINESIZE=8 a0 73ea 24 datab0 31ff b581 5eff e46d 5bff ef 32 ee 55f0 10 16. CPU