22.05.04 הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת...

22.05.04

הטכניון - מכון טכנולוגי לישראל

המעבדה למערכות ספרתיות מהירותהפקולטה להנדסת חשמל

Characterization Characterization PresentationPresentation

  Enhanced Ethernet CardEnhanced Ethernet CardProject num. 1523Project num. 1523

Students:Students: Alex ShpinerAlex ShpinerEyal AzranEyal Azran

Supervisor:Supervisor: Boaz MizrahiBoaz Mizrahi

Present ArchitecturePresent Architecture

FPGAPLX

MAC

PHY

PCI

ETHERNET

Current Main Features:Current Main Features:Transmitting and Receiving Ethernet framesTransmitting and Receiving Ethernet framesMAC and PHY configuration controlMAC and PHY configuration control

PCI

BRIDGE

MAC

PHY

CIF

GNR

MCF

TRN

RCV

ARB

Present FPGA Block DiagramPresent FPGA Block Diagram

Shared bus

Project’s goals: Automatic ping reply

Project’s goals: Automatic ping reply

Real time Packet analyzer & data collector

Project’s goals: Automatic ping reply

Real time Packet analyzer & data collector

Real time Network Testing Unit:

Project’s goals: Automatic ping reply

Real time Packet analyzer & data collector

Real time Network Testing Unit:

Predefined transmit rate

Project’s goals: Automatic ping reply

Real time Packet analyzer & data collector

Real time Network Testing Unit:

Predefined transmit rate

Accurate measurement of response time

Project’s goals: Automatic ping reply

Real time Packet analyzer & data collector

Real time Network Testing Unit:

Predefined transmit rate

Accurate measurement of response time

Testing parameters are predefined by user

MAC

CIF

TRN

RCV

ARB

FPGA ArchitectureFPGA Architecture

Shared bus

TRP

RCP

* Configuration units (GNR, MCF) are not shown on this diagram

RCP – Receive RCP – Receive Processing UnitProcessing Unit

Regular Packets Received

Data Collector

PacketAnalyzer

CIF

RCV

TRP

RCP

TRP – Transmit TRP – Transmit Processing UnitProcessing Unit

Echo Request

Parameters

Regular Packets to be transmitted

Echo RequestGenerator

Echo ReplyCreator

TRN Arbiter

CIF

TRN

RCP

TRP

Project Achievements

• Learning network protocols (Ethernet, IP, Echo).

• Experience in advanced VHDL.

• Appropriate unit design and simulation.

• Organized work and documentation.

Approximated Time Table

Time line

Learning the Network ProtocolsArchitecture Design and Algorithms Development

Final Presentation and Project Book Submitting

Writing the code and simulationSynthesis & Debug

March 2004

April 2004May to June 2004Jule 2004

August 2004

ThanksThanks