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Journée Informatique Embarquée :du Matériel au Logiciel
CAIRO+
Circuits Analogiques IntégrésRéutilisables et Optimisés
Marie-Minerve Louërat
Journée Informatique Embarquée: du Matériel au Logiciel - 13 mai 20052
CAIRO+ Project TeamAlain Greiner Professor
Marie-Minerve Louërat CR CNRS
Hassan Aboushady Assistant Professor
Jacky Porte Associate Professor
Pierre Nguyen Tuong PHD
Vincent Bourguet PHD
Laurent de Lamarre PHD
Nicolas Beilleau PHD
Ramy Iskander PHD
in cooperation with :
Andreas Kaiser CNRS-IEMN/ISEN, Lille, France
Mohamed Dessouky ICLab, Ain Shams University, le Caire,EG
Assistant Pr., Invited Pr. UPMC
Journée Informatique Embarquée: du Matériel au Logiciel - 13 mai 20053
Overview
•Digital Integrated Circuit Design ==> System On Chip
•Analog and Mixed Signal SOC
•Analog Integrated Circuit Design
•CAIRO+ : Generator, Devices & Hierarchy
•Design Examples
•Conclusion and Future work
Journée Informatique Embarquée: du Matériel au Logiciel - 13 mai 20054
Digital Integrated Circuit DesignBEFORE 1987 VHDL
1987
AFTER 1987
P&R
E1
Out = 1
E2
Out = 0
E0
Out = 0
Finite State Machineck
Entity circuit isport (ck,i,reset,vdd,vss : in bit, Out : out bit)
architecture MOORE of circuit is :type ETAT_TYPE is (E0,E1,E2) ;
beginprocess (EP, i reset)….
Process (ck)begin
if(ck=‘ 1 ’ and ck ’stable) thenEP <= EF ; ……..
ck
LOGICAL
SYNTHESIS
Dramat
ical In
crea
se
of Des
ign E
fficie
ncy
Journée Informatique Embarquée: du Matériel au Logiciel - 13 mai 20055
SOC Design : the SOCLIB example• Build an open platform for modelling and simulation of multi-processors SOCs• The core of the platform is a library of simulation models forvirtual components (IP cores)• Create the largest possible cooperation project at Europeanlevel, in order to share the development costs.
The main concern is true interoperability between the SoCLib IP cores :
• All simulation models written in SystemC• Two well defined abstraction levels have been defined :
• CABA (Cycle Accurate / Bit Accurate)• TLM (Transaction Level Modelling)
• All SoCLib components respect the VCI communication protocol.
100 0
00 00
0 MOS tr
ansis
tors
Journée Informatique Embarquée: du Matériel au Logiciel - 13 mai 20056
RF receiveron chip
A/D - D/A
SRAM
ROM/FLASH
DSP
ASIC
µP
RF
LNAMixers
LOsA/D
SRAM
Analogical IP !! Netlist Topology & Sizing Electrical Trade-Offs ==>
n New application : new electrical & physical environment.
n New performance specifications : electrical resizing.
n Technological process evolution : physical reshaping.
:-) Core Reuse (IP)
SOC : Analog to Digital Interface
Journée Informatique Embarquée: du Matériel au Logiciel - 13 mai 20057
Analog Integrated Circuit Design
W = 76.8 µmL = 3.1 µm
Technologie 0.25 µ
Folded Cascode OTA
Specification
& Technology
Migration
W = 140 µmL = 3.95 µm
Technologie 0.6 µ
Journée Informatique Embarquée: du Matériel au Logiciel - 13 mai 20058
Analog Function GeneratorVoltage Transfer Characteristic
-0,5
0
0,5
1
1,5
2
2,5
3
0 0,5 1 1,5 2 2,5 3
Vin (V)
Vou
t (V
)CMOS Inverter
Vin
Vout
Voltage Gain
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
2
0 0,5 1 1,5 2 2,5 3
Vin (V)
Gai
n
Vout High
Vout Low
ANALOGICAL OPERATING POINT
Vin Vout
Wn/Ln
Wp/Lp
Journée Informatique Embarquée: du Matériel au Logiciel - 13 mai 20059
CAIRO+ Generator
CAIRO+
SIZING engine & LAYOUT engine Electrical
Parameters
CAIRO+
Devices
Design Rule
Manual
Sized
Netlist
Resulting
PerformancesLayout
Design Rule
Manual Electrical
Parameters
Performance
specifications
Performance
specifications
Netlist Template Layout Template
Functional Interface :
parameters procedures
CAIRO+ Functions
Journée Informatique Embarquée: du Matériel au Logiciel - 13 mai 200510
BSIM3v3
Netlist :• 1 basic component (MOS transistor,R,L,C)• Set of matched components
Electrical sizing procedure based onaccurate electrical modeling
Custom optimized layout
CAIRO+ : Library of Devices
Journée Informatique Embarquée: du Matériel au Logiciel - 13 mai 200511
Hierarchical CommunicationDEVICE
GENERATOR
UPPERLEVEL
CREATION
DSES
SHAPING
P&R
CREATION
DSES
Shaping Layout
Generation
Top-down creation
Parameters tradeoffs
Error occurance
Layout& Sized Device Netlist
W, LShape FunctionShape Selection
Journée Informatique Embarquée: du Matériel au Logiciel - 13 mai 200512
SNRTH BW OSR80 dB 100 kHz 128
Process 0.6µm 0.18µmVDD 3.3V 1.8VI0 70µA 150µA
0.18µm Process
0.6µm Process
2 Current-Mode Integrators:• same specifications• different CMOS processes
Relative Placement and Routing: Independent from Devices Dimensions Independent from Technology Process
H. Aboushady University of Paris VI
Design Example
with S
TMicroele
ctronics
Journée Informatique Embarquée: du Matériel au Logiciel - 13 mai 200513
Design Example
MATCHED CAPACITOR
With
STMicr
oelec
tronic
s
Classical capacitor array
Matched capacitor array
Journée Informatique Embarquée: du Matériel au Logiciel - 13 mai 200514
Chips were measured using automated setup in Ain Shams IC Laboratory
Measurement Result : Low-Pass Biquad
Frequency Response of all chips
Standard Deviation
ProposedArray
Conventional Array
Conventional Array
ProposedArrayLess variations in the frequency
response for the proposed capacitorarray.
Journée Informatique Embarquée: du Matériel au Logiciel - 13 mai 200515
Conclusion and Future Work– CAIRO+ : Analog IP design environment
– an Analog IP : a CAIRO+ generator
– CAIRO+ provides a language : not black box generators, butfunctional interfaces
– Enhance library of devices with new technology features
– Enhance language with sizing trade-off capture
– Enhance layout engine with automated analog router
– Enhance sizing engine with optimization facilities
– Enhance methodology with hierarchical circuit standards
– Demonstrate CAIRO+ efficiency on smart circuits
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