View
75
Download
10
Category
Preview:
Citation preview
저 시-비 리- 경 지 2.0 한민
는 아래 조건 르는 경 에 한하여 게
l 저 물 복제, 포, 전송, 전시, 공연 송할 수 습니다.
다 과 같 조건 라야 합니다:
l 하는, 저 물 나 포 경 , 저 물에 적 된 허락조건 명확하게 나타내어야 합니다.
l 저 터 허가를 면 러한 조건들 적 되지 않습니다.
저 에 른 리는 내 에 하여 향 지 않습니다.
것 허락규약(Legal Code) 해하 쉽게 약한 것 니다.
Disclaimer
저 시. 하는 원저 를 시하여야 합니다.
비 리. 하는 저 물 리 목적 할 수 없습니다.
경 지. 하는 저 물 개 , 형 또는 가공할 수 없습니다.
SW Design
VirtualPrototype
PhysicalPrototype
HW Design
System
Level
Design SoCin Silicon
System
Integration
Specification
System Design
HW/SWPartitioning
Sys
tem
-lev
elD
esig
n Co-Simulation
ArchitectureTemplates
Arch
itecture
Exp
loration
Block-levelDesign
Logic Simulation
Logic Synthesis
HW
Des
ign
Back-end /Fabrication
Co-Simulation
Co-Emulation
FPGAPrototyping
HW-SWCo-Verification Programming
Compilation
Debugging
SW
Design
RTOS
FPGA
Processor
Memory
I/O
SoC Platform
Methodology-SpecificLibraries
Master/Slave Library, etc.
Layered Libraries
Verification Library Static Dataflow, etc.
Primitive Channels
Signal, Mutex, Semaphore, FIFO, etc.
Core Language
ModulesPorts
ProcessesInterfacesChannelsEvents
Event-driven simulation
Data Types
4-valued Logic type 4-valued Logic Vectors
Bits and Bit VectorsArbitrary Precision Integers
Fixed-point typesC++ user-defined types
C++ Language Standard
Sy
stem
C
Elaborate
sc_start( )
Cleanup
Initialize Evaluate
Update
AdvanceTime
DeltaCycle
.notify( )immediate
whileprocesses
ready
.notify(t)timed
.notify(SC_ZERO_TIME) delayed
sc_main( ) SystemC Simulation Kernel
SystemCModel
Simulation
Refinement
Synthesis
Rest of Process
Un-timed
Approximate-timed
Cycle-timed
Un-timed
Approximate-timed
Cycle-timed
SAM TLM
TLM
TLM
TLM
RTL
System Architectural ModelTransaction Level ModelingRegister Transfer Level
Communication
Fu
ncti
ona
lity
MoreAccurate
MoreAccurate
System level model
Explore algorithmsVerify against specifications
Refine
Timed model
Explore architecturesDo performance analysis
Partition hardware / software
HardwareRefineSoftware
Behaviorallevel model
Refine
RTL model
To synthesis
RTOS
Target code
- Not synthesizable- Event driven- Abstract data types- Abstract communication- Untimed
- Event driven
- Synthesizable- Algorithmic description- I/O cycle accurate- Clocked
- Synthesizable- Clocked- FSM
Design Specification
Design Partition
HDL Design
Simulation
Synthesis
Place & Route
Verification
System Integration & Test
11 12 13 14 2416 17 18 19 20 21 22 2315
7
3
65 98 10
2 4
1
Gate
RTL
Behavieral
StructuralDescription
BehavioralDescription
PhysicalDescription
View
1
2
3
Algorithm
Dataflow/RTL
Boolean algebra
ProcessorMemoryPeripheral interface
Registers,ALUs, etc.
Logic netlist,schematic
HierarchicalModules and
Primitiveinstantiations Cell geometry
ProceduralAssignment
PhotomaskLayoutDatabase
Nonblockingassignment
Continuousassignment
C/C++ Source Codes
Compiler
Assembly Programs
Assembler
Object Files Static Library
Linker
Executable Program
Test vectorGenerator DUT
ReferenceModel
Post-processor
Testbench
test vector actual result
expectedresult
Test
Generator
Agent
Driver
Scoreboard Checker
MonitorAssertions
DUT
Environment
ISSBFMMEM
Hardware model
Processor modelin C
Simulator ISS program
Cross-compiler
Applicationprogram
Targetdependent
library
Executableimage
ProcessorRTL model
Reset ofSoC model..
. Perpheralmodels..
.
HDL simulator
(a) Core model co-simulation environment
Interface(BFM)
Reset ofSoC model...
Perpheralmodels...
HDL simulator
(b) Real-chip driven co-simulation environment
Network processor
Interface(BFM)
Reset ofSoC model..
. Perpheralmodels..
.
HDL simulator
(c) Native-code co-simulation environment
Native codeC program
Interface(BFM)
Reset ofSoC model...
Perpheralmodels...
HDL simulator
(d) Integrated-ISS co-simulation environment
ISS
Interface(BFM)
Reset ofSoC model...
Perpheralmodels...
HDL simulator
(e) Decoupled-ISS co-simulation environment
C program
ISS
Interface(BFM)
Reset ofSoC model..
. Perpheralmodels..
.
HDL simulator
(f) ICE-based co-simulation environment
uP
M
Development board
Real chip
Readtask
Writetask
PLI/VPIinterface
Soc
ket
lib
rary
ahb
_tas
ks
DesignedIP
AMBAAHB
ahb_bfm_socket
top
BFMAPI
Socket lib
rary
Testingroutine
C program domain HDL simulator domain
socket
Client
srv_open(...);
srv_accept(...);
socket_get(...);
socket_put(...);
cli_connet(...);
socket_put(...);
socket_get(...);
socket_close(...);
Server
Pre-definedmessage passingcommunication
ApplicationProgram
ahb_read ...
DUT
top
SystemVerilogSystemC
task
ahb_writeDPI
Interface
sc_channel fifo_if payload_if
print ( );FIFO_read ( );
FIFO_read_nb ( );// ...
sc_simcontext*sc_get_curr_simcontext ( );
sc_module(const char* nm);
// ...
FIFO
FIFO_read ( );FIFO_read_nb ( );
print ( );// ...
sc_channel semaphore_if payload_if
print ( );get ( );put ( );
// ...
sc_simcontext*sc_get_curr_simcontext ( );
sc_module(const char* nm);
// ...
Semaphore
get ( );put ( );
print ( );// ...
Test
Generator
Agent
Driver
Scoreboard Checker
MonitorAssertions
HWComponent
Environment
virtual interfacetask/function call SystemC FIFOchannel
Test
HW1 ...
Environment1
Environment2
HW2
Gen_base
rand_testvector( );send_testvector( );
// ...
Env_base
configure( );wait_setup( );
report( );// ...
Generator
rand_testvector( );send_testvector( );
configure( );wait_setup( );
// ...
sc_module
sc_simcontext*sc_get_curr_simcontext( );sc_module(const char* nm)
// ...
Test
Agent
Driver
Scoreboard Checker
MonitorAssertions
HWComponent
Environment
virtual interface
mailbox
task/function call
Generator
SystemC design unit
RegisterFile
ALU
AHBSlaveState
Machine
...
...
DUT
AMBASignals
SystemVerilog
ahb_decoder
ahb_default_slave
ahb_bfm
DUTahb_s2m
HADDR
HWDATA
HRDATA
interface
top
decoder
defaultslave
DUTs2m
arbiter
m2sMaster1
Master2
HW1
interface
HW2
Recommended