IspLEVER 6.1 (VHDL)

Table of Contents ispLEVER 6.1

1 Project

2 Device

3 Design Source 1) Schematic Design Example 2) Design 3) 4-bit counter 4) Compile 5) 5 1) Package View 5 2) Spreadsheet View 6) Simulation 6 1 Test Bench File 6 2 Simulation 6 3 ModelSim

Lattice Device Design (VHDL)1 Project File->New Project schematic .Project~.syn project name Design Entry TypeSynthesis Tools (N) ABEL/SchematicVHDL/SchematicVerilog/SchematicDesign

Lattice Device Design (VHDL)2 Device Device

Family -> Device ->Speed grade-> Package type ->Operating conditions

Device (N) Add Source

-> source

-> project (N)

Project Information

->

Lattice Device Design (VHDL) PATH . Source in ProjectUntitled .()LFEC1E-3T100C , Device Selector .Device Selector, .

Lattice Device Design (VHDL)3 Design Source 1) Schematic Design ExampleSource ->New 2) Design NEW-> source

Import-> source ABEL Test Vectors->ABEL Design Simulation Text Editor

Schematic->Schematic Design

VHDL Module->VHDL Editor

Waveform Stimulus->Simulation Waveform Editor

Lattice Device Design (VHDL)->VHDL Module TEXT File, Entity Architecture Name . .

-> File Name Entity name file name architecture name Behavioral .library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;

entity demo is

end;

architecture behavioral of demo isbegin

end behavioral;

Lattice Device Design (VHDL)3) 4-bit counter 4-bit up counter

Lattice Device Design (VHDL) , . VHDL syntax check Synthesis Compile EDIF File. .

(** VHDL . Compile EDIF File .**)4) Compile

Process stateIconInitialNo iconWarningscompletedErrors

Lattice Device Design (VHDL) *** *** CPLD device Constraint Editor

FPGA device Design Planner (post-Map) 5) -> Design Planner (post-Map) View view . Package View Spreadsheet View

View Package View .

Lattice Device Design (VHDL)5 1) Package ViewPackage View Package I/O . pin Top View pin Unlock click (*signal datasheet Pinout Information )

Lattice Device Design (VHDL)5 2) Spreadsheet View pin Attributes pin block Double click pin Bank . pin demo.lpf .

Lattice Device Design (VHDL)6) Simulation Mentor Model Sim Simulation Test Bench File .

Test Bench File VHDL Test Bench Template Test Bench Format . cnt.vht .

6 1 Test Bench File

Lattice Device Design-> Text Editor Window Text Editor Text Editor .Text Editor File -> New

Lattice Device Design (VHDL) cnt.vht Drag input wave stimulus . Clock , clear Clock Clear Test Bench .(**Test bench VHDL **)Test Bench File *.vhd File Name OK

Lattice Device Design (VHDL)Test Bench File File Import.Importing Associate VHDL Test Bench , Function Simulation , TimingFunction Simulation Device .

Lattice Device Design (VHDL)6 2 Simulation Sources in ProjectTest Bench File

VHDL Functional Simulation ( Function )VHDL Post-Route Functional SimulationVHDL Post-Route Timing Simulation( Delay )

Simulation Simulation

Simulation ModelSim .

Lattice Device Design (VHDL)6 3 ModelSimCommand Run Wave Clear