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93 uAR(uAR)1 uAR uAR CPU61 F13 3 2 2101 5 61 2 3 4 0uAR() 1IRREG981 * * (uOP) (uOP)IRuAR()uIR uOP REGuOPmAR()mIRmOP() uOPuOP7695 CM()000000000100010001 110 10 00000 000 01 10110 010 00 00 CM CM0 000010 000101 ***** 00110001110100001001010100 001110 010000 010010 010100 00000 LD(I=1) 001 110 10 00000 000 01 10110 110 10 00000 000 00 10110 011 00 110001100100001010 001000 001010 00000 LD(I=0) 010 110 10 00000 000 00 10110 011 00 110101101100011010 011000 011010 00000 ST100 110 11 00010 111 00 10000 000 00 111000110010100111010010101010 110 10 00000 000 00 10110 100 00 00100 101 00 01101 011 00 110 100100 100110 101000 101010 00000 ADD(I=1) 011100111110000010 100 00 00100 101 00 01101 011 00 110 111110 100000 00000 ADD(I=0) CM CM101101011111000001 100 00 00011 101 00 01101 001 00 110 101110 110000 00000 JNZ(ZF=0)(ZF=1)11001000 000 00 110 0000091695.4 * uOPuOP ROM(CM) () uOPCmdMEM 6763 uOPCmdST(0100)RDout,MARin,Write RSout,MDRin,WMFCEndRSout,MARin,Read WMFCMDRout,RDin,EndLD(000)I0PCout,MARin,ReadPC+1,WMFCMDRout,MARin,ReadWMFCMDRout,RDin,EndI1JNZ(1110)ZF0EndPCout,Yin SEout,ADD,ZinZout,PCin,EndZF1ADD(100)I0RSout,MARin,Read WMFCMDRout,YinRDout,ADD,ZinZout,RDin,EndRSout,Yin RDout,ADD,ZinZout,RDin,EndI16061PCout,MARin,ReadPC+1,WMFCMDRout,IRin OP I RD RS OP I RD ADDR OP DISP OP RD RS32 *6JMP AuOPs: t1t3uOPs() t4PCMAR 1Read (PC)MEMA t5(PC)+1PCM(MAR)MDR (PC)+1 t6MDRPC1End APC 3R1(R0)+[A][A]uOPs uOPs CPU2824 1 (PC)+1PCA210 REG()uOP7CPU *CPU () () *:():():()9 * () (PC) +1 (PC)+1 (PC) * (PC+1)110 *CPU84REG 8(28) REG REGREGREGREGREGREGREGREGREGREGREGREG() () (MOV): RDIMME RD(RS)(LD) : RD[(RS)](ST) : [(RD)](RS)(ADD): RD(RD)+(RS) RD(RD)+[(RS)]1(INC) : RD(RD)+11(DEC) : RD(RD)-1(JMP): PCADDR (JNZ): ZF=0PC(PC)+DISP ZF=1PC(PC)+14 2 2RD0 0 0IMMERS0RD0 0 01RD0 0 1 0RSRDRS0 0 1 1RD0 1 0RS0RD0 1 010 1 1 00 1 1 1RSADDRDISP1 0 0 01 0 0 1RDRD16 OP/OPDOPD(PC)+1()tPCMARMEMMDRIR +1PCID

(OPOPD)20(3) * *uOP 1Write MARABusWriteCBus MDRM(MAR) MDRDBusMEMWRRDMFC MEM(Cache)uOP uOP()ALU21(4) * (ALU) *uOP R1ALU RREGMDR R2ALU OPALU ALUOP ALUR RR * REGALU(2) ALUREG REGALU23 * CPU() CPU 2 * (uOPs)uOP (uOPs) * uOPuOPs TuOPs uOPsuOPs4272 *CPUCPU(/) * () CPU CPU CPUD3A3A1A2D1D2ALUIRMUXPCMUXMUXMUXRDRS1RS2IDIMARIMDRIMEMDMDRDMARDMEM33 CPU *CPU(5)CPUCPU(ALU)IRPCID CU CPU()uOPuOPCPUuOPs P220 457(2)(3)8 *()/MEMuOP/MEMuOPsuOP3338(1)(CPU) *CPU * CPU * ()()()(DMA)() *nCPU nmax{x}+2 43 * REG+2CP DQT3 T2 T1 T0CLKResetSCP DQRCP DQRCP DQRCLK2-4T2 T3 T1 T0CP TQRCP TQ QRReset(1) T0 Tm-1P0 Pp-1 SR&Q * *44(2) * 1pp(=p) 1mm CPUnn * CPUResetT2T1T0P1P0QSCP DRQSCP DRQSCP DRCLK&QSCP DRQSCP DR45 CPU * CPUT2DMAQSCP DResetQCP DQCP DQCP DQCP DIDIRRSRSRSRSR&1&&End&DMADMAuOP&&53(3) *ALU 1Y (YALU) 2ALUZ *uOPs uOPCmd R1Y R2ALUOPALUALUZ R1outYin R2outOPZin(4) *(PC)+1PCuOPCmd PC PC+1 *1EnduOP([CPU]) EndPCPC+1ALUYZOP PC PCout,YClear,C-1,ADD,Zin Zout,PCinALUinALUout62 4JNZZFLAG (LD) RD[(RS)] RD[ADDR] (ST) [(RD)](RS)(ADD)RD(RD)(RS) RD(RD)[(RS)](JNZ)ZF0PC(PC)DISP ZF1PC(PC)1 REGREGREG

REGREGREGREGREGREG () RD1001RSDISP1110ADDRRD1000RSRD0100RSRD0001RD0000RS uOP CPU MEM70 * CPU *CPU () *uOP M+1 M+2 *** *** M P+1 P+2 MK Q+1 MK MM+1M+2NKPP+1P+2QQ+1ADDJMPCPU 722 * uOPs CM(uAR)-uIRuOPuARCMuOP IRIR uIRuOP-------uOPuOP ----------uAR73 *CPU CPUCPU DMAYYYNNN CPULDADDJMPYNDMAYNYN (IRREG) 3(DMA) () 772 uOPuOP * (log2) * n () uOP1 2 nuOP 1 2 p 78 * (log2) * + 1 2 puOP80 uOP410 1 2 3 40--1PCout2RSout3SEout4RDout5Zout6--MDRout0--1PCin2IRin3RDin4Yin5Zin6MARin7MDRin 0--1PC+12Read3--Write01ADD2WMFC3End3 3 2 2 1 2 3 4IR83 *uARfunc(,) ROM *uARF5uAR uARF4 ()85 CPU OP(0010) RD RS OP(11) DISP(1/):CPUI0I1I2I3()I3()0000001000110101011001111000100110101011110011101111 CM CM94 89 uOPCmd a a+1 a+2 uOP F uOPCmd PCout,MARin,ReadPC+1,WMFCMDRout,IRin b b+1 b+2 b+3 b+4001 110 10 00000 000 01 10110 110 10 00000 000 00 10110 011 00 110 b+10 b+20 b+30 b+40 a LD(I=1) PCout,MARin,ReadPC+1,WMFCMDRout,MARin,ReadWMFCMDRout,RDin,End001 110 10 00000 000 01 10110 010 00 000 a+10 a+21 *** 1 2 3 40--1PCout2RSout3SEout4RDout5Zout6--MDRout0--1PCin2IRin3RDin4Yin5Zin6MARin7MDRin 0--1PC+12Read3--Write01ADD2WMFC3End01992 * CM * CMEPROM *CM CMROM CM 1005.5 CPU1Intel 8086/8088 CPU * (8b/16b) (32b/64b) (8b) (8b/16b) *CPU () 16 80861680888(16CPU) (20+BHE) (20) (Byte) 3 1MB=log2(1MB/1B)=20min()2max()1012Intel 8086 CPU *EUBIU * 8/16/ ALUYZALU(16)FLAGEUEU 1 2 3 4 5 6Q(8)BIUCSDSESSSIP20AH ALBH BLCH CLDH DLSPBPDISIAXBXCXDXALU102 REG816REG488REG * IPPC () IR(EU) EUBIUREG(MARMDR) MARMDR() * 68REG - REG4() FLAGPSWREG ()1044Intel 8086 CPU *(--) * 80386CLK=5MHz *CLK T1 T2 T3 T4()T1 T2 T3 T3 T3 T4(+)1 : 1~51 : 3~51 : 1~21055.6 *:(IF)(OF)(EX)(WB):PCIRIDPSWREGxMEMALUPSWREGxPCMEM *tI1() [1]I1I2I2I3I3tI1() [3]I1I2I2I3I3I4I4I5I5I6I6Tt1t2tmm1~2REG1061 * * CISC CPU(ID)(IF)(EX)(OF)(WB) *0 1 2 3 4 5 n n+4()I1() WB EX OF ID IFI2I3I4I5I1I1I1I1I2I2I2I2I3I3I3I3I4I4I4I4I5I5I5I5InInInInIn Tn(mt)Tmt(n1)t-kk+1 kk+11072 (1) OP1RSRD1OP1RSRD1RTRTBAOP2RD2BAOP2RD2 ()RD3FRD3FCondCondREGRSRTRD3ABFPCMUXFCondMEMA/BRTRD3F1 2 3 4 5kk+1ALUREGMEMIDIMEMPCREGMEMPCALUREGMEMIDIMEMPCREGMEMPCIRIR107108 ALUREGMEMIDIMEMPCMUXIROP1RSRD1RTBAOP2RD2RD3FCond (2) IFIF/ID REGIDID/OF REGOFOF/EX REGEXEX/WB REGWB max{i}ti max{j}112 * MEML1 I-CacheBIUL2 Cache

JEUALUFPUWBOFOFIDIFIREX MOB IFOFWBWBL1 D-CacheL1 I-CacheIFOF/WBOFWBMOBWBIFOF/WB MOBL1-D$1132 *REGMEM 1 2 3 4 5 6I1R1=R2+R3 IF ID OF EX WBI2R4=R1+R3 IF ID OF EX WBR1R1 RAW (RAW) (Read After Write) 1 2 3 4 5 6 7 8 9 I1 IF ID OF EX WBI2 IF ID OF EX WBI3 IF ID OF EX WBIR1R1IFIDOFEXWB () *117I1I5I6I7I9I1I5I6I6(I1I5I6)I7I9 nop 1 2 3 4 5 6 7 8i IF ID OF EX WB

(xi+5) IF ID OF n IF ID OF EX WB IF ID OF EX WB IF ID OF EX EB IF ID OF EX119(t)I1WBEX2EX1IDIFI2I3I1I4I2I3I4I1I2I3I4I1I2I3 *Tmt+(n-1)t * t 1201 */(t)I1WBEX2EX1IDIFI2I3I1I4I2I3I4I1I2I3I4I1I2I3WBEX2-2EX2-1EX1-2EX1-1IDIF-2IF-1I1I1I1I1I1I1I2I2I2I2I2I2I3I3I3I3I3I4I4I4I4I4I3I4(0.5t)1/ P220 457(2)(3)8 P221 10111315 P222 19202123 --() REGALUREGMEMIDIMEMPCMUXIROP1RSRD1RTBAOP2RD2RD3FCond124